Abnormal interface state generation under positive bias stress in TiN/HfO2 p-channel
metal-oxide-semiconductor field effect transistors
Wen-Hung Lo, Ting-Chang Chang, Jyun-Yu Tsai, Chih-Hao Dai, Ching-En Chen, Szu-Han Ho, Hua-Mao Chen,
Osbert Cheng, and Cheng-Tung Huang
Citation: Applied Physics Letters 101, 133505 (2012); doi: 10.1063/1.4752456 View online: http://dx.doi.org/10.1063/1.4752456
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/101/13?ver=pdfcov
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Abnormal interface state generation under positive bias stress in TiN/HfO
2p-channel metal-oxide-semiconductor field effect transistors
Wen-Hung Lo,1Ting-Chang Chang,1,2,a)Jyun-Yu Tsai,1Chih-Hao Dai,3Ching-En Chen,4 Szu-Han Ho,4Hua-Mao Chen,5Osbert Cheng,6and Cheng-Tung Huang6
1
Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan
2
Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan
3
Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan
4
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
5
Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan
6
Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan
(Received 31 May 2012; accepted 30 August 2012; published online 27 September 2012)
This Letter studies positive bias stress-induced abnormal interface state on TiN/HfO2 p-channel
metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in Vthshift but without subthreshold slope degradation. However,
charge pumping current (ICP) shows a significant degradation after stress. Accordingly, the impact
ionization-induced Nit located HfO2/SiO2is proposed to demonstrate the ICPdegradation. The AC
stress with several frequencies is used to evidence the occurrence of impact ionization. Further, the device with additional pre-existing Nitlocated SiO2/Si has insignificant degradation due to reduction
in stress electric field.VC 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4752456]
The physical limitation of the silicon dioxide (SiO2) as
gate insulator has achieved the point where its thickness is approaching to a few atomic layers thick.1,2Below the physi-cal thickness 12 A˚ , the significant gate leakage current results in a volume active power consumption, leading a worse reli-ability of metal-oxide semiconductor field effect transistors (MOSFETs). To avoid this serious issue, high-k dielectrics have been introduced as hafnium (Hf)-base, zirconium, alumi-num oxides3–6and heavily investigated as a replacement for conventional SiO2gate insulator. However, metal gate/high-k
stack has to face many critical issues such as defects in high-k material, which can lead to undesired transport through the dielectrics and trapping-induced instabilities such as negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time-depended dielectric breakdown (TDDB), and hot carrier injection (HCI) in metal gate/high-k devices to realize the influence of high-k dielectric character-istics on devices under electric stress.7–13 However, for p-FETs, the behavior of off-state stress on gate/high-k devices has not yet been studied. Therefore, this Letter investigates the phenomenon for TiN/HfO2 p-MOSFETs under positive
bias stress (PBS). And we found that the stress-induced Nitis
generated at interface between high-k layer and buffer oxide, instead of channel interface.
The TiN/HfO2 p-MOSFETs were studied in this paper
based on the high-performance 28-nm CMOS technology. Both devices were fabricated using a conventional self-aligned transistor flow through the gate first process. For the gate first process devices, 10 A˚ and 30 A˚ of high quality ther-mal oxide were, respectively, grown on a (100) Si substrate as buffer oxide layers. After standard cleaning procedures, 30 A˚ of HfO2 films were sequentially deposited by atomic layer
deposition. Next, 10 nm of TiN films were deposited by radio frequency physical vapor deposition, followed by poly-Si dep-osition as a low resistance gate electrode. The dopant profile is1020cm3and1018cm3for source/drain and channel,
respectively, and activation were performed at 1025C. And the doping concentration of poly gate is 1020cm3. In this
study, the dimensions of the selected devices were 10 lm and 1 lm in width and length, respectively. The device with buffer thickness of 10 A˚ was subjected to the positive gate voltage (VG) condition with 2Vþflatband voltage (VFB). The stress
was briefly interrupted to measure the drain current-gate volt-age (ID-VG) and charge pumping current (ICP). All
experimen-tal data were measured using an Agilient B1500/B1530A semiconductor parameter analyzer.
Figure1shows the PBS-induced drain current (ID)-gate
voltage (VG) characteristic under semi-logarithmic scale of
TiN/HfO2 p-MOSFETs (device A). The stress condition VG
was selected 2 V, adding VFBto be a correction term. As the
result, the degradations on device during PBS show positive shift and decrease in threshold voltage (Vth) and drain current
(ID), respectively. The subthreshold slope (SS) is extracted by
ID ranges 107A to 109 A. In addition, the ID-VG under
semi-logarithmic scale shows a parallel shift at subthreshold region without stretch out, indicating invariant of SS after PBS. This is because the PBS-induced charge trapping is asso-ciated with amount of traps and stress electric field. As car-riers could rely on tunneling or/and thermal emission to cross oxide barrier height, charge trapping behavior should occur and no damaging interface state at Si/SiO2(Nit, Si/SiO2),
espe-cially for ultra-thin buffer oxide.10,11 Additionally, the C-V curve also shows the occurrence of electron trapping at high-k layer as shown in the inset of Figure1. It can be seen that the capacitance of gate terminal to body terminal versus gate volt-age (CGB-VG) curve exhibits a hysteresis window as VG
implements a dual-sweep (forward and reverse) before and
a)Author to whom correspondence should be addressed. Electronic mail: [email protected].
after PBS. According to experimental data, the window size seems to be invariant after PBS (red triangle). This behavior illustrates that stress condition did not result in additional bulk traps in high-k layer. However, charge pumping current (ICP),
which is another method to examine Nit, Si/SiO2has an
incon-sistent result with SS. Figure2shows the ICPshift for TiN/
HfO2p-MOSFETs under PBS and the SS degradation is also
shown for comparison. The gate pulse frequency (f) with 1 MHz is selected as ICPwas measured. It can be seen that the
shift of ICPis more significant than SS. According to the
pre-vious, ICPmeasurement with high frequency (<1 MHz) is
dif-ficult to examine the deep defects in high-k bulk due to insufficient charging time. The measurement condition of ICP
with f¼ 1 MHz we selected is mainly bounded to detect inter-facial defects, instead of deep bulk traps.14,15And then, CGB
has shown that there are not additional stress-induced deep defects in high-k layer as shown in the inset of Fig.1. Accord-ingly, ICPsignal must reflect the defects located at somewhere.
Based on those results, we would like to propose that interfa-cial defects could be generated under PBS located at HfO2/
SiO2interface (Nit, SiO2/HfO2). Due to the buffer SiO2layer is
10 A˚ , the pumping carriers come from source and drain
(S/D) have a probability to tunnel buffer oxide to approach HfO2/SiO2interface as ICPwas measured. Therefore, Nit, SiO2/ HfO2 could be detected by ICP with 1 MHz. To illustrate by
energy diagram, the electrons could tunnel from conduction band (ECB) into high-k layer, then gaining potential energy to impact interface of HfO2/SiO2, generating non-recovery
bro-ken bonds near that. According to continuity boundary condi-tions and the property of direct tunneling, we estimate the depth carriers could reach under stress voltage roughly as shown in the inset of Fig.2. The result demonstrates that the stress condition can make carriers cross through 14 A˚ for SiO2 dielectric layer under direct tunneling mechanism,
showing the consistency of assumption we mentioned. Since HfO2/SiO2 interface owns more incomplete or weak bonds
between high-k and buffer oxide, the stress condition could induce more additional Nit, SiO2/HfO2, instead of Nit, Si/SiO2. In
order to verify the impact-induced Nit, SiO2/HfO2 under PBS,
we introduce AC voltage into experiment. Under AC stress, Nit, SiO2/HfO2 should be degraded seriously as well as the
amount of Nit, SiO2/HfO2could be increased as stress frequency
increases. The stress condition was fixed VG¼ 2V þ VFBfor
frequency range of 1 kHz1 MHz to assure the corresponding result. Figure 3 shows the SS and ICP degradation for TiN/
HfO2 p-MOSFETs under PBS with different frequencies.
Obviously, the ICP degradation becomes more significant as
frequency increases, but SS degradation seems to be invariant regardless of modulating frequencies.
This is because under AC stress, carrier could be accel-erated and released repeatedly to enhance the probability of collision at HfO2/SiO2interface, and the reduction of stress
electric field due to interfacial (Nit, SiO2/HfO2) trapping is
in-significant than that under DC stress. Figure4shows IG
mea-surement by single pulse with period width (PW) 1 ls (0.5 MHz). It can be found that the corresponding gate current forms a rectangular wave with 1.3 lA. To compare gate cur-rent with the DC measurement as shown in the inset of Fig. 4, it shows a consistent value at gate voltage¼ 1.6 V, proving that electrons can transport from substrate to gate
FIG. 1. ID-VG transfer characteristic curves of TiN/HfO2 p-MOSFETs before and after PBS stress. The inset shows normalized CGB-VG curve before and after stress and corresponding energy band diagram for stress condition.
FIG. 2. The PBS-induced ICPand SS degradation for TiN/HfO2p-MOSFETs. The inset shows the equation for partial voltage for SiO2and initial SS value.
FIG. 3. The PBS-induced ICP and SS degradation for TiN/HfO2 p-MOSFETs were plotted as a function of AC stress frequency ranging of 0 Hz, 1 kHz, 100 kHz, and 1 MHz. The inset shows the corresponding energy band diagram for AC and DC stress condition.
under AC voltage, and without current decrease. Further, showing that impact ionization under AC stress is possible.
In detail, electrons can transport continuously from EC
to gate dielectric and result in electron trapping. After that, electron could be caught by Nit, SiO2/HfO2, influencing in the
energy band near SiO2as shown in the peak voltage (þ2V)
in inset of Fig.3. Due to transport continuously, interfacial electron trapping (Nit, SiO2/HfO2) could occur constantly,
even though electric field makes electrons tends toward gate by Poole-Frenkel emission. However, there is a transform of trapping behavior from interfacial states to deep states for AC condition, since AC stress exhibits peak (þ2V) and base voltage (0V). For peak voltage, the behavior on device is identical to DC condition. As application of stress voltage goes through base voltage, trapped electrons in Nit, SiO2/HfO2
have sufficient time to enter deep traps as shown in the inset of Fig.3. During long time term, reduction of electric field for DC stress condition is more significant than that for AC.10 Thus, significant degradation should be under AC stress. Additionally, due to possible conduction of electron, worse degradation occurs under high frequency, meaning more amount of pulse induces significant impact ionization. To combine those two causes, ICP under AC stress shows
more obvious degradation than that under DC. Besides, since the direct tunneling mechanism does not influence channel interface, thereby SS shows an insignificant degra-dation under AC PBS. Furthermore, we also compare the degradation mechanism of ICPunder PBS for TiN/HfO2
p-MOSFETs with more pre-existing Nit, Si/SiO2(device B) as
shown in Figure5. It could be seen that ICPdecay curve of
device B is more insignificant than that of device A under PBS, indicating that device B has less pre-Nit, Si/SiO2.
How-ever, stress condition VG is given a correction term to
achieve identical stress field, therefore the result should be consistent. But the experimental data are not consistent with this assumption. According to that, the stress electric field for device B is lower than device A is suggested. Clearly to explain, device B has a field screen by pre-Nit, Si/SiO2 to
decrease stress electric field. As electrons are accelerated to-ward gate by stress electric field, pre-Nit, Si/SiO2could trap
carriers randomly, reducing stress electric field as shown in
the inset of Fig.5. Because of that, it can results in insignifi-cant impact ionization, also leading less Nit, SiO2/HfO2 in
device B.
This Letter investigates the degradation of TiN/HfO2
p-MOSFETs under off-state stress. Clearly, electron trapping behavior dominates the characteristic of device, including positive Vthshift, decrease in IDbut without SS. However,
ICP measurement shows an inconsistent result with SS, and
we believe that the signal reflect the defect generation at HfO2/SiO2 due to impact ionization. According to simple
estimation, carriers can result impact near HfO2/SiO2
inter-face. And we found that ICP degradation increases as
fre-quency of AC voltage increases. This is because increase probability of collision at HfO2/SiO2interface, and then the
behavior of electric field lowering is insignificant. Therefore, the degradation increases with frequency increases, support-ing the model we proposed. Further, the influence of pre-existing Nit, SiO2/HfO2under PBS was discussed. The pre-Nit, Si/SiO2 can screen the stress field to reduce degradations of
device due to interfacial charge trapping.
Part of this work was performed at United Microelec-tronics Corporation. The work was supported by the National Science Council under Contract NSC99-2120-M-110-001 and NSC-97-2112-M-110-009-MY3.
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