Phase Interpolation
CP Loop
Filter
VCO
FRef PFD FOut
V Divider
VCDL
Vdiv
Vdiv p[k]
VDD Vx
ΔT
p[k]
V
Vx Vx
C
Vx`
VDD
Vdiv C
C
time τ
τ max
Vx` Vx`
p[k]
C
τ min p[k]
1
min p[k]
max
Design Consideration
• Reduce the time for signals to propagate g p p g through VCDL
ff
• Differential structure is used to improve immunity to supply and ground noise
• Linearity (INL / DNL) of the phase interpolator should be evaluated
should be evaluated
• The size of the circuit can be reduced byThe size of the circuit can be reduced by
employing the DAD technique or SDM phase interpolation method.
2
interpolation method.