DIGITAL CONTROL

DIGITAL CONTROL

MECHATRONICS (I) - PART II

WINTER 2019

YONG LEI

EMAIL: [email protected], OFFICE: 教⼀336

SYLLABUS

• Course Website: To be announced

• Prerequisites: Classic Control Theory, Linear Systems

• Textbook recommendations:

• Gene Franklin, J. David Powell, Michael L. Workman. Digital Control of Dynamic Systems, 3rd Edition. Addison-Wesley

• 张艳兵 等. 计算机控制技术. 国防⼯工业出版社

• 许勇 等. 计算机控制技术. 机械⼯工业出版社

• 胡寿松. ⾃自动控制原理理. 国防⼯工业出版社

!2

OBJECTIVES

•

To introduce the concepts of sampling,

discrete-time signals/systems, and the analysis and synthesis of digital control systems

• Upon completion of this course, you should be able to construct discrete-time models, design digital control algorithms and

analyze the open-loop and closed-loop behavior.

!3

MAJOR COURSE CONTENT

• Introduction to computer controlled systems

• Sampled data analysis

• Z-transform and the difference equations

• Discrete-time system representation and analysis

• Design of discrete time controller - input/output approaches

• Design of discrete time controller - polynomial approaches

• Design of discrete time controller - state space approaches

• Linear quadratic optimal control

• Kalman filter (if time permits)

• Final Project/Final Exam

!4

GRADING POLICY

• Grading:

• Midterm Exam I + Homework (linear systems): 50%

• Midterm Exam II: 20%

• Homework: 5%

• Final Project: 25%

!5

GRADING POLICY (CONT.)

• Homework:

• The homework will be assigned in the class and due on the following week, before the end of the class.

• Late homework policy: submit within 24 hours past due, 70%

credit maximum can be received. Submit after 24 hours past due, 50% credit maximum can be received

!6

FINAL PROJECT

• 1. Form a project team

• 2-3 people

• common hours for group meeting

• complementary skills (programming, modeling, technical writing, controls)

• Same level of commitment

• 2. Project proposal (due on the 3rd lecture)

• 1-2 pages, It should contain

• Course number and title

• Project name

• List of team members (Name&E-mail)

• Description of the project scope and tasks, Time table in weeks

!7

FINAL PROJECT (CONT.)

• 3. Project report

• Paper report with less than 25 pages, including text, figures, and equations)--graded

• Electronic report including electronic version of the printed report, the MATLAB/SIMULINK programs and software

documentation (if any) are due together with the paper report.

Archived and tested.

FINAL PROJECT EXAMPLES

• Ball and beam (Experiment)

• Induction motor

• Adaptive cruise control

CONTROL ISSUES TO BE ADDRESSED IN 
 FINAL PROJECT

• Plant (modeling) - system order, inputs/outputs

• Objectives - which output, to what level of accuracy.

• Sensors - noise level, cost.

• Actuators - saturation, actuator dynamics

• Communications

• Computing - PC, microprocessors, PLC, etc.

• Architectures and interface

• – Centralized/decentralized? Feedback/feed-forward?

• – Trade-off due to standard hardware/software protocols?

• Algorithms

• –  Control law

• –  Filters, observers, ...

• Disturbances and uncertainties

INTRODUCTION

DIGITAL CONTROL

WINTER 2019

MOTIVATION FOR CONTROL

• Feedback control has a long history which began with the early desire of

humans to harness the forces of nature, avoid hazardous/laborious/repetitive

work.

• Watt’s Fly Ball Governor had a major impact on the industrial revolution.

• Most modern systems (aircrafts, automobiles, production lines, CD

players, etc.) could not operate without the aid of control systems.

ME561 Lecture1- 3

Motivation for “Controls”

• Feedback control has a long history which began with the early desire of humans to harness the forces of nature, avoid

hazardous/laborious/repetitive work.

• Watt’s Fly Ball Governor had a major impact on the industrial revolution.

• Most modern systems (aircrafts, automobiles, production lines, CD players, etc.) could not operate without the aid of control

systems.

Photos from G. Goodwin’s lecture slides

COMPUTER CONTROLLED SYSTEMS

• Mechanical control systems – e.g., Watt’s Fly Ball Governor 


• Analog control systems


– e.g., Op-amp plus RC circuits based controllers. 


• Digital (computer) control systems 


COMPUTER CONTROLLED SYSTEMS

• Direct Digital Control(1960s)—implementation of PID control algorithms on large systems (chemical, power plants, space, military).

• Now, complex and 


intelligent algorithms.

ME561 Lecture1- 5

Computer Controlled Systems

• Direct Digital Control (1960s)—implementation of PID control algorithms on large systems

(chemical, power plants, space, military).

• Now, complex and intelligent algorithms.

From: W. Powers, AVEC 2000

7-Series BMW and S- class Mercedes boast about 100 processors

apiece.

MICROPROCESSOR BASED CONTROL SYSTEMS

• example on motor control

ME561 Lecture1-6

Microprocessor Based Control Systems -- example on motor control

Source: http://www.ti.com/sc/docs/psheets/diagrams/dmc.htm

AVIATION & AEROSPACE INDUSTRY

Apollo Navigation System, 1960x 1MHz, 16k RAM, 32k storage 


Multi-task OS, 8 tasks

Boeing 777, 1994, Boeing’s First full fly-by-wire System Airbus 320, 1984

First digital fly-by-wire commercial jet

Space Shuttle, 1977 All digital Fly-by-

Wire System

AD AND DA

ME561 Lecture1-7

AD and DA

r

Reference Computer

Plant

+ – Output

y u e

D/A A/D

Clock

Sampling (discretize in time)

Quantization ((discretize in magnitude)

Continuous Signal Discrete

Signal

1 2 3 4 5 6 7 8 9 10 kT

u

u(kT) u(t)

Average u(t)

INHERENTLY DISCRETE-TIME (SAMPLED) SYSTEMS

• Economic Systems

• Radar, GPS

• Accurate emission measurement of internal combustion engines, or some medical sensors.

• Internal combustion engines.

• Signals transmitted in nervous systems

• Systems with embedded computers or microprocessors.

• Production Systems

DISCRETE TIME DESIGN BY EMULATION

•

A simple way to design a discrete-time control system is to start with classical techniques to design a continuous-time compensator for a

plant. The continuous-time compensator can then be approximated with a discrete-time, sampled-

data system. This process is known as emulation.

EMULATION

ME561 Lecture1-20

Emulation (cont.)

Controller r C(s)

Plant G(s)

+ –

y u e

r G(s)

+ –

y Digitized

Control Algorithm u(t)

D/A A/D

Clock

≈ C(s)

u(kT) e(kT) e(t)

T

Emulation (indirect design)

Sample and hold

SAMPLE AND HOLD

ME561 Lecture1-21

Sample and Hold

Discrete-Time Control Systems, Ogata

A/D

• Several circuit design types

• Successive-approximation—n clock cycles for n-bit accuracy

• (Single-slope) Integration

• Counter (voltage to frequency)

• Parallel (Flash) encoding

ME561 Lecture1- 22

A/D

• Several circuit design types

– Successive-approximation—n clock cycles for n-bit accuracy – (Single-slope) Integration

– Counter (voltage to frequency) – Parallel (Flash) encoding

Figure 1-9 from Discrete -Time Control Systems, Ogata

The Art of Electronics, Horowitz and Hill, pp.415

ME561 Lecture1-22

A/D

• Several circuit design types

– Successive-approximation—n clock cycles for n-bit accuracy – (Single-slope) Integration

– Counter (voltage to frequency) – Parallel (Flash) encoding

Figure 1-9 from Discrete -Time Control Systems, Ogata

The Art of Electronics, Horowitz and Hill, pp.415

D/A

ME561 Lecture1-23

D/A

• Weighted resistors

• R-2R ladder circuit

The Art of Electronics, Horowitz and Hill, pp.410-411

EMULATION METHODS

•

Approximate continuous-time operations (e.g.,

differentiation) with discrete-time operations (e.g., difference).

•

– (Forward) Euler


– Trapezoidal with Pre-warp 
 – Matched pole/zero


– Zero-Order Hold (ZOH)

ME561 Lecture1- 25

Euler Approximation

& lim

x x

t

=

→

∆

∆

∆

0

&( ) ( ) ( )

x k x k x k

≈ + − 1 T where

T t t

t kT k

x k x t

x k x t

k k

k

k

k

= −

=

+

+

+ 1

1

(the sampling period in seconds), for a constant sampling period

is an integer,

is the value of at time , and is the value of at time .

( ),

( )

( )

ME561 Lecture1-26

Ex1_1 Emulation Using Euler Approximation

C s U s

E s K s a ( ) ( ) s b

= ( ) = + +

Controller r C(s) Plant

G(s)

+ –

y u e

( s b U s + ) ( ) = K s a E s ( + ) ( ) u b u & + = K e a e ( & + )

Euler approximation:

&( ) ( ) ( )

x k x k x k

≈ + − 1 T

u k u k

T b u k K e k e k

T a e k

( ) ( )

( ) ( ) ( )

+ − + ⋅ = L + − + ⋅ ( )

N M O Q P

1 1

u k ( + = − 1 ) ( 1 bT ) ⋅ u k ( ) + K aT ( − ⋅ 1 ) ( ) e k + ⋅ K e k ( + 1 ) u k ( ) = − ( 1 bT ) ⋅ u k ( − + 1 ) K aT ( − ⋅ 1 ) ( e k − + ⋅ 1 ) K e k ( ) or

u(k + 1) − u(k)

T + b ⋅ u(k) = K { e(k + 1) − e(k)

T + a ⋅ e(k)}

ME561 Lecture1-26

Ex1_1 Emulation Using Euler Approximation

C s U s

E s K s a ( ) ( ) s b

= ( ) = + +

Controller r C(s) Plant

G(s)

+ –

y u e

( s b U s + ) ( ) = K s a E s ( + ) ( ) u b u & + = K e a e ( & + )

Euler approximation:

&( ) ( ) ( )

x k x k x k

≈ + −1T u k u k

T b u k K e k e k

T a e k

( ) ( )

( ) ( ) ( )

+ − + ⋅ =

L

N M O Q P

1 1

u k ( + = − 1 ) ( 1 bT ) ⋅ u k ( ) + K aT ( − ⋅ 1 ) ( ) e k + ⋅ K e k ( + 1 )

u k ( ) = − ( 1 bT ) ⋅ u k ( − + 1 ) K aT ( − ⋅ 1 ) ( e k − + ⋅ 1 ) K e k ( )

or

SIMULATION OF EULER EMULATED CONTROLLER

ME561 Lecture1-27

Ex1_2 Simulation of Euler-Emulated Controller

Lead compensator

Controller r C(s) Plant

G(s)

+ –

y u e

C s s

( ) = s + 50 + 2 G s 10

( ) s s

( )

= +

1 1

Implement Euler-emulated digital controller at 10Hz and 30Hz x

x

x o

ME561 Lecture1-28

Ex1_2 MATLAB Implementation of the Continuous- Time System

% Construct the plant transfer function:

G_num = 1;

G_den = [1 1 0];

G = tf(G_num, G_den);

% Construct the compensator transfer function:

C_num = 50*[1 2];

C_den = [1 10];

C = tf(C_num, C_den);

% The open-loop transfer function can be simply calculated by:

OP = G*C;

% The closed-loop transfer function is:

CL = feedback(OP,1,-1);

% Or you can use the following arithmetic:

CL1 = OP / (1+OP);

% Or

CL2 = OP * inv(1+OP);

% The unit step response of the closed-loop system:

[y,t] = step(CL);

C s s

( ) = s + 50 + 2

10 G s( ) s s

( )

= +

1 1

Controller r C(s) Plant

G(s)

+ –

y u e

ME561 Lecture1-29

Ex1_2 SIMULINK Implementation of the Continuous- Time System

t Time

Step Scope

y

Response (Output)

1 s +s2

Plant

50(s+2) (s+10)

Lead Compensator Clock

ME561 Lecture1-30

Ex1_2 Discrete-Time System

Zero-Order Hold

t_digital Time

Step Scope

1 1 Sampling y_digital

Response (Output)

1 s +s2

Plant

50z+50*(-0.9333) z-0.6667

Discrete Implementation of the Lead Compensator

Clock

MATLAB: see notes Coefficients depend

on T

ME561 Lecture1-31

Ex1_2 Results

0 0 . 5 1 1 . 5

0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2

T i m e ( s e c )

Unit Step Response

A n a l o g C o n t r o l

D i g i t a l C o n t r o l ( 1 0 H z )

0 0 . 5 1 1 . 5

0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2

T i m e ( s e c )

Unit Step Response

A n a l o g C o n t r o l

D i g i t a l C o n t r o l ( 3 0 H z )

10Hz 30Hz

0 0.5 1 1.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

T i m e ( s e c ) ( b )

Unit Step Response

A n a l o g C o n t r o l

S a m p l e d D i g i t a l O u t p u t ( 5 H z ) A c t u a l O u t p u t

0 0.5 1 1.5

0 0.2 0.4 0.6 0.8 1 1.2

T i m e ( s e c ) ( a )

Unit Step Response

A n a l o g C o n t r o l D i g i t a l C o n t r o l ( 5 H z )

5Hz

ISSUES FOR DIGITAL CONTROL SYSTEMS

• Sampling time for emulated designs need to be at least about

20-30 times closed-loop bandwidth. Else inter-sampling behavior becomes questionable

• Clock Dependency.

• Aliasing (explained in more details later)

• Time delay due to Sample/Hold.

• Need for discrete-time models.

ME561 Lecture1-33

Ex1_3 Clock Dependency

Digitized Control Algorithm u(t)

D/A A/D

Clock ≈ C(s)

u(kT) e(kT) e(t)

T

0 1 2 3 4 5 6

0 0 . 2 0 . 4 0 . 6 0 . 8 1

Step Response

0 1 2 3 4 5 6

0 0 . 2 0 . 4 0 . 6 0 . 8 1

Step Response

T i m e

0 1 2 3 4 5 6

0 0 . 2 0 . 4 0 . 6 0 . 8 1

Step Response

0 1 2 3 4 5 6

0 0 . 2 0 . 4 0 . 6 0 . 8 1

Step Response

T i m e R e f e r e n c e S t e p

C o n t i n u o u s - T i m e R e s p o n s e D i g i t a l R e s p o n s e

( ) a C s = s a

+

Because sampling is often periodic, computer controlled systems will often result in closed- loop systems that are linear periodic systems.

SIDE NOTE

• Since sampling will lose information in between samples, digital control will always be inferior to its continuous-time counter part, i.e. we cannot expect better performance from digital control ...

• The above argument does not always apply ...

• Although sampling inevitably loses information, digital control do poses some unique design flexibility that are not achievable

through continuous-time LTI control

• Dead-beat control (see next page) is one example.

ME561 Lecture1-35

Ex1_4 Dead-Beat Control

Controller r

C(s) Arm

G_A( s)

y u

Amplifier k

Open-Loop Frequency Response

( ) _A ( ) k 2

G s k G s

= ⋅ = J s

Plant:

( ) bK ( ) s b ( )

U s R s K Y s

a s a

= − +

Control law: +

( )

( ) ( ) ( )

1

0 2

3 2

0 0 0

( ) 1

( ) ( ) 2 2 1

CL

Y s s G s

R s s s s

ω

ω ω ω

= = +

+ + +

0 1 2 3 4 5 6 7 8 9 10

0 0.5 1 1.5

Position

0 1 2 3 4 5 6 7 8 9 10

- 0.2 0 0.2 0.4 0.6 0.8

Velocity

0 1 2 3 4 5 6 7 8 9 10

- 1 - 0.5 0 0.5 1

Time

Control Input

Analog Control Response

0 1 2 3 4 5 6 7 8 9 10

0 0.5 1 1.5

Position

0 1 2 3 4 5 6 7 8 9 10

- 0.2 0 0.2 0.4 0.6 0.8

Velocity

0 1 2 3 4 5 6 7 8 9 10

- 1 - 0.5 0 0.5 1

Time

Control Input

Analog Control Response Digital Control Response Sampled Response

the sampling rate is 0.71 times the closed-loop bandwidth, 
 placing all closed loop zeros to the origin

ME561 F^ALL 2001

H. Peng and George T.-C Chiu ©1994- 2001 INTRODUCTION – 13

Alternatively, a digital controller of the form

u k ( ) = − ⋅ r u k

( − + ⋅ 1 ) t r k

( ) + ⋅ t r k

( − − ⋅ 1 ) s y k

( ) − ⋅ s y k

( − 1 ) (1.8)

can be design where the parameters r

, t

, t

, s

, and s

are determined base on the plant parameter and the sampling period T to achieve deadbeat performance. The response of the continuous-time disk drive servo with the digital controller, Eq. (1.8), is shown in Figure 1.13. Notice the superior performance of the digital controlled system. The position of the arm reaches the desired position in two sample steps without any overshoot. Also notice the sampling rate does not have to be an order of magnitude larger than the closed-loop bandwidth ω

. Specifically, the sampling rate in this case is 0.71 times the closed-loop bandwidth, i.e. T = 14 . ω . The system behavior under this

discrete control cannot be obtained with continuous-time controllers because of the solution to such systems are sums of functions that are products of polynomials and exponential functions.

Example 1.4 shows that control strategies with different system response can be obtained with digital control that are not possible to obtain with continuous-time linear time-invariant controls. In this particular example, the control strategy is called the deadbeat control. It is achieved by placing all the closed-loop poles of the discrete-time transfer function to the origin.

E E f f f f e e c c t t o o f f S S a a m m p p l l i i n n g g

Stable linear time-invariant systems have the property that their steady-state response to sinusoidal excitation is sinusoidal with the frequency of the excitation signal. Sampled-data system behaves in a more complicated manner because sampling will create signals with new (perceived) frequencies (aliasing) or exhibit beating phenomenon due to the interference between the input frequency and the sampling process. This (introduction of signals at different frequencies) can have adverse effect to the system performance if proper precautions are not taken.

Example 1.5 Aliasing/beating

Figure 1.14 shows the response of the digital filter system discussed in Example 1.3 under a sinusoidal input signal of frequency 4.9 Hz. The sampling rate for the system is set at 10 Hz. A beating of 0.1 Hz can be seen in the figure.

- 1 - 0 . 5

0 0 . 5

1

0 2 4 6 8 1 0

Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

Sampled Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

- 1 - 0 . 5

0 0 . 5

1

- 1 - 0 . 5

0 0 . 5

1

0 2 4 6 8 1 0

Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

Sampled Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

Sampled Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

Sampled Input

0 2 4 6 8 1 0

- 1 - 0 . 5

0 0 . 5

1

T i m e

Response

Figure 1.14 Sinusoidal Excitation of the Digital Filter in Example 1.3

ME561 Lecture1-36

Ex1_5 Aliasing/Beating

C(s)

u(t)

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Time

Response

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Time

Response

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Time

Response

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Time

Response

-1 -0.5

0 0.5

1

0 2 4 6 8 10

Input

-1 -0.5

0 0.5

1

0 2 4 6 8 10

Input

4.9 Hz sine wave

Digitized Control Algorithm u(t)

D/A A/D

Clock ≈ C(s)

u(kT) e(kT) e(t)

T

10 Hz sampling

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Sampled Input

0 2 4 6 8 10

-1 -0.5

0 0.5

1

Sampled Input

Proper selection of anti-aliasing filters is an important part of designing sampled-data systems. To avoid beating, the sampled signal should not have frequency components that

are (lower than but) close to the Nyquist frequency.

ME561 Lecture1-37

Time delay due to Sample/Hold

1 2 3 4 5 6 7 8 9 10 kT

u

u(kT) u(t)

Average u(t)

Delay ~ T/2 which deteriorates phase margin and damping

(see Example 1_6)

ME561 Lecture1- 38

Ex1_6

• ZOH introduces additional phase lag, which reduces the phase margin of the continuous-time design

– The amount of the phase lag is proportional to the frequency

• Device in digital feedback loop that reduces phase margin

– Hold circuits (D/A)

– Low-pass (anti-aliasing) filter

1 2 3 4 5 6 7 8 9 10 kT

u u(kT) ZOH signal u^H(t) u(t)

Averaged signal u(t)

[ ]

2

( ) 2

( ) ( )

T s

u t u t T

U s e⁻ U s

 

≈  − 

⇓

≈ ⋅

L i

( )

2

1 and

2

T T

j j

T

e

= R e

= − ω

ME561 Lecture1-39

Digital Control Design Process

Physical Process (Plant)

Select Sampling Frequency

Discrete-Time Control Model

Discrete-Time Controller Design

Performance

Evaluation & Analysis

Implementation

Continuous-Time Controller Design Continuous-Time

Control Model

Performance

Evaluation & Analysis

Select Sampling Frequency

Performance

Evaluation & Analysis

Detail Dynamic Model

(Simulation Model)

Direct Design Direct Design Indirect Design

Indirect Design

emulate