The Implementation of an Reed-Solomon Decoder with CPU Technology 吳泰宗、胡大湘
E-mail: [email protected]
ABSTRACT
The implementation of Reed Solomon decoding is realized by VHDL programming, which includes operations of CPU and RAM.
The firmware program operated in CPU is with MIPS instruction formats, and stored in a block of RAM. MIPS instructions with the length of 32 bits are employed in this firmware program, which contains syndrome computations, error location polynomial calculations, error location searches, and error corrections. In this work, we also design a codespim platform to modify some instructions and reduce the size of the firmware program. In such a way, the decoding speed is faster and implementation is realized with Modelsim.
Keywords : Reed-Solomon code
Table of Contents
封面內頁 簽名頁 中文摘要．．．．．．．．．．．．．．．．．．．．．．．iii 英文摘要．．．．．．．．．．．．．
．．．．．．．．．．iv 誌謝．．．．．．．．．．．．．．．．．．．．．．．．．．v 目錄．．．．．．．．．．．
．．．．．．．．．．．．．．vi 圖目錄．．．．．．．．．．．．．．．．．．．．．．．．viii 表目錄．．．．．．
．．．．．．．．．．．．．．．．．．ix 第一章 緒論 1.1 前言．．．．．．．．．．．．．．．．．．．．1 1.2 研究 動機．．．．．．．．．．．．．．．．．．1 1.3 全文架構．．．．．．．．．．．．．．．．．．2 第二章
Reed-Solomon碼原理 2.1伽羅瓦場(Galois Field)元素的建立與基本運算．．．3 2.1.1伽羅瓦場(Galois Field)基本四則運算．
．．． 5 2.2 Reed-Solomon碼定義與參數．．．．．．．．．．6 2.3 Reed-Solomon編碼演算法則．．．．．．．．．．7 2.3.1 生成多項式．．．．．．．．．．．．．．．7 2.3.2 Reed-Solomon編碼演算法則．．．．．．．．8 2.4
Reed-Solomon解碼演算法則．．．．．．．．．．9 第三章 微處理器的架構與運作方式 3.1微處理器的基本架構．．．
．．．．．．．．．．13 3.2其他功能區塊的介紹．．．．．．．．．．．．．15 3.3 微處理器的指令週期．．．．．．．
．．．．．16 3.4微處理器的指令說明．．．．．．．．．．．．．16 第四章 硬體實現與模擬比較 4.1 硬體電路設計．
．．．．．．．．．．．．．．．．．19 4.1.1加法器、乘法器的電路設計．．．．．．． 19 4.1.2除法器的電路設計．．
．．．．．．．．． 21 4.2說明利用自行撰寫的C語言程式轉換成組合語言指令．．23 4.3 Berlekamp-Massey解碼演算法則 結合與驗證及ModelSim與 PCSpim模擬之比較．．．．．．．．．．．．．．．．． 24 第五章 結論及未來展望 5.1 研究 流程與解決問題．．．．．．．．．．．．29 5.2 結論及未來展望．．．．．．．．．．．．．．29 參考文獻．．．．．
．．．．．．．．．．．．．．．．．．31 REFERENCES
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