The Impact of Gate-to-Source Tunneling Current on the Characterization
of Metal-Oxide-Semiconductor Field-Effect Transistor’s Hot-Carrier Reliability
Jone F. CHEN, Chih-Pin TSAO and T.-C. ONG1
Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, Tainan 701, Taiwan, R.O.C.
1Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C.
(Received September 17, 2002; accepted for publication December 14, 2002)
Drain current (Id) degradation due to Fowler-Nordheim (FN) stress and Vg¼Vdstress were investigated in 0.15mm n-channel
metal-oxide-semiconductor field-effect transistors (nMOSFETs) and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs). When pMOSFETs reach the lifetime under Vg¼Vd stress, the damage resulting from
gate-to-source tunneling current is not negligible in comparison with the damage caused by channel hot carriers. Id degradation
models of pMOSFETs under FN stress and Vg¼Vd stress were established. According to the Iddegradation models, the
impact of gate-to-source tunneling current on the result of hot-carrier reliability testing is discussed. [DOI: 10.1143/JJAP.42.2149]
KEYWORDS: MOSFET, hot-carrier, reliability, tunneling current, ultra-thin gate oxide
1. Introduction
Hot-carrier reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) is a major reliability concern to continued device scaling.1) Accelerated testing of hot-carrier reliability is usually carried out under the worst-case stress condition to evaluate the fastest device degradation. Recent studies show that Vg¼Vdis the worst-case condition during stress for both nMOSFETs and pMOSFETs.2–4) At the operating voltage (VDD), Li et al.5)reported that Isubmaxis the worst-case condition for both nMOSFETs and pMOS-FETs, but Morifuji et al.6)claimed that Vg¼Vdis the worst-case condition for pMOSFETs. Further, Li et al.7) reported that at VDD, Vg¼Vd is the worst-case condition for both nMOSFETs and pMOSFETs operated at 100C. Since the worst-case stress condition may vary due to different device design, process conditions, and operating temperature, reliability testing is recommended to be carried out at both Vg ¼Vd and Isubmax.
As ultra-thin gate oxide is used in state-of-the-art complementary metal-oxide-semiconductor field-effect tran-sistor (CMOS) technologies, a new concern arose for when the device is stressed under Vg¼Vd. Due to the high electric field which is applied between the gate and source, the damage near the source side resulting from the gate-to-source tunneling current may become comparable to the damage near the drain side caused by channel hot carri-ers.5,8)Such an effect can lead to misinterpretation of stress results because the damage to the device is no longer mainly due to channel hot carriers. To address this new concern, in this study we investigate the significance of the damage resulting from the gate-to-source tunneling current during hot-carrier reliability testing in both nMOSFETs and pMOSFETs. Further, Id degradation models were estab-lished to evaluate the impact of gate-to-source tunneling current on the result of hot-carrier reliability testing. 2. Experiments
nMOSFETs and pMOSFETs used in this study were fabricated using an advanced 0.15 mm dual-poly gate CMOS process with 2 nm gate oxide thickness (Tox). The gate length (L) and width of the devices are 0.15 mm and 10 mm, respectively. The forward-mode saturation Id measured at
Vg¼Vd¼VDD¼ 1:2 V was monitored. Although a high electric field (6 MV/cm) is applied between the gate and source when Vg ¼ 1:2 V, Idmonitoring shows that it does not influence the degradation of the devices because less than 0.02% in Id change is observed after performing 40 characterizations without application of stress in between. Devices were stressed at room temperature under various Vg with Vd¼Vg or Vd¼0 V. The stressing was interrupted periodically to measure Id degradation. Device lifetime is defined as the time required to reach 5% degradation in Id. 3. Results and Discussion
Iddegradation of nMOSFETs and pMOSFETs under Vg¼ Vd stress and FN stress is shown in Fig. 1. Two distinct trends are observed. First, gate-to-source tunneling current has a negligible impact on the result of Vg¼Vd stress in nMOSFETs, but this is not negligible in pMOSFETs. We assume the amount of damage resulting from gate-to-source tunneling current during Vg¼Vdstress is half of the damage under pure FN stress. When the device reaches 5% Id degradation during Vg¼Vd stress, the amount of Id degradation resulting from gate-to-source tunneling current is 0.006% and 0.6% for nMOSFETs and pMOSFETs,
2.0 2.5 3.0 3.5 4.0 0.01 0.1 1 10 100 5 0.012 1.2 2.3 2.75 NMOS NMOS PMOS Vd = Vg , PMOS Vd = 0V, PMOS Stress: t = 50min Vd = Vg , NMOS Vd = 0V, NMOS - ∆ I d / I d (%) |Vg| (V)
Fig. 1. Id degradation of nMOSFETs and pMOSFETs under Vg¼Vd
stress and FN stress for 50 min. The impact of gate-to-source tunneling current on the result of Vg¼Vdstress is negligible in nMOSFETs, but not
negligible in pMOSFETs. Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 2149–2151
Part 1, No. 4B, April 2003
#2003 The Japan Society of Applied Physics
respectively. Such a phenomenon mainly results from lower stress jVgj in nMOSFETs (2.3 V) than that of pMOSFETs (2:75 V). Since the mean free path of electrons is about twice that of holes,9) electrons can obtain sufficiently high energy to create damage under a lower jVdj(¼ jVgj) during Vg ¼Vd stress.
The second trend is that FN-stress-induced Iddegradation of nMOSFETs is lower under smaller jVgj stress but is projected to be greater than that of pMOSFETs when jVgj> 3:7 V. To explain this phenomenon, a carrier-separa-tion experiment was carried out under inversion condicarrier-separa-tions on nMOSFETs and pMOSFETs.10,11) The hole component (Igh) and electron component (Ige) of the tunneling gate current are drawn in Fig. 2. As seen in Figs. 1 and 2, the similarity of crossover in FN-stress-induced Id degradation and Igh around jVgj ¼3:7 V suggests that Iddegradation due to FN stress is highly related to Igh. Such an observation is consistent with the result reported in ref. 12 that a hole is two orders of magnitude more effective than an electron in activating traps which cause oxide breakdown. Because FN-stress-induced Id degradation is highly related to Igh, an Igh dependent model shown below is proposed to model the pMOSFET’s FN-stress-induced Id degradation:
ðId=IdÞFN ¼ ðA1ÞðIm1ghÞðt
n1Þ ð1Þ
A1, m1, and n1are technology-dependent parameters and t is the stress time. In our samples, A1 ¼2:0 1018, m1¼2:53, and n1¼0:30 can model degradation data reasonably well as seen in Fig. 3(a).
To evaluate the impact of gate-to-source tunneling current on the result of Vg¼Vd stress, modeling of Id degradation under Vg ¼Vdstress is also required. Since the total damage in the device is the sum of the damage resulting from gate-to-source tunneling current and the damage caused by channel hot carriers, Id degradation for pMOSFETs under Vg ¼Vd stress is modeled as the sum of two terms:
ðId=IdÞVg¼Vd¼0:5 ðA1ÞðI
m1 ghÞðt n1Þ þ ðA 2ÞðIgm2Þðt n2 Þ ð2Þ The first term in eq. (2) accounts for the degradation resulting from gate-to-source tunneling current. The second
term is the degradation caused by channel hot carriers where A2, m2, and n2 are also technology-dependent parameters. Note that gate current (Ig) during Vg¼Vd stress is used to model the Id degradation caused by channel hot carriers because the damage is the result of channel hot-hole injection.13,14)As seen in Fig. 3(b), the results of the model and data matched pretty well when A2¼1:8 107, m2¼1:09, and n2¼0:32 are used in eq. (2).
According to the measured Igh vs Vg and Ig vs Vg relationship (shown in Fig. 4), the lifetime of pMOSFETs as a function of Vgunder Vg¼Vdstress can be solved as a self-consistent solution for eqs. (1) and (2). Once the lifetime is obtained, the amount of Id degradation resulting from gate-to-source tunneling current can be estimated as the value calculated from the first term of eq. (2). Results of the above modeling are shown in Fig. 5. Data of lifetime under Vg¼ Vd stress and half of the Id degradation under FN stress for the pMOSFETs in Fig. 1 are also included in Fig. 5 to show that the above modeling is accurate. From Fig. 5, the impact of gate-to-source tunneling current on the characterization result of Vg¼Vd stress can be discussed. First, Id degrada-tion resulting from gate-to-source tunneling current has a peak around Vg¼ 3 V. Such a phenomenon can be explained by the crossover of Igh and Ig at Vg¼ 3 V as shown in Fig. 4. When the stressing jVgjis higher than 3 V, Igh is less than Ig. As a result, Iddegradation contributed by
2.5 3.0 3.5 4.0 10-10 10-9 10-8 10-7 PMOS NMOS NMOS I gh , PMOS I ge , PMOS Tox = 2nm Vd = 0V I gh , NMOS I ge , NMOS I (A/ µ m 2 ) |Vg| (V)
Fig. 2. The hole component (Igh) and electron component (Ige) of the
tunneling gate current in nMOSFETs and pMOSFETs under Vd¼0 V.
Around jVgj ¼3:7 V, crossover of Ighand FN-stress-induced Id
degrada-tion (in Fig. 1) between nMOSFETs and pMOSFETs is observed.
- ∆ I d / I d (%) 1 10 100 0.1 1 10 PMOS FN Stress: Vd = 0V Vg = -2.8V Vg = -3.0V Vg = -3.3V Vg = -3.6V Model:solid lines Time (min) - ∆ I d / I d (%) 1 10 100 1 10 PMOS Stress: Vg = Vd Vg = -2.7V Vg = -2.8V Vg = -3.0V Vg = -3.2V Model: solid lines
Time (min)
(a)
(b)
Fig. 3. Model and data of Id degradation for pMOSFETs under (a) FN
stress (b) Vg¼Vdstress at various stressing Vg. Good fitting suggests that
the modeling is reasonably good.
gate-to-source tunneling current is reduced. Second, under lower field stress conditions (i.e. stressing jVgj< 3 V), Id degradation resulting from gate-to-source tunneling current is reduced when the stress jVgjis lower. Specifically, if Vg¼ Vd stress is carried out under jVgj< 1:95 V, Id degradation resulting from gate-to-source tunneling current can be
controlled to be less than 0.25%, i.e. less than 5% of the total Id degradation.
4. Conclusions
The impact of gate-to-source tunneling current on the characterization result of Vg¼Vd stress is negligible in nMOSFETs, but not negligible in pMOSFETs. pMOSFET’s Id degradation due to FN stress and Vg¼Vd stress can be modeled by the hole component of the tunneling gate current and hot-hole gate current. To reduce the impact of gate-to-source tunneling current on the result of Vg¼Vd stress, stressing should be performed under a lower jVdj (¼ jVgj). Acknowledgements
This work is partially supported by the National Science Council under contract number NSC91-2215-E006-015.
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-2.0 -2.5 -3.0 -3.5 -4.0 10-9 10-8 PMOS I gh , Vd = 0V I g , Vg = Vd I ( A/ µ m 2 ) Vg (V)
Fig. 4. The hole component (Igh) of the tunneling gate current under
Vd¼0 V, and the hot-hole gate current (Ig) under Vg¼Vd in
pMOS-FETs. Note that the crossover of Ighand Igis observed at Vg¼ 3 V.
-2.0 -2.5 -3.0 -3.5 10-1 100 101 102 103 104 Lifetime ∆ Id / Id
Model: solid lines
Vg (V) Lif etime (min) 0.0 0.2 0.4 0.6 0.8 1.0 -1.95 0.25 PMOS - ( ∆ I d / I d ) gate-to-source (%)
Fig. 5. Model and data of lifetime for pMOSFETs under Vg¼Vdstress.
When the device reaches its lifetime, the amount of Id degradation
resulting from gate-to-source tunneling current is also estimated. Under lower field stress conditions, this Id degradation is reduced when the
stress jVgj(¼ jVdj) is lower.
