dip : in STD_LOGIC_VECTOR (3 downto 0)

(1)

--功能功能功能功能：：：：７７７７段左移段左移段左移段左移 --利用移位暫存器利用移位暫存器利用移位暫存器利用移位暫存器

-- project name: ch06/ex03 library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ex03 is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

position : out STD_LOGIC_VECTOR (3 downto 0);

seg7 : out STD_LOGIC_VECTOR (7 downto 0);

dip : in STD_LOGIC_VECTOR (3 downto 0);

pbsw : in STD_LOGIC);

end ex03;

architecture Behavioral of ex03 is

signal b2seg : STD_LOGIC_VECTOR (7 downto 0);

signal count_t : STD_LOGIC_VECTOR (23 downto 0);

signal clkm : std_logic;

signal shift_reg : STD_LOGIC_VECTOR (3 downto 0); --4bit 移位暫存器移位暫存器移位暫存器 移位暫存器 begin

div:process(clk) begin

if reset = '0' then

count_t <= (others => '0'); --暫停暫停暫停暫停 elsif rising_edge(clk) then

count_t <= count_t + 1;

end if;

clkm <= count_t(23);

end process;

--- move_position:process(clkm)

begin

if reset = '0' then

shift_reg <= "1110";

elsif rising_edge(clkm) then

(2)

shift_reg <= shift_reg(2 downto 0) & shift_reg(3); -- 左移左移左移左移 1bit end if;

end process;

position <= shift_reg;

---

b2seg <= "11000000" when dip ="0000" else --BCD 對對對７對７７７段解碼段解碼段解碼段解碼 "11111001" when dip ="0001" else

"10100100" when dip ="0010" else "10110000" when dip ="0011" else "10011001" when dip ="0100" else "10010010" when dip ="0101" else

"10000110" when dip ="1110" else "10001110" when dip ="1111" else "11111111";

---

seg7 <= b2seg when pbsw = '0' else "11111111"; --有按下則顯示有按下則顯示有按下則顯示有按下則顯示

end Behavioral;