Phoebe (Lo-Mei) Chang 3F., No.14, Ln. 201, Zhulin Rd., Yonghe Dist., New Taipei City 234, Taiwan (R.O.C.) Tel: +886-9-52125786

Phoebe (Lo-Mei) Chang

3F., No.14, Ln. 201, Zhulin Rd., Yonghe Dist., New Taipei City 234, Taiwan (R.O.C.)

Tel: +886-9-52125786 E-mail: [email protected]

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 Skills: C/C++, PHP, MATLAB, SystemC, Verilog

 Gender: Female Nationality: U.S.A Language: Chinese, English

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NATIONAL TAIWAN UNIVERSITY (NTU)

Bachelor, Department of Computer Science & Information Engineering 2004- 2008

 Major GPA: 4.00 Overall GPA: 3.91

 Ranked 6^th place out of 118 graduates

Master, Graduate Institute of Electronics Engineering, ICS Group 2008-

 Join GIEE on 2008 Fall

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 Low Power System Design for SoC Sept. 2007- Jun.2008 “System-Level Energy/Performance Simulation Framework for SoC”

- Provide the performance and power statistics for each SoC components via proposed design flow.

“Low Power Memory Hierarchy Design”

- Cache policy design of HotSpot Cache and line buffer Cache for multimedia applications.

Advisor: Prof. Chia-Lin Yang

 Electronics System Level (ESL) Design for SoC Jan. 2008-Jun.2008 “System Model for NOR Flash Memory”

- Build the system model of NOR flash memory with SystemC.

- Improve the speed of simulation and verification for the SoC system design.

Advisor: Prof. Liang-Gee Chen

 Motion Compensation Architecture Design July 2008-2009

“Bandwidth-Efficient Cache-Based MC Architecture Design for H. 264/AVC Decoder”

- Design a MC Architecture for H.264/AVC Decoder to reduce bandwidth efficiently.

- Two approaches:

 Cache-based MC architecture: exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared to conventional scheme.

 DRAM-friendly data access: DRAM-friendly data mapping and access control are designed to reduce the row pre-charge/active frequency and access latency of DRAM.

Advisor: Prof. Liang-Gee Chen

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 Presidential Award [Top 5% in NTUCSIE academic performance out of 146] (2006)

 Honorable Mention, IC Design Contest - Cell Based Design Category (2009)

 Winner, 47nd DAC/ISSCC Student Design Contest (2010)

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 Tzu-Der Chuang, Lo-Mei Chang, Tsai-Wei Chiu, Yi-Hau Chen and Liang-Gee Chen, "Bandwidth- Efficient cache-based motion compensation architecture with DRAM-friendly data access control ", in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.

2009 – 2012, May 2009.

 Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen and Liang-Gee Chen, "Low Bandwidth Decoder Framework for H.264/AVC Scalable Extension", in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2960–2963, May 2010.

 Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen and Liang-Gee Chen, "A 59.5mW Scalable/Multi-view Video Decoder Chip for Quad/3D Full HDTV and Video Streaming Applications", in IEEE International Solid-State Circuits Conference (ISSCC), 2010.

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 GRE (General) V: 157(73%) Q: 169(99%) AWA: 3(11%) 5/2013

 TOEFL (iBT) R: 28 L: 30 S: 23 W: 24 Total:105 6/2013

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 Art design & Publisher, CSIE Council (student association), National Taiwan University 2005-2007

 Secretary, Bridge club at National Taiwan University 2005-2007

 the 45th Pacific Asia Bridge Federation Championship (Taiwan Team) 2007

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 Contract bridge, Volleyball, Photography