Chapter #9: Finite State Machine Optimization

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Chapter #9: Finite State Machine Optimization

Contemporary Logic Design

Randy H. Katz

University of California, Berkeley

July 1993

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• Procedures for optimizing implementation of an FSM State Reduction

State Assignment

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(1) Understand the problem (2) Obtain a formal description (3) Minimize number of states (4) Encode the states

(5) Choose FFs to implement state register (6) Implement the FSM

This Chapter!

Next Chapter

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Odd Parity Checker: two alternative state diagrams • Identical output behavior on all input strings

• FSMs are equivalent, but require different implementations • Design state diagram without concern for # of states,

Reduce later

0

S0 [0]

S1

[1] S2

[0]

1 S0

[0]

S1 [1]

0

1

0 0

0 1 1

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Implement FSM with fewest possible states • Least number of flipflops

• Boundaries are power of two number of states

• Fewest states usually leads to more opportunities for don't cares • Reduce the number of gates needed for implementation

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Identify and combine states that have equivalent behavior

Equivalent States: for all input combinations, states transition to the same or equivalent states

Odd Parity Checker: S0, S2 are equivalent states Both output a 0

Both transition to S1 on a 1 and self-loop on a 0

Algorithmic Approach

• Start with state transition table

• Identify states with same output behavior

• If such states transition to the same next state, they are equivalent

• Combine into a single new renamed state

• Repeat until no new states are combined

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Example FSM Specification:

Single input X, output Z

Taking inputs grouped four at a time, output 1 if last four inputs were the string 1010 or 0110

Example I/O Behavior:

X = 0010 0110 1100 1010 0011 . . . Z = 0000 0001 0000 0001 0000 . . .

Upper bound on FSM complexity:

Fifteen states (1 + 2 + 4 + 8)

Thirty transitions (2 + 4 + 8 + 16)

sufficient to recognize any binary string of length four!

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State Diagram for Example FSM:

Reset

0/0 1/0

0/0 1/0 0/0 1/0

0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0

0/0 1/0 0/0 0/0

1/0 1/0 0/0

1/0

0/1

0/0 1/0

1/0 0/0 1/0 0/1

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S

₁₃

S

₁₄

Input Sequence

X =0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

X =0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

X =1

0

X =0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

X =1

0

₁₀

Input Sequence

Reset 0 1 00 01 10 1 1 not (01 1 or 101) 01 1 or 101

'

S

₇

'

'

S '

₁₀

Input Sequence

Reset 0 1 00 01 10 1 1 not (01 1 or 101) 01 1 or 101

'

S

₇

'

S '

₁₀

S '

₁₀

S

₇

'

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Final Reduced State Transition Table

Corresponding State Diagram

Input Sequence Reset 0 1 00 or 11 01 or 10 not (011 or 101) 011 or 101

Present State S0

S1 S2 S3' S4' S7' S10'

X=0 S1 S3' S4' S7' S7' S0 S0

X=1 S2 S4' S3' S7' S10'

S0 S0

X=0 0 0 0 0 0 0 1

X=1 0 0 0 0 0 0 0

Reset

S1

S3'

S7'

S2

S4'

S10' 0,1/0

0,1/0 0/0

0/0

1/0 1/0 1/0

1/0

0/1 1/0 S0

0/0

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• Straightforward to understand and easy to implement

• Problem: does not allows yield the most reduced state table!

Example: 3 State Odd Parity Checker

No way to combine states S0 and S2 based on Next State Criterion!

Present State S ₀

S ₁ S ₂

Next State X =0

S ₀ S ₁ S ₂

X =1 S ₁ S ₂ S ₁

Output 0 1 0

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New example FSM:

Single input X, Single output Z

Output a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

Enumerate all possible combinations of states taken two at a time

Naive Data Structure:

Xij will be the same as Xji

Also, can eliminate the diagonal

Implication Chart Next States

Under all Input

Combinations

S0 S1 S2 S3 S4 S5 S6

S1 S2 S3 S4 S5 S6

S0 S1 S2 S3 S4 S5

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Entry Xij — Row is Si, Column is Sj

Si is equivalent to Sj if outputs are the same and next states are equivalent

Xij contains the next states of Si, Sj which must be equivalent if Si and Sj are equivalent

If Si, Sj have different output behavior, then Xij is crossed out

Example:

S0 transitions to S1 on 0, S2 on 1;

S1 transitions to S3 on 0, S4 on 1;

So square X<0,1> contains entries S1-S3 (transition on zero) S2-S4 (transition on one)

S1-S3 S2-S4 S0

S1

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Starting Implication Chart

S2 and S4 have different

I/O behavior This implies that S1 and S0 cannot

be combined S1

S2 S3 S4 S5 S6

S0 S1 S2 S3 S4 S5

S1-S3 S2-S4 S1-S5 S2-S6

S3-S5 S4-S6 S1-S0

S2-S0

S3-S0 S4-S0

S5-S0 S6-S0

S1-S0 S2-S0

S3-S0 S4-S0

S5-S0 S6-S0

S0-S0 S0-S0

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Results of First Marking Pass

Second Pass Adds No New Information S3 and S5 are equivalent

S4 and S6 are equivalent

This implies that S1 and S2 are too!

Reduced State Transition Table Reduced State Transition Table

Input Sequence Reset 0 or 1 00 or 10 01 or 1 1

Present State S

₀

S

₁

' S

₃

' S

₄

'

X =0 0 0 0 1

X =1 0 0 0 0 Next State Output

S0-S0 S0-S0 S3-S5

S4-S6

S0-S0 S0-S0

S1 S2 S3 S4 S5 S6

S0 S1 S2 S3 S4 S5

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State Diagram

Symbolic State Diagram

Present State

S ₀ S ₁ S ₂ S ₃ S ₄ S ₅

Next State 00

S ₀ S ₀ S ₁ S ₁ S ₀ S ₁

01 S ₁ S ₃ S ₃ S ₀ S ₁ S ₄

10 S ₂ S ₁ S ₂ S ₄ S ₂ S ₀

1 1 S ₃ S ₅ S ₄ S ₅ S ₅ S ₅

Output 1 0 1 0 1 0 S0

[1]

S2 [1]

S4 [1]

S1 [0]

S3 [0]

S5 [0]

10

01 11 00

00 01

11 10

10 01 00 11

10

00

01 11

00

11 10

01

10

01 11

00

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Implication Chart

Minimized State Table

Present State

S ₀' S ₁ S ₂ S ₃'

Next State 00

S ₀' S ₀' S ₁ S ₁

01 S ₁ S ₃' S ₃' S ₀'

10 S ₂ S ₁ S ₂ S ₀'

1 1 S ₃' S ₃' S ₀' S ₃'

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1 S1-S3 S2-S2 S3-S4

S0-S0 S1-S1 S2-S2 S3-S5

S0

S0-S1 S3-S0 S1-S4 S5-S5

S0-S1 S3-S4 S1-S0 S5-S5

S1

S1-S0 S3-S1 S2-S2 S4-S5

S2

S1-S1 S0-S4 S4-S0 S5-S5

S3 S4

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Does the method solve the problem with the odd parity checker?

Implication Chart Implication Chart

S0 is equivalent to S2

₁

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The detailed algorithm:

1. Construct implication chart, one square for each combination of states taken two at a time

2. Square labeled Si, Sj, if outputs differ than square gets "X".

Otherwise write down implied state pairs for all input combinations

3. Advance through chart top-to-bottom and left-to-right. If square Si, Sj contains next state pair Sm, Sn and that pair labels a square already labeled "X", then Si, Sj is labeled "X".

4. Continue executing Step 3 until no new squares are marked with

"X".

5. For each remaining unmarked square Si, Sj, then Si and Sj are equivalent.

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When FSM implemented with gate logic, number of gates will depend on mapping between symbolic state names and binary encodings

4 states = 4 choices for first state, 3 for second, 2 for third, 1 for last = 24 different encodings (4!)

Example for State Assignment: Traffic Light Controller

Symbolic State Names: HG, HY, FG, FY 24 state assignments

for the traffic light controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

C 0 X 1 X X 1 0 X X X

TL X

0 1 X X 0 X 1 X X

TS X X X 0 1 X X X 0 1

Inputs Present State Q ₁ Q ₀

HG HG HG HY HY FG FG FG FY FY

Next State P ₁ P ₀

HG HG HY HY FG FG FY FY FY HG

Outputs ST

0 0 1 0 1 0 1 1 0 1

H ₁ H ₀ 00 00 00 01 01 10 10 10 10 10

F ₁ F ₀ 10 10 10 10 10 00 00 00 01 01

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State Maps: similar in concept to K-maps

If state X transitions to state Y, then assign "close" assignments to X and Y

S ₀

S ₁ S ₂

S ₃

S ₄

0 1

Q ₁Q ₀

00 01 1 1 10 0

1 Q ₂

S ₀ S ₄ S ₃ S ₁ S ₂ State Map State Name

S ₀ S ₁ S ₂ S ₃ S ₄

Assignment Q ₂

0 1 1 0 0

Q ₁ 0 0 1 1 1

Q ₀ 0 1 1 0 1 Assignment

Q ₁Q ₀

00 01 1 1 10 Q ₂

0 1

S ₀ S ₁ S ₃ S ₂ S ₄ State Map State Name

S ₀ S ₁ S ₂ S ₃ S ₄

Q ₂ 0 0 0 0 1

Q ₁ 0 0 1 1 1

Q ₀ 0 1 0 1 1 Assignment

Assignment

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Minimum Bit Distance Criterion

13 7

Traffic light controller: HG = 00, HY = 01, FG = 11, FY = 10

yields minimum distance encoding but not best assignment!

Transition S0 to S1:

S0 to S2:

S1 to S3:

S2 to S3:

S3 to S4:

S4 to S1:

First Assignment Bit Changes

2 3 3 2 1 2

Second Assignment Bit Changes

1 1 1 1 1 2

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Alternative heuristics based on input and output behavior as well as transitions:

Adjacent assignments to:

states that share a common next state (group 1's in next state map)

states that share a common ancestor state (group 1's in next state map)

states that have common output behavior (group 1's in output map)

Highest Priority

Medium Priority

Lowest Priority

i/j i/k

i/j i/j

α

β

β β

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Example: 3-bit Sequence Detector

Highest Priority: (S3', S4') Medium Priority: (S3', S4') Lowest Priority:

0/0: (S0, S1', S3')

1/0: (S0, S1', S3', S4') Reset

S0 0,1/0

0,1/0

1/0

S1'

0/0

0/1, 1/0

S3' S4'

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Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

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Highest Priority: (S3', S4'), (S7', S10') Medium Priority:

(S1, S2), 2x(S3', S4'), (S7', S10') Lowest Priority:

0/0: (S0, S1, S2, S3', S4', S7') 1/0: (S0, S1, S2, S3', S4', S7') Another Example: 4 bit String Recognizer

Reset

S1

S3'

S7'

S2

S4'

S10' 0,1/0

0,1/0 0/0

0/0

1/0 1/0 1/0

1/0

0/1 1/0 S0

0/0

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00 = Reset = S0

(S1, S2), (S3', S4'), (S7', S10') placed adjacently

State Map Q1 Q0 Q2

0 1

00 01 11 10

S0

Q1 Q0 Q2

0 1

00 01 11 10

S0 S3'

S4'

Q1 Q0 Q2

0 1

00 01 11 10

S0 S3'

S4' S7' S10'

Q1 Q0 Q2

0 1

00 01 11 10

S0 S1 S3' S2 S4'

S7' S10'

Q1 Q0 Q2

0 1

00 01 11 10

S0

Q1 Q0 Q2

0 1

00 01 11 10

S0

S7' S10'

Q1 Q0 Q2

0 1

00 01 11 10

S0 S3'

S4'

S7' S10'

Q1 Q0 Q2

0 1

00 01 11 10

S0 S1 S3' S2 S4'

S7' S10'

(a) (b)

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First encoding exhibits a better clustering of 1's in the next state map

Q ₂Q ₁ Q ₀X

P ₀ Q ₂Q ₁

Q ₀X

P ₀ Q ₂Q ₁

Q ₀X

P ₁ P ₂

P ₁ Q ₂Q ₁

Q ₀X Q ₂Q ₁

Q ₀X

( S ₀) ( S ₁) ( S ₂) ( S ₃' ) ( S ₄' ) ( S ₇' ) ( S ' ₁₀)

0 0 00

01

00 01 1 1 10

1 1 10

0

0 0

0 0 0 1 1 0

0

X X

P ₂

00 01

00 01 1 1 10

1 1 10

0

1 1

1 1 1 1

X X

00 01

00 01 1 1 10

1 1 10

1 1 1 1

0 0 0 0

X X 1 1 ( S ₀)

( S ₁) ( S ₂) ( S ₃' ) ( S ₄' ) ( S ₇' ) ( S ' ₁₀)

000 001 101 01 1 1 1 1 010 1 10

X = 0 001

01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000 Current

State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001

01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000 Current

State

Next State

1 1 0 0

1 1 0 0 0

0 1 Q ₂Q ₁

Q ₀X 00

01

00 01 1 1 10

1 1 10

0

0 0

0 1 0 0 1 1

1

1 1

00 01

00 01 1 1 10

1 1 10

0

0 1

X X 0 0

0 1

00 01

00 01 1 1 10

1 1 10

1 0 0 1

0 1 1 1

0 0 X X

1 0 0 0 X

0 0 X

0 0 0 0 1