Magamp application and limitation for multiwinding
flyback converter
C.-C. Wen and C.-L. Chen
Abstract: A new magamp technique for multiwinding flyback converters is proposed. Ideal operating principle and analysis are presented. The practical circuit operation is limited due to the nonideal component characteristics. An analytical model for studying the phenomenon is provided. Based on the model, the mechanism of the boundary condition that causes the converter to be out of regulation is explored. Experimental verifications on a 20 W two-output flyback converter are conducted. They illustrate the effectiveness of the proposed magamp approach and the accuracy of the presented analytical model.
List of symbols
CC capacitance of RC clamp snubber
iM instantaneous current of LM
IMA average current of LM
IMPi peak current of LMat the end of the ith time interval
iP, i1, i2 instantaneous current of LKP, LK1 and LK2, respectively
IPA, I1A, I2A average currents of LKP, LK1 and LK2, respectively
IPPi, I1Pi, I2Pi peak currents of LKP, LK1 and LK2, respectively at the end of the ith time interval
I0 initial current of LMat the beginning of T1time interval
KP, K1, K2 inductance factors where Kp¼ LM/LKP, K1¼ LM/LK1and K2¼ LM/LK2+N22LSR LM: magnetising inductance of transformer LSR saturated inductance of saturable reactor
SR
N1, N2 turn ratios of transformer where N1¼ np/n1and N2¼ np/n2
T switching period
nP, n1, n2 winding turns of transformer for primary winding, secondary winding 1 and sec-ondary winding 2, respectively
Ti ith time interval where i is 1–5
VC voltage across CC
Vg input DC voltage
RC resistance of RC clamp snubber
VMi voltage across LM during the ith time
interval
V1, V2 output voltage 1 and 2 where
V1¼ N1 VO1, V2¼ N2 VO2
LKP, LK1, LK2 leakage inductances of transformer for primary winding, secondary winding 1 and secondary winding 2, respectively
1 Introduction
Among the variety of switching-mode power converters, the flyback converter is a favourite choice: for design engineers in low power applications. The major merits of the flyback converter are: low part count, effective cost, quick dynamic response and simple multi-output structure. In industrial design of the multi-output flyback converter, a weighted voltage control scheme is often used to maintain regulation for all outputs. However, it does not reduce the total output error by adjusting the weighting factors. It only shifts the error to the other outputs[1]. Another disadvantage is that it is hard to arrange the transformer structure to make the output voltage be in the centre of regulation. Some previous papers [2, 3] have improved the cross-regulation of the multi-output flyback converter. However, in some applica-tions, such as the onboard power supply of TFT-LCD monitor, stringent regulation is required to prevent the interference effect on the display panel. A postregulator is added to meet the regulation requirements. Among the different postregulation approaches, the magnetic amplifier (magamp) regulator has been popular for years. Compared with other postregulation schemes, the magamp postregu-lator is one of the most reliable, efficient and cost-effective solutions.
In recent decades, the magamp approach has mostly been applied in forward-type converters. Research on the use of the magamp for forward converters has also been widely reported, including: resetting methods, design guidelines and limitations[4–6]. There has been little research on the use of the magamp for flyback converters. A magamp technique for the flyback converter is presented in[7]. The main drawback is that the main output for the PWM feedback is restricted to the output with higher voltage, even with light rated output current. In this paper, a new magamp technique for flyback converters with multiple output windings is proposed [8]. The feedback loop and winding turn ratio can be chosen. This feature provides The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
rIEE, 2005
IEE Proceedings online no. 20040829 doi:10.1049/ip-epa:20040829
more freedom to achieve optimum performance. For a practical design, the operating condition is limited due to the nonideal characteristics of the components.
2 Basic operation principle
Figure 1 shows the diagram of the multiwinding flyback converter with a magamp output. For simplicity, a two-output flyback converter is presented. As we know, in forward converter, the secondary outputs of the main transformer can be viewed as voltage sources and transfer energy to each output simultaneously. However, in the flyback converter, the operating principle is completely different. The flyback transformer can be viewed as a current source. The current time-sharing technique is applied. Figure 2 shows some waveforms in continuous current mode assuming ideal components. The basic operations are described as follows.
In the time period dT, the main switch S1is on and the input voltage Vg charges the magnetising inductance LM, where d is the turn-on duty cycle and T is the switching period. In the flyback converter, the main transformer is not only a common transformer but also an inductor to supply the energy to the outputs. At this period, the saturable reactor SR is reset by the voltage difference between the reverse secondary winding voltage VS2 and the magamp controlled voltage VA.
During the time period d1T, the switch is turned off and the energy in the magnetising inductance is released to the output VO1. In this period, the diode D1 is on and the secondary winding voltage VS1 is clamped at the output voltage VO1. The saturable reactor SR is in the blocking state and is set with the voltage difference between the secondary winding voltage VS2and the output voltage VO2. Ideally the stored energy in the main transformer is only supplied to the output VO1.
As soon as the saturable reactor SR is saturated, the diode D2 comes on and the secondary winding VS2 is clamped at the output voltage VO2. Since the reflected voltage on the winding voltage VS1is lower than the output voltage VO1, the diode D1 becomes reverse bias and is turned off. As a result, ideally the stored energy of the main transformer is only transferred to the output VO2during the time period d2T. At the end of the switching period, the main switch is turned on again and the saturable reactor SR is reset ready for next switching period.
According to the above descriptions, the following equation is needed to be satisfied to ensure the magamp set operation:
VO1 n1 4
VO2
n2 ð1Þ
For the volt–sec and balance rule of the main transformer, we may have Vg d ¼ nP n1 VO1 d1þ nP n2 VO2 d2 ð2Þ dþ d1þ d2¼ 1 ð3Þ
where nP, n1and n2are winding turns for primary winding, output winding 1 and output winding 2, respectively.
To achieve continuity of magnetising current when the current flowing through output VO1is switched to VO2, the following equation is satisfied:
IO1nn1P d1 ¼IO2 n2 nP d2 þ1 2 Vg d T LM ð4Þ where IO1and IO2are the average current of output 1 and output 2, respectively.
Substituting (2) and (3) into (4) yields
d3þ p d2þ q d þ r ¼ 0 ð5Þ where p¼ ð V1 VgþV1þ V2 VgþV2Þ q¼2 LM T ðV2 V1Þ Vg I1 Vgþ V2 þ I2 Vgþ V1 þ V1 V2 ðVgþ V1ÞðVgþ V2Þ r¼ 2 LM T ðV2 V1Þ ðI1 V1þ I2 V2Þ Vg ðVgþ V1Þ ðVgþ V2Þ V1¼ nP n1 VO1; V2¼ nP n2 VO2; I1¼ n1 nP IO1; I2¼ n2 nP IO2 PWM control + + + − − − Vg VP nP iP VS1 V0 1 I02 i02 D1 C1 VA VSR D3 n2 S1 D2 C2 V02 VS 2 n1 i0 1 I0 1 LM + − − − − SR + + + mag−amp control 0 0
Fig. 1 Diagram of multiwinding flyback converter with a magamp output VS2 VSR VA iP i01 i02 dT d1T d2T t t t t t
Fig. 2 Some key waveforms in flyback converter with a magamp regulator
To solve the root d of the third-order (5), one may follow the procedure in the Appendix (Section 7). As soon as d is found, it would be easy to find d1and d2from (2) and (3). Figure 3 shows the relations of duty cycles versus load conditions that are applied to the example in Section 4.
Since it is hard to find a root of the third-order equation or a higher-order equation, approximation could be made by assuming that the current ripples are negligible. The approximate equation can be obtained from (4) by neglecting the last item
IP d ¼ I1 d1 ¼I2 d2 ¼ IMA ð6Þ
where IMA is the average magnetising current of transformer.
From (6), we find that the relations between duties and input/output depend on the average currents. This is a very interesting feature. In most topologies of switching mode power supplies, the relations are dominated by voltages rather than currents.
3 Analytical model with nonideal characteristics of components
In practical design, the performance of the flyback con-verter with magamp application is limited by the non-ideal characteristics of the components. Since the energy delivery for each output depends on the current sharing principle, some parasitic parameters such as leakage inductance and saturated inductance may limit the rate of current flow. These will not only constrain the number of outputs, but also the operating area under extreme load conditions.
An analytical model is now proposed to explore the internal mechanism and to investigate the critical factors that affect proper operation.
3.1
Circuit analysis of proposed analytical
model
To simplify the analysis, some reasonable assumptions are made: first, when the main switch and the diodes are turned on, they are considered as short circuits. The voltage drop of onresistance (Rds,on) of the main switch is negligible compared with the input voltage Vg. In the low output voltage application, the drops of the diodes could be lumped with the output voltages. Under the off state, they are represented as an open circuit.
Secondly, the main transformer can be represented as an ideal transformer with a magnetising inductance LM and equivalent leakage inductances, LKP, LK1 and LK2, corre-sponding to primary winding, secondary winding 1 and secondary winding 2, respectively. The voltage drops of the winding resistances are small enough compared with the input voltage Vg and output VO1 and VO2. They are neglected in the model.
Thirdly, the output capacitances C1, C2 and the capacitance of the clamp snubber CCare sufficiently large that the voltages across these capacitances could be considered to be constant during the switching cycle.
Finally, the behaviour of the saturable reactor SR can be modelled as an inductance LSR when saturated. During block operation, it could be viewed as an open circuit. The core loss due to the hysteresis characteristics is sufficiently small so that it can be neglected.
The equivalent circuit model of Fig. 1 is shown in Fig. 4 where all secondary quantities have been referred to the primary side. A typical RC clamp snubber circuit is added on the primary side to prevent high voltage stress due to the energy stored in the leakage inductance LKP.
Figure 5a shows the key waveforms that are simulated by the proposed equivalent model in normal continuous current mode. It would be easy to indicate that some current transition periods are inserted among every duty period in the previous ideal case. In particular, the time
3 2 I 01, A I 02, A I 01, A I 02, A I 01, A I 02, A 3 2 0.3 0.2 0.1 0 d d 1 d 2 0.4 0.6 0.2 0 3 2 0 0.2 0.4 0.6 a b c
Fig. 3 Duty cycles plotted against load conditions
Vg¼ 20 V, VO1¼ 3.3 V, VO2¼ 5 V, IO1¼ 0–3 A, IO2¼ 0–2 A
a duty d b duty d1 c duty d2 SR C2 V2 V1 N 2 2 C1 LM iM VM VC LK1 LKP Vg S1 DC RC CC LK2 i1 iP i2 D1 D2 N2 N 12 + + − − + + _ _ 2 SR L + −
interval in which diodes D1 and D2 are on is the most evident in real applications and deserves attention. As the load of output 2 increases the duty for output 2 also increases but the blocking time of the saturable inductor decreases. Under the extreme load condition, the blocking time becomes a minimum. Since the current rise time is limited by the leakage inductance and the saturated inductance, output 2 cannot obtain enough energy and becomes nonoperational. Figure 5b shows the key wave-forms under extreme load conditions.
3.1.1 T
1time interval: At the beginning of the T
1time interval, the main switch S1 is turned off. The magnetising current starts to charge outputs 1 and 2. At the same time the energy stored in the leakage inductance LKPis absorbed by the capacitor of the RC clamp snubber. The equivalent circuit during the T1interval is represented as that shown in Fig. 6a. Thus, one can obtain the following equations: iM¼ iP þ i1þ i2 ð7Þ iMðtÞ ¼ VM1 LM t þ I0 ð8Þ iPðtÞ ¼ ðVM1 VCÞKP LM t þ I0 ð9Þ i1ðtÞ ¼ ðVM1 V1ÞK1 LM t ð10Þ i2ðtÞ ¼ ðVM1 V2ÞK2 LM t ð11Þ
Substituting (8)–(11) into (7), we obtain VM1¼ðVM1 VCÞKP þ ðVM1 V1ÞK1þ ðVM1 V2ÞK2 ð12Þ VM VM 1− VM iM iP i 2 I2P 1 I1P 1 IPP 4 T1 −I0 T4 T5 T3 T2 IPP 5 =I0 I2P 2 I 2P 3 i 1 VM 4− VM 2 VM 3 VM 5 iM iP i1 i2 t t t t t t t t t t a b
Fig. 5 Key waveforms that are simulated by the proposed equivalent model a normal condition b boundary condition VC VM 1 DC iM iP i 2 iM iM i1 iP iP iM iM VM 4 i2 i2 V2 Vg i2 D1 V2 V1 V2 VM 2 LM VM 3 LM LK 1 LKP LKP LM VMS LM LK 1 LK 2 LK 2 LK 2 D 2 D 2 D 2 S 1 Vg S 1 D 2 N 2 LSR i 1 LKP LM LK 1 D1 V1 V2 LK 2 + + _ _ SR 2 N 2 LSR 2 N 2 LSR 2 N 2 LSR 2 + + _ _ + − SR SR SR + + + + _ _ _ _ + + + + − − − − + _ a b c d e
Fig. 6 Equivalent circuit for different time intervals
a T1time interval
b T2time interval
c T3time interval
d T4time interval
Solving (12) for VM1yields VM1¼
K1V1þ K2V2þ KPVC 1þ K1þ K2þ KP
ð13Þ At the end of the T1interval, T1is obtained from (9) by letting iP(T1)¼ 0. T1¼ LMI0 KP 1þ K1þ K2þ KP VCþ K1VCþ K2VC K1V1 K2V2 ð14Þ Substituting T1 and VM1 into (10) and (11), the peak currents of i1and i2at the end of T1are, respectively
I1P 1¼ K1 KP K2V2þ KPVC V1 K2V1 KPV1 VCþ K1VCþ K2VC K1V1 K2V2 I0 ð15Þ I2P 1¼ K2 KP K1V1þ KPVC V2 K1V2 KPV2 VCþ K1VCþ K2VC K1V1 K2V2 I0 ð16Þ In this period, the energy stored in the leakage LKP had been transferred to the RC clamp snubber. Assuming the voltage VCis constant, the energy will be dissipated by the resistance RC. The total power loss of snubber can be derived as follows: PRC¼ 1 T Z T1 0 VC iPðtÞ dt ¼LMI 2 0 2T ð1 þ K1þ K2þ KPÞVC KPðVCþ K1VCþ K2VC K1V1 K2V2Þ ¼V 2 C RC ð17Þ Solving (17), the voltage of the snubber capacitor CCis
VC¼ ðK1V1þ K2V2Þ þ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðK1V1þ K2V2Þ2þ 2LMRCI02ð1þK1þK2þKPÞð1þK1þK2Þ TKP q 2ð1 þ K1þ K2Þ ð18Þ
3.1.2 T
2time interval: As the current of LKP
decreases to zero, the diode DC is reverse biased and the operation enters the T2time interval. The equivalent circuit model is given in Fig. 6b. Similarly, the following equations can be obtained: iM ¼ i1þ i2 ð19Þ iMðtÞ ¼ VM2 LM t þ I1P 1þ I2P 1 ð20Þ i1ðtÞ ¼ ðVM2 V1ÞK1 LM t þ I1P 1 ð21Þ i2ðtÞ ¼ðVM2 V2ÞK2 LM t þ I2P 1 ð22Þ
Similarly, VM2can be found as VM2 ¼
K1V1þ K2V2 1þ K1þ K2
ð23Þ T2is also obtained from (21) by letting i1(T2)¼ 0.
T2¼ LMI0 KP 1þ K1þ K2 V1þ K2V1 K2V2 K2V2þ KPVC V1 K2V1 KPV1 VCþ K1VCþ K2VC K1V1 K2V2 ð24Þ Substituting (16), (23) and (24) into (22), we can obtain the peak current I2P2
I2P 2¼
K2ðV1 V2Þ V1þ K2V1 K2V2
I0 ð25Þ
3.1.3 T
3time interval: When the current of diode D
2decays to zero, the T3time interval begins. Only LM and LK2 have current through it. The equivalent circuit model during T3is shown in Fig. 6c. Similarly to the T1and T2 intervals, we have iM¼ i2 ð26Þ iMðtÞ ¼ VM3 LM t þ I2P 2 ð27Þ i2ðtÞ ¼ ðVM3 V2ÞK2 LM t þ I2P 2 ð28Þ
Solving (26)–(28), VM3can be derived as VM3¼
K2V2 1þ K2
ð29Þ Substituting (25) and (29) into (28), the peak current of i2at the end of T3is I2P 3¼ K2V2 LMð1 þ K2Þ T3þ K2ðV1 V2Þ V1þ K2V1 K2V2 I0 ð30Þ
3.1.4 T
4time interval: At the beginning of the T
4interval, the main switch turns on again and then the input starts to charge LM. Figure 6d shows the equivalent circuit model in the T4interval. As in the previous process, we have
iM¼ iP þ i2 ð31Þ iMðtÞ ¼ VM4 LM t þ I2P 3 ð32Þ iPðtÞ ¼ ðVM4þ VgÞKP LM t ð33Þ i2ðtÞ ¼ ðVM4 V2ÞK2 LM t þ I2P 3 ð34Þ Solving (31)–(34), VM4is VM4¼ K2V2 KPVg 1þ K2þ KP ð35Þ T4is obtained from (34) by letting i2(T4)¼ 0.
T4¼ LM K2 1þ K2þ KP V2þ KPV2þ KPVg ð K2V2 LMð1 þ K2Þ T3 þ K2ðV1 V2Þ V1þ K2V1 K2V2 I0Þ ð36Þ
And the peak current of iPat the end of T4can be found by substituting (35) and (36) into (33)
IPP4¼ KP K2 Vgþ K2Vgþ K2V2 V2þ KPV2þ KPVg ð K2V2 LMð1 þ K2Þ T3 þ K2ðV1 V2Þ V1þ K2V1 K2V2 I0Þ ð37Þ
3.1.5 T
5time interval: As long as the current i2
drops to zero, the diode D2 is off and the current loop through LMand LKPonly exists on the primary side. The equivalent circuit model is presented in Fig. 6e. Similarly, one may obtain
iM ¼ iP ð38Þ
iMðtÞ ¼ VM5
LM
iPðtÞ ¼
ðVM5þ VgÞKP LM
t þ IPP4 ð40Þ
Solving (38)–(40) for VM5yields VM5¼
KPVg 1þ KP
ð41Þ Substituting (37) and (41) into (40), the peak current IPP5is expressed by IPP5¼ KPVg LMð1 þ KPÞ T5þ KP K2 Vgþ K2Vgþ K2V2 V2þ KPV2þ KPVg K2V2 LMð1 þ K2Þ T3þ K2ðV1 V2Þ V1þ K2V1 K2V2 I0 ð42Þ
Due to the continuity of the inductor current in steady state operation, the following equation is satisfied:
IPP5¼ I0 ð43Þ
Substituting (43) into (42), one can obtain
T5 A T3¼ B I0 ð44Þ where A¼V2ð1 þ KPÞðVgþ K2Vgþ K2V2Þ Vgð1 þ K2ÞðV2þ KPV2þ KPVgÞ B¼LMV2ð1 þ KPÞðV1þ K2V1 K2V2þ KPV1þ KPVgÞ KPVgðV2þ KPV2þ KPVgÞðV1þ K2V1 K2V2Þ For a switching period T, we have
T ¼ T1þ T2þ T3þ T4þ T5 ð45Þ
Substituting (14), (24) and (36) into (45) yields
T5þ C T3¼ T D I0 ð46Þ where C¼ KPðVgþ K2Vgþ K2V2Þ ð1 þ K2ÞðV2þ KPV2þ KPVgÞ D¼LMðV1þ K2V1 K2V2þ KPV1þ KPVgÞ ðV2þ KPV2þ KPVgÞðV1þ K2V1 K2V2Þ T3and T5can be obtained by solving (44) and (46)
T3¼ Vgð1 þ K2Þ Vgþ K2Vgþ K2V2 T LMð1 þ K2Þ KP ðV1þ K2V1 K2V2þ KPV1þ KPVgÞ ðVgþ K2Vgþ K2V2ÞðV1þ K2V1 K2V2Þ I0 ð47Þ T5¼ V2ð1 þ KPÞ V2þ KPV2þ KPVg T ð48Þ
3.2
Analytical expression of boundary
condition
Based on the above analysis, the average currents of outputs 1 and 2 under the boundary condition are calculated as follows: I1A¼ 1 2T I1P 1 ðT1þ T2Þ ¼K1LMI 2 0 2KPT ðK2V2þ KPVC V1 K2V1 KPV1Þ ðVCþK1VCþK2VC K1V1K2V2ÞðV1þK2V1 K2V2Þ ð49Þ I2A¼ 1 2T I½2P 1ðT1þ T2Þ þ I2P 2ðT2þ T3Þ þ I2P 3ðT3þ T4Þ ¼E I1Aþ 1 2T I½2P 2ðT2þ T3Þ þ I2P 3ðT3þ T4Þ ð50Þ where E¼K2ðK1V1þ KPVC V2 K1V2 KPV2Þ K1ðK2V2þ KPVC V1 K2V1 KPV1Þ The solution of (50) can be obtained easily by substituting each individual item that has already been derived before. However, it is trivial and too complex to analysis the relation between I1A and I2A. To obtain an analytical expression of the boundary condition, some reasonable assumptions could be made. First, since T2 and T4 are transition periods, they could be neglected compared with T3. Secondly, the magnetising inductance LM is large enough, so that the can decay can be neglected during T3, i.e. I2P2EI2P3EI0. Finally, the leakage inductances LK1, LK2, LKP and the saturated inductance LSR are much smaller than the magnetising inductance LM, such that K1, K2and KP441.
Equation (50) can be approximated by I2A E I1Aþ
I0 T3
T ð51Þ
Equation (47) can be also approximated by T3 Vg Vgþ V2 T I0 LKP Vgþ V2 þðLK2þ N 2 2LSRÞðVgþ V1Þ ðV1 V2ÞðVgþ V2Þ ð52Þ Substituting (52) into (51) yields
I2A E I1Aþ Vg Vgþ V2 I0 I 2 0 T LKP Vgþ V2 þðLK2þ N 2 2LSRÞðVgþ V1Þ ðV1 V2ÞðVgþ V2Þ ð53Þ
Equation (53) will help us to understand the factors that affect the boundary condition in Section 4.
4 Experimental results
To illustrate the effectiveness of the previous analysis, some experimental results are given below. A 20 W two-output flyback converter is constructed having the following parameters: input range Vg 20 30 V output VO1 3:3 V =0 3 A output VO2 5 V =0 2 A switching period T 10 mS turn number nP=n1=n2 10=3=8 leakage inductance LKP=LK1=LK2 0:95=0:96=0:94 mH magnetising inductance LM 70 mH saturated inductance LSR 0:45 mH
The core number of the main transformer is EI33 from TDK corporation. The saturable reactor has eight turns and the core number is MP1506 from Allied Signal. The common used current reset scheme is applied to reset saturable reactor. The clamp snubber capacitance and resistance are 0.1 uF and 1 kO, respectively. The output diode D1is a Schottky diode SBL840 from Transys Electronics Limited and the diode D2 is a fast diode SF1004G from Taiwan Semiconductor
Co. Ltd. Since both output voltages are low, the voltage drops of diodes are taken into account in the simulations. The voltage drops of D1 and D2 under boundary load conditions are 0.1 V and 0.9 V, respectively.
Figure 7 shows some experimental waveforms under: (a) half load; (b) full load; (c) boundary load conditions. In Fig. 7, VP is the voltage across the primary winding of the transformer as shown in Fig. 1 and iO1, iO2 are the instantaneous currents of outputs 1 and 2, respectively. Figure 8 shows the boundary condition for the average output currents IO1and IO2with both the analytical model and experimental results. It is obvious that the experimental results are in good agreement with the proposed analytical model. We can find the boundary conditions when the output current IO2is a heavy load and IO1is a light load. On the left side of the boundary line, output 2 becomes out of regulation. The results also verify the effectiveness of (50). However, (50) is complex and trivial. The simplified (53) is more comprehensive and analytical. In (53), output currents I1Aand I2Aare a function of I0which depends on the load condition. The only nonideal factors that affect the boundary (53) are the leakage inductances LKP, LK2 and
Vp , 20 V /div Vp , 20 V /div Vp , 20 V /div iO 2, 2A /div iO 2 , 2 A /div iO 1 , 5 A /div iP , 2 A /div iO 2, 2 A /div iO 2 iO 1 iO 1 iO 2 iO 2 iO 1 iP iP iP iO 1, 5 A /div iP, 2 A /div iO 1, 5A /div iP , 2A /div T T T a b c
Fig. 7 Some experimental waveforms time scale is 1 ms/div
a half load: Vg¼ 20 V, IO1¼ 3 A, IO2¼ 2 A
b full load: Vg¼ 20 V, IO1¼ 1.5 A, IO2¼ 1 A
c boundary load: Vg¼ 20 V, IO1¼ 0.249 A, IO2¼ 2 A
2.0 1.5 1.0 0.5 0 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 prediction 1 2 3 1 2 3 experiment I 0 2, A 2.0 1.5 1.0 0.5 0 I 0 2, A 2.0 1.5 1.0 0.5 0 I 0 2, A I 0 2, A I 01, A 0 0.5 1.0 1.5 2.0 2.5 3.0 I 01, A 0 0.5 1.0 1.5 2.0 2.5 3.0 I 01, A 0 0.5 1.0 1.5 2.0 2.5 3.0 I 01, A a b c d
Fig. 8 Experimental results with different design conditions
a under Vg¼ 20 V, T ¼ 10 ms and n2¼ 8 T condition: 1 LSR¼ 0.45 mH, 2 LSR¼ 0.7 mH, 3 LSR¼ 1 mH b under Vg¼ 20 V, T ¼ 10 ms and LSR¼ 0.45 mH condition: 1 n2¼ 8 T, 2 n2¼ 7 T, 3 n2¼ 6T c under Vg¼ 30 V, T ¼ 10 ms and LSR¼ 0.45 mH condition: 1 n2¼ 8 T, 2 n2¼ 7 T, 3 n2¼ 6 T d under Vg¼ 20 V, T ¼ 6.67 ms and LSR¼ 0.45 mH condition: 1 n2¼ 8 T, 2 n2¼ 7 T, 3 n2¼ 6 T
the saturated inductance LSR. The current rise time is limited by these factors. Hence, the magnetising inductance LMcannot supply enough energy to output 2 beyond the boundary. The other factors of (53) are designed parameters such as the switching period T, input voltage Vg, output voltages V1, V2, turn ratio N2and the turns of the saturable reactor. Figure 8a–d show the effectiveness of the designed factors with different values compared to the original design.
In Fig. 8a, three different turns of saturable reactor are provided: condition 1 is the original value: 8 turns and LSR¼ 0.45 mH, condition 2 is 10 turns and LSR¼ 0.7 mH and condition 3 is 12 turns and LSR¼ 1 mH. It can be seen that the boundary lines move toward the right with increasing turns of the saturable reactor. This complies with the conclusion of (53) that the larger the leakage inductances and the saturated inductance are, the worse the boundary condition is. It seems that fewer turns of the saturable reactor are preferred. However, the side effects should be considered to reduce the saturated inductance. More reset current from the controller is needed when the turns of the saturable reactor are decreased. On the other hand, it reduces the volt–second blocking range of the saturable inductor.
Since the output voltages VO1and VO2are defined by the specification, the actual designed factors are the turn ratios for V1and V2. The turn ratio N1for the main output V1can be designed by the traditional approach. However, the turn ratio N2for the magamp output V2becomes a critical factor affecting the boundary. Figure 8b shows the effect with three different turns for winding 2 i.e. condition 1 is the original value: n2¼ 8 turns, condition 2: n2¼ 7 turns and condition 3: n2¼ 6 turns. As the winding turns of output 2 decrease, the voltage difference between V1and V2will be reduced. It can be observed from (53) that the third item in the right-hand side of the equation will be increased and the boundary lines are shifted to the right. The major reason is that reducing the voltage difference V1–V2across LK2will increase the current rise time. This factor becomes significant when the voltage difference is too small. To prevent this, one should increase the winding turns. However, this will increase the voltage stress on the output diode.
As the input voltage Vgis changed to a high line voltage (Vg¼ 30 V), all the boundary lines with the same conditions as in Fig. 8b are shifted to the left. This is because higher input voltage can speed up the current rise time. The effect is shown in Fig. 8c. This also means that the worse case condition is under the low line condition.
In Fig. 8d, the switching frequency is increased to 150 kHz, i.e. the switching period (T¼ 6.67 mS) becomes two-thirds of the original value. The boundary lines with the same conditions as in Fig. 8b are moved further towards the right. This is because the time period for the current distribution is further limited. This can be also explained by (53), that decreasing the switching period will also be increase the third item.
From the above discussions, the design becomes a trade-off problem. One should design the parameters carefully to obtain the optimum performance. However, under any condition, the minimum load requirement on output 1 is necessary to keep regulation. A simple and cost effective way to solve this issue is to add a preload on output 1. In this example, a 1 W preload is placed to meet the 1% regulation requirement. Figure 9 shows the cross-regulation of output VO1 andVO2 (without and with magamp, respectively). Output VO1 is controlled by the PWM feedback loop. The cross-regulation of output VO1 meets
the 1% (0.3–0.3%) regulation requirement for with and without magamp condition. On the other hand, the cross-regulation of output VO2without magamp control is varied from 16.9–16.9%. As the saturable reactor is added and the magamp feedback loop is enabled, the cross-regulation of output VO2 is well under 1% (0.4–0.4%) regulation requirement.
5 Conclusions
We have investigated the operation of the magamp postregulator in flyback converters with multiple output
3 3 3 2 2 3 2 2 −5.0 0 2.5 −2.5 5.0 −5.0 0 2.5 −2.5 5.0 −5.0 0 2.5 −2.5 5.0 I0 1, A I 0 2, A I0 1, A I0 2, A I0 1, A I0 2, A I0 2, A I0 1, A ∆V0 1 V0 1 % ∆V0 1 V0 1 % ∆V0 2 V0 2 % ∆V0 2 V0 2 % 20 10 0 −10 a b c d
Fig. 9 Cross-regulation of output VO1, VO2
a output VO1without magamp
b output VO2without magamp
c output VO1with magamp
windings. The circuit of the magamp regulator looks similar to that of the forward converters. But the operating principle is totally different. The output of the main transformer in the flyback converter is viewed as a current source. The energy is supplied to each output winding by the time-sharing approach. Due to the leakage inductances and the saturated inductance, the current rise time is limited so that some transition periods are inserted. The proposed analytical model effectively explains the mechanism of the regulation boundary. The experimental results matched the predicted boundary conditions. A simple analytical expres-sion is derived to explain the factors that affect the boundary lines, such as: leakage inductance, saturated inductance, switching frequency and input voltage. To maintain the regulation, a minimum load is required. Finally, the experimental example shows the effective of applying the magamp in the flyback converter. Both output regulations are excellent with a 1 W preload on output 1.
6 References
1 Chen, Q., Lee, F.C., and Jovanovic, M.M.: ‘Analysis and design of weighted voltage-mode control for a multiple-output forward con-verter’. APEC, San Diego, CA, USA, 1993, pp. 449–455
2 Maksimovic, D., and Erickson, R.: ‘Modeling of cross regulation in multiple-output flyback converters’. APEC, Dallas, TX, USA, 1999, pp. 350–356
3 Ji, C., Smith, K.M., Smedley, K.M., and King, K.: ‘Cross regulation in flyback converter: analytic model and solution’, IEEE Trans. Power Electron., 2001, 16, (2), pp. 231–239
4 Kotlarewsky, P.: ‘Beyond the limitation of reset control and square loop of materials for mag-amp post regulators’. High Frequency Power Conversion Conference, Toronto, Canada, 1991, pp. 129–139 5 Lee, J., Chen, D.Y., and Jamerson, C.: ‘Magamp post
regula-torsFpractical design considerations to allow operation under extreme loading conditions’, IEEE Trans. Power Electron., 1990, 5, (1), pp. 69–76
6 Tedder, R.M.: ‘Effects of converter type, reset method and core material on magamp regulator performance’. APEC, Baltimore, MD, USA, 1989, pp. 391–400
7 Nelson, O.N.: ‘Time share mag amp’. High Frequency Power Conversion Conference, San Diego, CA, USA, 1988, pp. 49–54 8 Wen, C.C., Chen, C.C., Chen, W., and Jiang, J.: ‘Magamp post
regulation for flyback converter’. PESC, Vancouver, Canada, 2001, pp. 333–338
7 Appendix
For a cubic equation
d3þ p d2þ q d þ r ¼ 0 ð54Þ
One may reduce (54) to the form by substituting for d with the value, xp/3.
x3þ a x þ b ¼ 0 ð55Þ
where a¼ (1/3)(3qp2
) and b¼ (1/27)(2p39pq+27r). Equation (54) with aba0 can be always solved by transforming it to the trigonometric identity. Let x¼ m cos y, then
x3þ ax þ b ¼ m3cos3yþ am cos y þ b
¼ 4 cos3y 3 cos y cosð3yÞ ¼ 0 ð56Þ Hence 4 m3¼ 3 am¼ cosð3yÞ b ð57Þ
from which it follows that: m¼ 2 ffiffiffiffiffiffiffi a 3 r ð57Þ cosð3yÞ ¼3b am ð58Þ
Any solution y1, which satisfies (59), will also have the solutions y1þ 2p 3 and y1þ 4p 3 The roots of (55) are
2 ffiffiffiffiffiffiffi a 3 r cos y1;2 ffiffiffiffiffiffiffi a 3 r cos y1þ 2p 3 ;2 ffiffiffiffiffiffiffi a 3 r cos y1þ 4p 3
Hence, the roots of (54) are 2 ffiffiffiffiffiffiffi a 3 r cos y1 p 3;2 ffiffiffiffiffiffiffi a 3 r cos y1þ 2p 3 p 3;2 ffiffiffiffiffiffiffi a 3 r cos y1þ 4p 3 p 3
