An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

(1)

2184 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 9, SEPTEMBER 2009

An Ultra-Wideband High-Linearity CMOS

Mixer With New Wideband Active Baluns

Pei-Zong Rao, Tang-Yuan Chang, Ching-Piao Liang, and Shyh-Jong Chung, Senior Member, IEEE

Abstract—A 2–11-GHz high linearity CMOS down-conver-sion mixer with wideband active baluns using 0.18- m CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highestIIP₃and IP1 dB, and exhibits more compact size than most published

studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9 1.5 dB, input 1-dB compres-sion point(IP1 dB) of 3.5 dBm, single-sideband noise figure of

15.5 dB, and third-order input intercept point(IIP3) of 6.5 dBm

under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 0.57 mm2.

Index Terms—Active baluns, CMOS, mixers, phase splitters, ultra-wideband (UWB).

I. INTRODUCTION

T

HE MIXER, which is responsible for frequency conver-sion, is an essential building block of transceivers. It is also an important component associated with the linearity of the front-end receivers. The first stage of mixer must have high lin-earity to handle the large input signals from the low-noise ampli-fier (LNA) without significant intermodulation [1]. Nonlinearity will cause many problems such as cross modulation, desensi-tization, harmonic generation, and gain compression [2]. The differential architecture can be used to reduce the even-order nonlinearity, but it is difficult to suppress the odd-order one, es-pecially for the third-order intermodulation distortion (IMD3), which is the dominant part of the odd-order nonlinearity.

The Gilbert cell is a typical type of active mixer. The Gilbert mixer consists of three stages: transconductor stage, switching stage, and load stage. The linearity of the Gilbert mixer will be dominated by the transconductor stage if the switching stage is ideal. Third-order input intercept point , second-order input intercept point , and input 1-dB compression point

are the principal parameters of linearity. and

Manuscript received November 27, 2008; revised May 06, 2009. First pub-lished August 11, 2009; current version pubpub-lished September 04, 2009. This work was supported by the National Science Council of Taiwan under Contract NSC97-2221-E-009-040-MY2.

The authors are with the Department of Communication Engineering, Na-tional Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: sjchung@cc. nctu.edu.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2009.2027079

Fig. 1. Block diagram of the proposed mixer.

are the effects of intermodulation terms in nonlinear circuits, and is the ceiling of the input power. In order to improve the linearity of the Gilbert mixer, many methods have been used such as adding source degeneration resistors below the gain stage [3], using a bisymmetric class-AB input stage [1] and mul-tiple gated transistor [2], and employing common-source and common-emitter RF transconductors [4].

In order to get higher conversion gain, good isolation, and better dynamic and static offsets, and help improve the second-and third-order intermodulation rejection, the double-balanced Gilbert mixer with differential RF, local oscillator (LO), and IF signals are commonly used for optimum operation [5]–[6]. Differential balun (or phase splitter) circuits play an important role in generating differential output signals, which charac-terize balanced amplitude and phase. Here are two distinct types of baluns, i.e., passive and active baluns. In general, the passive baluns have the advantage of consuming no dc power, and they are often implemented in the forms of LC networks or microstrip line transformers. The LC network baluns can be used in narrowband and the microstrip line transformers in wideband applications. However, both of them are lossy and expansive for larger physical size at frequencies below -band, which limit the practicability of the passive baluns in monolithic microwave integrated circuit (MMIC) designs. Conversely, the active baluns have the characteristics of more acceptable gain imbalance and phase imbalance in a wideband range. The compact size also makes the active baluns more suitable than passive baluns in integrated circuit designs.

Several types of active balun topologies have been proposed in the literature. Three configurations are commonly used: single field-effect transistor (FET) circuits, common-gate cas-caded with common-source (CGCS) circuits, and differential amplifier circuits. The challenge of the active balun design is to maintain an 180 phase difference and limit gain imbalance between the two output ports in a wide frequency range. The common-source single-FET type is the simplest configuration

(2)

Fig. 2. Completed circuit schematic of the proposed mixer with wideband active baluns.

of active baluns. When signals enter the gate, ideally the output signals at the drain and source will be out of phase by 180 and have equal amplitude. However, the parasitic capacitance of the FET makes the common-source FET difficult to achieve the required phase difference for wideband and high-frequency ap-plication. Examples can be found in [7] and [8] with operation frequency lower than 2 GHz. As for the second configuration, the CGCS circuit, its characteristics are low power consumption and adequate isolation. However, it does not have low phase error performance in broadband applications due to the para-sitic effects. An active phase splitter proposed in [9] adopted the common base/common emitter structure using the InGaP HBT foundry process, which exhibited a maximum amplitude error and a phase error up to 1.3 dB and 8 , respectively, at the personal communication system (PCS) frequency band (1850–1910 MHz).

For the third configuration, the differential amplifier balun circuit, the output signals are usually poor in equal amplitude and out-of-phase since the current source becomes an imper-fect open circuit at the high frequency. The leakage signal to the current source will cause the phase and gain imbalances. The over-driven voltage of the differential amplifier will also decrease the headroom of the output signals. Viallon et al. [10] utilized this configuration to implement an active balun with a very wide frequency range from 0.2 to 22 GHz. The drawback of their design is the large power consumption up to 166 mW.

In this paper, we proposed a new high linearity down-con-version mixer with wideband active baluns by using the stan-dard 0.18- m CMOS process. Detailed design information is presented. The adopted cascode CG and CS active balun is im-proved from the CGCS structure for better performance at high-frequency and wideband applications. This paper is organized as follows. In Section II, the equations describing harmonic terms in the feedforward transconductor are first derived from which one observes that the high linearity can be achieved by canceling

sented and compared to other wideband mixers using the similar technology. Finally, Section IV gives a conclusion with a brief summary of the proposed mixer.

II. CIRCUITDESIGN ANDANALYSIS

Fig. 1 illustrates the block diagram of the proposed mixer. It includes the mixer core (double-balanced mixer), two ac-tive baluns (modified CGCS baluns) for RF and LO ports, and an output buffer for the IF port. The mixer core uses the

LC folded cascode topology with differential transconductor

to improve the linearity. The active baluns also adopts the improved common gate that cascaded with common-source baluns to generate balanced RF and LO signals. The output buffer is a differential common-source amplifier for testing and matching purposes. All input/output ports are single ended so that the proposed mixer circuit can be directly combined with single-ended frond-end and back-end circuits.

A. Mixer Core

The completed circuit schematic of the high linearity mixer is shown in Fig. 2. The proposed mixer is based on a Gilbert cell mixer, which is composed of an LO switching stage – , an RF transconductor stage – , current mirrors, and IF buffer amplifiers.

The transconductor, as shown in Fig. 3, consists of two degenerate common-source transistors and two degenerate common-gate transistors , which used to be the input stage and achieve feed-forward distortion linearization [11]. This feedforward compensated differential transconductor has the function of providing accurate input impedance and high intermodulation intercepts, and has less distortion than the class-AB [12], multi-tanh [13], degenerated differential pair, and cascode compensation [14]. and , as will be described below, are used for suppressing the excited harmonics, and thus the nonlinearity, in the circuit. also

(3)

Fig. 3. Differential transconductor stage of the proposed mixer.

linearity was achieved, neither theoretical study, nor design formula was given there.

In order to analyze the nonlinear effects generated by the transconductor stage, the harmonic balance analysis started from the derivation of the output current. The output cur-rents and of the differential transconductor stage characterize a nonlinear relationship with the input voltages

and , where

is the dc-bias voltage of the input signals. The differential output current can be written as

(1) where to are the currents for transistors to . In this study, the third-order harmonic distortion canceling technique is adopted for achieving high linearity. To this end, the cancel-lation criterion for wideband applications is first derived based on the harmonic balance analysis.

Assume that all the FETs in Fig. 3 are operated in the satu-ration region with channel length modulation parameter . The currents and can be expressed as

(2) (3) where and are the threshold voltage and bias voltage, respectively. The transconductance parameter ( or ) is also given as

Reforming (2) and (3), one obtains

(4) and

(5)

where and .

Similarly, the currents and for and , respec-tively, can be derived as

(6) and

(7) Substituting (4)–(7) into (1), the differential output current turns out to be

(8) where and represent the amplitudes of the funda-mental and third-order harmonics, respectively. and can be found as

(4)

(10) The even-order harmonic distortion is canceled due to the dif-ferential architecture. The third-order distortion is the dominant part of the nonlinearity, and it may induce problems like inter-modulation, cross-inter-modulation, desensitization, and gain com-pression. All these higher order distortions deteriorate the cir-cuit linearity. The dc and second-order harmonics in (4)–(7) are canceled due to the differential architecture. It is seen from (10) that the amplitudes of the third-order harmonic become null if it follows that

(11) This means that the third-order distortion, which is the dom-inant part of the nonlinearity, can be eliminated if one designs the resistances and and the transconductance parame-ters and properly according to (11). The formula is pro-posed to provide design guidance for obtaining better linearity by canceling the third-order distortion. Based on the above cri-teria, the third-order harmonic of the differential output current becomes null. The fundamental amplitude can also be rewritten as follows:

(12) Formula (12) shows that the fundamental amplitude will enlarge when the resistor increases. However, with the unchanged transconductor parameter , (11) indicates that should be increased at the same time to meet the criteria if is increased. Meanwhile, (12) shows that the increased will lessen the fundamental amplitude due to the term though the term is enlarged. The method of increasing mixer gain at the same point is to find out the maximum under the consideration of in (12). Hence, in an attempt to find out the maximum mixer gain, and should be well chosen and is a tradeoff.

However, the mixer gain is proportional to the transconduc-tance , and higher overdrive voltage will get higher gain. Fur-thermore, the level of the supply voltage for the feedforward compensated differential transconductor is critical to keep the driver FETs always operated in the saturation region. To over-come this problem, the RLC folded cascode circuit is used as the load to get larger output voltage headroom [2], [3], [16], [17]. Since the inductor is short circuited at dc operation, this modi-fied LC folded load can still provide more voltage headroom for the output signal. The addition of the resistance in the LC tank helps to reduce the quality factor, and thus increase the

band-Fig. 4. Circuits of: (a) the conventional CGCS balun and (b) the cascode CG and CS balun.

Fig. 5. Small-signal equivalent-circuit model of cascode common-gate stage.

at this stage. The current signal is then down-converted by the switching pair. Finally, the RLC tank provides loading to the preceding stages and converts the current signals back to the voltage signals.

B. Wideband Active Balun

In this section, the adopted cascode CG and CS active balun is analyzed and compared to the conventional CGCS one. As shown in Fig. 4(a), a conventional CGCS balun consists of common-gate and common-source stages, whose advantages are low power consumption and adequate isolation. However, it gets too much phase error for broadband application.

To meet the bandwidth requirement in this study, the active balun, as illustrated in Fig. 4(b), is used, which is modified from the CGCS circuit by replacing the CG stage into a cascode CG stage to improve the phase error of differential output. The re-sistance is utilized for input matching to save the die area.

To demonstrate the superiority of the cascode CG and CS structure in wideband phase balance, the transmission phase (i.e., the phase of ) of the cascode CG structure is derived by using the small-signal equivalent circuit

(5)

respectively, in (13)–(15) at the bottom of this page, where

From the derived transmission phases, the phase imbalances for the conventional CGCS balun and the cascode CG and CS balun are obtained as follows:

Phase imbalance of conventional CGCS balun (16) Phase imbalance of cascode CG and CS balun

(17) Fig. 6 depicts the calculation results for the two circuits. Here, the process parameters given by the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, with 0.18- m CMOS technology are used ( ,

ms, fF, fF, ). It

is seen that, in the frequency range from 0 to 13 GHz, the phase

Fig. 6. Calculated phase imbalances of the conventional CGCS balun and cas-code CG and CS balun in Fig. 4.

TABLE I

COMPARISON OFACTIVEBALUNS

imbalance of the conventional CGCS balun is varied from 0 to 10 , while that of the cascode CG and CS balun is from 0 to 2.2 . Obviously, the latter has better performance than the former.

Table I summaries the performances of reported active baluns and this study. It is seen that the cascode CG and CS active balun

(13)

(14)

(6)

Fig. 7. Simulated amplitude imbalance and phase imbalance of the cascode CG and CS active balun with mixer core.

in this study has higher upper frequency bound than others, ex-cept [13]. The balun in [13] adopted the differential amplifier topology, and has a wideband range performance from 0.2 to 22 GHz. However, it consumed a very large power, which is 92 times the power used in this study. The main difference between the cascode CG and CS active balun and conventional one is the cascode common-gate stage. The common source stage char-acterizes high resistance with the reactance composed of para-sitic capacitance and in the transmission process. The large resistance and parasitic capacitance will lead to higher RC delay. Therefore, larger phase delay will be generated. As to the common gate stage, the resistance in the transmission process is approximate to with the reactance composed of parasitic capacitance of . Hence, its RC delay effect is less than the common source stage, especially for wideband application. The cascode common gate stage is used to add phase delay to ap-proach the tendency toward the phase variation of the common source stage when frequency varies. The cascode common-gate configuration is adopted to increase the phase delay to attain the bandwidth extension in the less phase error condition.

The simulated gain imbalance and phase imbalance of the cascode CG and CS active balun combined with the mixer core, presented in Section II-A, are shown in Fig. 7. The Agilent Ad-vanced Design System (ADS) simulated data show that in the bandwidth from 2 to 13 GHz, the gain imbalance is less than 2 dB (0.7–1.9 dB) and the phase imbalance is within 2 .

III. MEASUREMENTRESULTS

The proposed cascode Gilbert cell mixer with wideband active baluns was designed and fabricated using the TSMC 0.18- m CMOS process. The die photograph of the proposed circuit is depicted in Fig. 8 with a chip size of 0.85 0.57 mm , where the active region occupies an area of 0.44 0.48 mm .

Fig. 8. Micrograph of the proposed mixer (size: 0.852 0.57 mm ).

Fig. 9. Die mounted printed circuit board for testing.

The effects of the chip pads, bond wires, and transmission lines in the circuit board are taken into consideration in the sim-ulation process of the entire circuitry. All measurements were done at a 1.8-V supply voltage and the total power consump-tion is 25.7 mW, including that (14.5 mW) consumed by the output buffer. The conversion gain of the proposed mixer was measured for an IF frequency of 50 MHz with both RF and LO ports swept in frequency up to 12 GHz. The RF and LO signal power were set to be 30 and 5 dBm, respectively. The sim-ulated and measured power conversion gain versus the RF fre-quency is shown in Fig. 10. The mixer achieved a conversion gain of better than 4.4 dB over a wideband frequency from 2 to 12 GHz. The conversion gain also exhibited a 3-dB variation across the RF frequency of 2–11 GHz with an average conver-sion gain of 6.9 dB and maximum gain of 8.4 dB. The measured return loss for the RF signal is also shown in Fig. 10, which il-lustrates that the proposed mixer possesses a return loss better than 10 dB from 2 to 12 GHz. Although not shown, the mea-sured LO and IF return losses are also larger than 10 dB. The port-to-port isolations of the proposed mixer were measured and are presented in Fig. 11. The LO-to-RF and RF-to-IF isolations of the mixer are both better than 25 dB, and the LO-to-IF isola-tion is above 20 dB over the entire measurement frequencies.

The simulated and measured power conversion gain versus RF input power is illustrated in Fig. 12 for RF frequency of

(7)

Fig. 10. Power conversion gain and RF return loss versus RF frequency. The IF frequency is 50 MHz, RF power is030 dBm, and LO power is 05 dBm.

Fig. 11. Measured isolations versus RF frequency.

Fig. 12. Power conversion gain versus RF input power.

power and third-order intermodulation power as functions of the RF input power. There are two signals fed to the RF input port for IIP3 measurement, one at 8 GHz and the other at 8.001 GHz. The LO signal has a frequency of 7.9505 GHz and power level

Fig. 13. Main signal power and third-order intermodulation power as functions of the RF input power.

Fig. 14. MeasuredIIP and IP versus RF frequency.

Fig. 15. Noise figure versus RF frequency.

of 5 dBm. The proposed mixer exhibited an input third-order intercept point of 3.5 dBm at the RF frequency of 8 GHz.

(8)

TABLE II

PERFORMANCECOMPARISONBETWEEN THISSTUDY ANDOTHERWIDEBANDMIXERS

Finally, and were measured for various RF fre-quencies ranging from 2 to 12 GHz. The results are shown in Fig. 14. In the measurement, the LO power was set as 5 dBm and the IF frequency was fixed at 50 MHz. The measured single-sideband (SSB) noise figure is 15.5 dB, and the overall measured results are shown in Fig. 15. The proposed mixer works well from 2 to 11 GHz with maximum and of 3.5 and 6.5 dBm, respectively. The proposed mixer is compared with the state-of-the-art Gilbert cell mixers [22]–[31] in Table II.

It shows that the proposed mixer provides better linearity, more compact chip size, and acceptable conversion gain and power consumption than other studies. The proposed configu-ration shows the highest and , and exhibits more compact size than most of the published studies.

IV. CONCLUSION

In this paper, a high linearity mixer using LC folded cas-code mixer topology, a feedforward compensated differential transconductor, and wideband active baluns in TSMC 0.18- m CMOS technology has been presented. The LC folded cascode method is used to get more voltage headroom, and the feed-forward compensated differential transconductor is adopted to achieve broadband impedance matching and lower the overall distortion. The cascode CG and CS active balun structure ex-hibits a broadband performance, which provides balance signals for the mixer core from a single input. The finished mixer core and active baluns possess good linearity, wide bandwidth, and occupy an area of only 0.85 0.57 mm with a consumed power of 25.7 mW under a 1.8-V supply voltage, which is suitable for application in various wireless communication systems.

[2] T.-W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223–229, Jan. 2004.

[3] N. Islam, S. K. Islam, and H. F. Huq, “High performance CMOS con-verter design in TSMC 0.18-m process,” in Proc. IEEE SoutheastCon, Apr. 8–10, 2005, pp. 148–152.

[4] P. Sivonen, A. Vilander, and A. Parssinen, “Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors,” IEEE Trans. Circuits

Syst. I, Reg. Papers, vol. 52, no. 2, pp. 305–317, Feb. 2005.

[5] K. W. Kobayashi, R. M. Desrosiers, A. G. Aitken, J. C. Cowles, B. Tang, L. T. Tran, T. R. Block, A. K. Oki, and D. C. Streit, “A DC–20-GHz InP HBT balanced analog multiplier for high-data-rate direct-digital modulation and fiber-optic receiver applications,” IEEE

Trans. Microw. Theory Tech., vol. 48, no. 2, pp. 194–202, Feb. 2000.

[6] P. Upadhyaya, M. Rajashekharaiah, and D. Heo, “A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion-zero IF re-ceiver,” in IEEE Microelectron. Electron Devices Workshop, Jun. 2004, pp. 129–130.

[7] M. E. Goldfarb, J. B. Cole, and A. Platzker, “A novel MMIC biphase modulator with variable gain using enhancement-mode FETs suitable for 3 V wireless applications,” in IEEE Microw. Millimeter-Wave

Monolithic Circuits Symp., May 1994, pp. 99–102.

[8] H. Koizumi, S. Nagata, K. Tateoka, K. Kanazawa, and D. Ueda, “A GaAs single balanced mixer MMIC with built-in active balun for personal communication systems,” in IEEE Microw. Millimeter-Wave

Monolithic Circuits Symp., May 1995, pp. 77–80.

[9] J. Kim, S. Bae, J. Jeong, J. Jeon, and Y. Kwon, “A highly-integrated Doherty amplifier for CDMA handset applications using an active phase splitter,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 5, pp. 333–335, May 2005.

[10] C. Viallon, D. Venturin, J. Graffeuil, and T. Parra, “Design of an orig-inal K-band active balun with improved broadband balanced behavior,”

IEEE Microw. Wireless Compon. Lett., vol. 15, no. 4, pp. 280–282, Apr.

2005.

[11] S. T. Lim and J. R. Long, “A feedforward compensated high-linearity differential transconductor for RF applications,” in Proc. IEEE Int.

Cir-cuits Syst. Symp., May 2004, vol. 1, pp. 105–108.

[12] J. Durec and E. Main, “A linear class AB single-ended to differential transconverter suitable for RF circuits,” in IEEE MTT-S Int. Microw.

Symp. Dig., Jun. 1996, vol. 2, pp. 1071–1074.

(9)

[15] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, “A wideband CMOS mixer with feedforward compensated differential transcon-ductor,” in IEEE Int. Circuits Syst. Symp., May 2007, pp. 3892–3895. [16] H. C. Wei, R. M. Weng, and K. Y. Lin, “A 1.5 V high-linearity CMOS

mixer for 2.4 GHz applications,” in Proc. IEEE Int. Circuits Syst.

Symp., May 2004, vol. 1, pp. 561–564.

[17] E. Abou-Allam, J. Nisbet, and M. Maliepaard, “Low-voltage 1.9-GHz front-end receiver in 0.5-m CMOS technology,” IEEE J. Solid-State

Circuits, vol. 36, no. 10, pp. 1434–1443, Oct. 2001.

[18] M. Kawashima, T. Nakagawa, and K. Araki, “A novel broadband active balun,” in IEEE Eur. Microw. Conf., Oct. 2003, vol. 2, pp. 495–498. [19] T. T. Hsu and C. N. Kuo, “Low power 8-GHz ultra-wideband active

balun,” in IEEE SiRF Symp., Jan. 2006, pp. 365–368.

[20] H. Ma, S. J. Fang, F. Lin, and H. Nakamura, “Novel active differential phase splitters in RFIC for wireless applications,” IEEE Trans. Microw.

Theory Tech., vol. 46, no. 12, pp. 2597–2603, Dec. 1998.

[21] M. A. Do, W. M. Lim, J. G. Ma, and K. S. Yeo, “Design of a phase splitter for 3rd ISM band,” in IEEE Electron Devices Solid-State

Cir-cuits Symp., Dec. 2003, pp. 237–240.

[22] C. Y. Wang, S. S. Lu, and C. C. Meng, “Wideband impedance matched GaInP/GaAs HBT Gilbert micromixer with 12 dB gain,” in IEEE

Asia–Pacific Conf., Aug. 2002, pp. 323–326.

[23] C. C. Meng, S. S. Lu, M. H. Chiang, and H. C. Chen, “DC to 8 GHz 11 dB gain Gilbert micromixer using GaInP/GaAs HBT technology,”

Electron. Lett., vol. 39, no. 8, pp. 637–638, Apr. 2003.

[24] M. D. Tsai and H. Wang, “A 0.3–25-GHz ultra-wideband mixer using commercial 0.18-m CMOS technology,” IEEE Microw. Wireless

Compon. Lett., vol. 14, no. 11, pp. 522–524, Nov. 2004.

[25] A. Q. Safarian, A. Yazdi, and P. Heydari, “Design and analysis of an ul-trawide-band distributed CMOS mixer,” IEEE Trans. Very Large Scale

Integr. (VLSI) Syst., vol. 13, no. 5, pp. 618–629, May 2005.

[26] T. A. Phan, C. W. Kim, S. G. Lee, T. J. Park, and E.-J. Kim, “Gain mismatch-balanced I/Q down-conversion mixer for UWB,” in Proc.

IEEE Int. Symp. Circuits Syst., May 2006, pp. 4987–4990.

[27] S.-C. Tseng, C. C. Meng, C.-H. Chang, C.-K. Wu, and G.-W. Huang, “Monolithic broadband Gilbert micromixer with an integrated Marc-hand balun using standard silicon ic process,” IEEE Trans. Microw.

Theory Tech., vol. 54, no. 12, pp. 4362–4371, Dec. 2006.

[28] F.-C. Chang, P.-C. Huang, S.-F. Chao, and H. Wang, “A low power folded mixer for UWB system applications in 0.18-m CMOS tech-nology,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 367–369, May 2007.

[29] C. Kihwa and H.-S. D.-P. Yue, “A 1.2-V, 5.8-mW, ultra-wideband folded mixer in 0.13m CMOS,” in IEEE Radio Freq. Integr. Circuits

Symp., Jun. 2007, pp. 489–492.

[30] K.-H. Liang, H.-Y. Chang, and Y.-J. Chang, “A 0.5–7.5 GHz ultra low-voltage low-power mixer using bulk-injection method by 0.18-m CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp. 531–533, May 2007.

[31] S.-C. Tseng, C. C. Meng, and C.-K. Wu, “GaInP/GaAs HBT wideband transformer Gilbert downconverter with low voltage supply,” Electron.

Lett., vol. 44, no. 2, pp. 127–128, Jan. 2008.

Pei-Zong Rao was born in Kaohsiung, Taiwan, on February 15, 1980. He received the B.S. degree in physics from National Kaohsiung Normal Univer-sity, Kaohsiung, Taiwan, in 2002, the M.S. degree in physics from National Tsing Hua University, Hsinchu, Taiwan, in 2004, and is currently working toward the Ph.D. degree in communication engi-neering at National Chiao Tung University, Hsinchu, Taiwan.

His currently research interests are microwave cir-cuits and RF integrated circir-cuits.

Tang-Yuan Chang received the B.S. degree in elec-trical engineering from Yuan Ze University, Taoyuan, Taiwan, in 1998, and the M.S. degree in communica-tion engineering with Nacommunica-tional Chiao Tung Univer-sity, Hsinchu, Taiwan, in 2007.

He spent several years in industry prior to earning the M.S. degree. His currently research interests in-clude wideband mixers for synthesizers and 24-GHz phase-locked loops for collision-avoidance radar systems.

Ching-Piao Liang was born in Changhwa, Taiwan, in 1980. He received the B.S. and M.S. degrees in communication engineering from Yuan Ze University, Taoyuan, Taiwan, in 2003 and 2005, respectively, and is currently working toward the Ph.D. degree in communication engineering at National Chiao Tung University, Hsinchu, Taiwan.

His primary research interests include RF inte-grated circuits and MMICs.

Shyh-Jong Chung (M’92–SM’06) was born in Taipei, Taiwan. He received the B.S.E.E. and Ph.D. degrees from National Taiwan University, Taipei, Taiwan, in 1984 and 1988, respectively.

Since 1988, he has been with the Department of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he is currently a Professor. From September 1995 to August 1996, he was a Visiting Scholar with the Department of Elec-trical Engineering, Texas, A&M University, College Station. His research interests include the design and applications of active and passive planar antennas, communications in intelli-gent transportation systems (ITSs), low-temperature co-fired ceramic (LTCC)-based RF components and modules, packaging effects of microwave circuits, and numerical techniques in electromagnetics.

Dr. Chung was the treasurer of the IEEE Taipei Section from 2001 to 2003 and the chairman of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Taipei Chapter from 2005 to 2007. He was the recipient of the 2005 Outstanding Electrical Engineering Professor Award of the Chinese Institute of Electrical Engineering and the 2005 Teaching Excellence Award of National Chiao Tung University.