數位校正式比較器及其在快閃型類比數位轉換器上的應用

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(8) Digitally-Calibrated Comparator and Its Application in Flash Analog-to-Digital Converters Student : Chun-Cheng Huang. Advisor : Jieh-Tsorng Wu. Department of Electronics Engineering and Institute of Electronics National Chiao-Tung University Abstract This thesis presents a digital background calibration technique to trim the input-referred offsets of a comparator circuit. The calibration does not interrupt the normal operation of the comparator, hence is suitable for high speed and power efficient applications such as flash analog-to-digital converters(ADC). For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. A calibration loop is then used to adjust the comparator offset so that the offset is minimized. All procedures in the calibration loop are performed in digital domain. This arrangement ensures excellent reliability and high yields. The calibration performance is characterized by the converging speed of the calibration loop and the fluctuation noise imposed to the input signal. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: iii.

(9) the probabilistic distribution of input signal, the quantized step size of offset adjustment, and the threshold of an internal bilateral peak detector. In flash ADCs, the offset fluctuation of a BCC can be drastically reduced by input windowing mechanism, which is accomplished by incorporating the thermometer-code edge detector(TCED) into the calibration loop. When introducing the TCED, uncorrelated random chopping for neighboring BCCs is used to avoid upward locking phenomenon which may lock calibration. A 2Gsample/s 6-bit ADC with the developed calibration technique is fabricated using 65 nm CMOS technology. A circuit architecture with no DC bias and small transistor sizes is selected for comparators used in the ADC. The comparator includes modifications for variable offset mechanism and high common-mode rejection capability. The parameters for the calibration loop are 1/4 LSB for the quantized offset adjustment step, and 16 for the bilateral peak detector threshold. The active area of the fabricated ADC is 0.21×0.66mm2 . Drawing from 1.5V supply voltage, the ADC consumes 54mW. Before activating the calibration, the DNL is -1.0/+4.9 LSB and the INL is -4.3/+5.4 LSB. After activating the offset calibration, the DNL becomes -0.5/+0.6 LSB and the INL is reduced to -0.4/+0.7 LSB. The calibration improves the SNDR from 20.4dB to 31.0dB with an input frequency of 32MHz. When operating at 2GS/s, the effective resolution of bandwidth extends over the Nyquist frequency. The figure-of-merit of the ADC is 0.93pJ/conversion-step.. iv.

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(12) Contents Z`. i. English Abstract. iii. *. v. List of Tables. xi. List of Figures. xiii. 1. 2. Introduction. 1. 1.1. ADC Enhancement Techniques . . . . . . . . . . . . . . . . . . . . . . .. 1. 1.1.1. Flash ADC Design Challenges . . . . . . . . . . . . . . . . . . .. 2. 1.1.2. Input Offset Storage Technique . . . . . . . . . . . . . . . . . .. 4. 1.1.3. Spatial Averaging Technique . . . . . . . . . . . . . . . . . . . .. 7. 1.1.4. Background Offset Trimming . . . . . . . . . . . . . . . . . . .. 9. 1.2. Analog Latch Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11. 1.3. Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14. Digital Calibration for the Comparators. 15. 2.1. Random-Chopping Comparator . . . . . . . . . . . . . . . . . . . . . . .. 15. 2.2. Calibration Processor Based on Offset Polarity . . . . . . . . . . . . . . .. 19. 2.3. Background-Calibrated Comparator . . . . . . . . . . . . . . . . . . . .. 22. 2.3.1. Transient Behavior . . . . . . . . . . . . . . . . . . . . . . . . .. 23. 2.3.2. Offset Fluctuation . . . . . . . . . . . . . . . . . . . . . . . . . .. 28. vii.

(13) 3. Flash ADC with Digitally Calibrated Comparators. 31. 3.1. Input Windowing Technique . . . . . . . . . . . . . . . . . . . . . . . .. 31. 3.1.1. Input Dependent Issues . . . . . . . . . . . . . . . . . . . . . . .. 31. 3.1.2. Input Windowing . . . . . . . . . . . . . . . . . . . . . . . . . .. 34. 3.1.3. Threshold Level Crossing . . . . . . . . . . . . . . . . . . . . .. 36. 3.1.4. Upward Locking . . . . . . . . . . . . . . . . . . . . . . . . . .. 36. 3.1.5. Offset Fluctuation . . . . . . . . . . . . . . . . . . . . . . . . . .. 39. A 6-bit ADC Design Case . . . . . . . . . . . . . . . . . . . . . . . . .. 42. 3.2 4. 5. A 6-bit 2GSample/s Flash ADC. 47. 4.1. Specification and Architecture of the ADC . . . . . . . . . . . . . . . . .. 47. 4.2. Resistor String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 49. 4.3. Background Calibrated Comparator . . . . . . . . . . . . . . . . . . . .. 52. 4.3.1. Circuit Structure . . . . . . . . . . . . . . . . . . . . . . . . . .. 52. 4.3.2. Chopper Settling Issues. . . . . . . . . . . . . . . . . . . . . . .. 54. 4.3.3. Power-Efficient Latch . . . . . . . . . . . . . . . . . . . . . . .. 57. 4.3.4. Latch Circuits for 2nd and 3rd Stages . . . . . . . . . . . . . . . .. 60. 4.3.5. Latch Circuit for 1st Stage . . . . . . . . . . . . . . . . . . . . .. 62. 4.3.6. Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 66. 4.4. Back-End Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71. 4.5. Other Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . .. 73. 4.6. Chip Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 74. 4.6.1. Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 74. 4.6.2. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . .. 79. Conclusions. 85. 5.1. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 85. 5.2. Recommendations for Future Works . . . . . . . . . . . . . . . . . . . .. 86. Appendix A Mathematical Model for Offset Fluctuation. 87. A.1 Formation of VOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87. A.2 VOS [k] Dependence on T[k] and S[k] . . . . . . . . . . . . . . . . . . .. 88. viii.

(14) A.3 R[k] dependence on VOS [k − 1] . . . . . . . . . . . . . . . . . . . . . .. 88. A.4 Steady-State Approach for VOS [k] . . . . . . . . . . . . . . . . . . . . .. 89. A.5 A Finite-State Markov Chain Reformation . . . . . . . . . . . . . . . . .. 92. Bibliography. 95. Vita. 101. Publication List. 102. ix.

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(16) List of Tables 4.1. Codes for coarse offset control . . . . . . . . . . . . . . . . . . . . . . .. 66. 4.2. Performance summary and comparison. . . . . . . . . . . . . . . . . . .. 82. xi.

(17) xii.

(18) List of Figures 1.1. A typical flash ADC architecture . . . . . . . . . . . . . . . . . . . . . .. 2. 1.2. The commonly-used comparator architecture . . . . . . . . . . . . . . .. 4. 1.3. Input offset storage(IOS) technique . . . . . . . . . . . . . . . . . . . .. 5. 1.4. Operation phases for IOS . . . . . . . . . . . . . . . . . . . . . . . . . .. 6. 1.5. Spatial averaging technique. . . . . . . . . . . . . . . . . . . . . . . . .. 7. 1.6. Random offset voltages on comparators . . . . . . . . . . . . . . . . . .. 8. 1.7. Small-signal equivalent circuits for the preamplifier and latch . . . . . . .. 9. 1.8. Background offset calibration for a comparator . . . . . . . . . . . . . .. 10. 1.9. Analog latch circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12. 1.9. Analog latch circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13. 2.1. The random-chopping comparator(RCC). . . . . . . . . . . . . . . . . .. 15. 2.2. 17. 2.3. Probability distribution for RCC . . . . . . . . . . . . . . . . . . . . . . P Calibration based on (−q × Dc ) . . . . . . . . . . . . . . . . . . . . .. 18. 2.4. Input signal with time-variant PDF . . . . . . . . . . . . . . . . . . . . .. 18. 2.5. Calibration based on accumulation and reset(AAR) . . . . . . . . . . . .. 20. 2.6. R and VOS variations versus time. . . . . . . . . . . . . . . . . . . . . .. 21. 2.7. A background-calibrated comparator . . . . . . . . . . . . . . . . . . . .. 22. 2.8. Transient behavior of BCC . . . . . . . . . . . . . . . . . . . . . . . . .. 24. 2.9. Transient response of a BCC example. . . . . . . . . . . . . . . . . . . .. 26. 2.10 Offset fluctuation phenomenon . . . . . . . . . . . . . . . . . . . . . . .. 27. 2.11 P (VOS ) of a BCC example. . . . . . . . . . . . . . . . . . . . . . . . . .. 29. 2.12 σ(VOS ) versus NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30. xiii.

(19) 3.1. Null-information input condition. . . . . . . . . . . . . . . . . . . . . . .. 32. 3.2. Small ∆P/P ratio in a real ADC case. . . . . . . . . . . . . . . . . . . .. 32. 3.3. Location-dependent ∆P/P ratio. . . . . . . . . . . . . . . . . . . . . . .. 33. 3.4. Flash ADC incorporating input-windowed BCCs. . . . . . . . . . . . . .. 34. 3.5. Input windowing for the jth BCC. . . . . . . . . . . . . . . . . . . . . . .. 35. 3.6. Effect of threshold level crossing . . . . . . . . . . . . . . . . . . . . . .. 37. 3.7. Upward locking caused by offseted threshold levels . . . . . . . . . . . .. 38. 3.8. Upward-locking-free operation . . . . . . . . . . . . . . . . . . . . . . .. 40. 3.9. σ(VOS ) of a windowed BCC in a 6-bit ADC . . . . . . . . . . . . . . . .. 41. 0 3.10 Worst-case σ(VOS ) with VOS = (1/2)∆V . . . . . . . . . . . . . . . . . .. 42. 3.11 Transient behavior of a 6-bit ADC design case. . . . . . . . . . . . . . .. 43. 3.12 BCC Offsets before and after calibration. . . . . . . . . . . . . . . . . . .. 45. 3.13 Spectrum performance for a 6-bit ADC . . . . . . . . . . . . . . . . . .. 46. 4.1. ADC architecture for circuit implementation. . . . . . . . . . . . . . . .. 48. 4.2. Cross connection for resistor string. . . . . . . . . . . . . . . . . . . . .. 50. 4.3. Reference level deviation due to resistor mismatch. . . . . . . . . . . . .. 52. 4.4. Circuit structure of the background calibrated comparator. . . . . . . . .. 53. 4.5. Settling issue for chopper switching . . . . . . . . . . . . . . . . . . . .. 55. 4.6. Simulation results for settling error. . . . . . . . . . . . . . . . . . . . .. 56. 4.7. Circuit of the power-efficient latch . . . . . . . . . . . . . . . . . . . . .. 57. 4.8. Waveforms of the latch . . . . . . . . . . . . . . . . . . . . . . . . . . .. 59. 4.9. The complete 2nd and 3rd latch circuit. . . . . . . . . . . . . . . . . . . .. 61. 4.10 SR latch and its waveforms . . . . . . . . . . . . . . . . . . . . . . . . .. 62. 4.11 The 1st stage latch in the BCC . . . . . . . . . . . . . . . . . . . . . . .. 63. 4.12 Binary search process for offset extraction . . . . . . . . . . . . . . . . .. 65. 4.13 Circuits for coarse offset control in the 1st -stage latch. . . . . . . . . . . .. 67. 4.14 Shift register used in ADC calibration . . . . . . . . . . . . . . . . . . .. 68. 4.15 Simulation results for offset Adjustment . . . . . . . . . . . . . . . . . .. 69. 4.16 Cover range for fine offset control . . . . . . . . . . . . . . . . . . . . .. 70. 4.17 Block diagram of the back-end encoder . . . . . . . . . . . . . . . . . .. 72. xiv.

(20) 4.18 Micrograph of the implemented circuit die . . . . . . . . . . . . . . . . .. 75. 4.19 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 76. 4.20 Measured DNL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 77. 4.21 Measured INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 78. 4.22 Spectrum performance of the implemented ADC . . . . . . . . . . . . .. 80. 4.23 SNDR versus input signal frequency. . . . . . . . . . . . . . . . . . . . .. 81. 4.24 SNDR versus sampling rate. . . . . . . . . . . . . . . . . . . . . . . . .. 83. A.1 VOS extended as an irregular random sequence. . . . . . . . . . . . . . .. 88. A.2 Steady-state transfer probabilities at. m VOS .. . . . . . . . . . . . . . . . . .. 90. A.3 Historically-unified fractional term for transfer probability. . . . . . . . .. 91. xv.

(21) Chapter 1 Introduction 1.1. ADC Enhancement Techniques. Analog-to-digital converter(ADC) is the interface that converts the external physical quantity into a digital value. In modern SOC system such as WLAN, WIFI, HDTV, xDSL, etc˙, ADC plays an essential role to provide the base band signal streams for the digital signal processing(DSP) core. As the CMOS technology progresses into nano-scale era, the challenges for ADC design become greater and greater. Due to the channel length shrinkage, the transition frequency of a transistor increases but its rds is reduced. High transition frequency is beneficial for high speed comparator. While OPAMP with high gain and high linearity becomes more and more difficult to implement due to lower rds . The reduced supply voltage increases the design barrier further. Nevertheless, OPAMP is the key component for pipelined ADCs. Another issues in nano-scale CMOS technology is the device mismatch. Mismatch becomes significant in tiny devices and limits the circuit speed and accuracy[1]. In comparator based data converter such as flash type ADCs, comparator offset caused from device mismatch corrupts the threshold level accuracy and hence limit the converter resolution. To overcome these analog design limitation, many enhancement techniques have been developed. For OPAMP based converters such as the pipelined ADCs, correlation based 1.

(22) 2. CHAPTER 1. INTRODUCTION. techniques[2][3][4] and dynamic matching algorithm [5][6] are used to calibrate the mismatchcaused nonlinearity. A comparator based mDAC[7] is used to eliminate the demand on the OPAMP. The off-chip calibration[8], the on-chip calibration using adaptive LMS algorithm[9][10] and the calibration with auxiliary conversion channel[11] are also developed to enhance the performance of the ADC. For comparator-based converter such as the flash ADCs, various methods are proposed to mitigate the effect of comparator offset voltage. These techniques include spatial averaging[12][13][14][15], offset storage[16][17], calibrated redundancy[18][19] and fault-tolerant encoding[20], and so on. On the other hand, digitally calibrated comparator in which the offset is removed by auxiliary digital circuits[21][22][23] has better reliability and stability but has not been implemented on-line. In this thesis, we introduce an effective on-line offset calibration technique for the comparator. The calibration is suitable for over-GHz flash ADC and can trim the comparator offset in the background.. 1.1.1 VR. Flash ADC Design Challenges VR, 2N −1 VR, 2N −2. VR,2. VR,1. 2. 1. Vi 2N −1. 2N −2. N ( 2 −1 ) − to − N Encoder. N. Do. Figure 1.1: A typical flash ADC architecture Fig. 1.1 shows an N-bit flash analog-to-digital converter (ADC) that uses 2N − 1 comparators to simultaneously compare input, Vi , with 2N − 1 references, VR,j , where j = 1, 2, · · · 2N − 1. Outputs of this comparator array appear as a thermometer code..

(23) 1.1. ADC ENHANCEMENT TECHNIQUES. 3. The output bits have the values of ‘1’ with threshold levels below the input signal, and the values of ‘0’ with threshold level beyond the input signal. The digital output Do is obtained by encoding this thermometer codes. For a high-speed CMOS flash ADC, the linearity of its transfer function is predominantly degraded by two characteristics of the comparators: 1. the metastability; 2. the the input offset voltage [24]. Metastability is the incompletely-defined comparator output as input signal falls close to the threshold level. The error probability on output codes, which is equivalent to the ratio of input ranges corresponding to incompletely-defined outputs and well-defined outputs, describe the metastability of a comparator. As comparators suffer metastability, the final value of its output strongly depends on the threshold level of the following digital gates. In addition, it is very sensitive to noise. Faster comparators have less metastable region, but consumes more power. Input offset voltage is the the input voltage that produces an output value at middle trip-point for a comparator. A systematic input offset voltage is analytical in circuit design phase and can be suppressed using symmetric circuit configuration. While the device mismatch aroused in semiconductor process causes a random input offset voltage that is not predictable. This random offset degrades the comparator resolution and can only be reduced by enlarging device sizes. Both metastability and input offset voltage produce ‘Bubbles’ in the thermometer code. Bubbles are the cavities of ‘0’ in a series of ‘1’, or ‘1’ in a series of ‘0’. Various designs of encoders have been proposed to suppress the effect of the bubbles[25] [26][27]. These techniques are effective but the improvements are limited. Since the bubbles are originated from the imperfection of the comparators, the ADC performance is dominated by the comparators. Fig. 1.2 is a commonly-used comparator architecture. Theoretically, a latch circuit in the right part of this figure is sufficient to be an comparator. Yet the large input offset voltage of the latch circuit is not tolerant in practical applications. This is why the preamplifier shown in the left part is necessary. The voltage gain of the preamplifier reduces the input-referred offset voltage of the latch. For the preamplifier, the input offset voltage is related to the device mismatch of the.

(24) 4. CHAPTER 1. INTRODUCTION. Vi. Dc. VR,j. VSS. VSS Preamplifier. Dc. Regenerative Latch. Figure 1.2: The commonly-used comparator architecture input pair: AV σ(∆Vt ) = √ t WL. (1.1). Circuits with larger device size have better matching properties but less power efficiency. Due to the design consideration on device matching, there exists a fundamental trade-off among the speed, power, and accuracy for a CMOS flash ADC [28]: Speed × Accuracy2 1 ≈ Power Cox · A2Vt. (1.2). Equation (1.2) figures out a physical limitation in comparator design. As an example, doubled speed and doubled resolution cost a power consumption of eight times. It is hard to exceed or even approach the limit of (1.2) merely by device size optimization. Several innovative techniques have been proposed to overcome this inherent constraint on devices. Among them, input-offset storage technique and averaging technique are two of the most popular ones. Subsection 1.1.2 and 1.1.3 describe the details of them.. 1.1.2. Input Offset Storage Technique. The principle of input offset storage(IOS) technique is to sample and store the input offset in the reset phase and then cancel it in the comparison phase[17][29]. As shown in Fig. 1.3, The input signal and the input offset voltage are together sampled to the serial.

(25) 1.1. ADC ENHANCEMENT TECHNIQUES. 5. 1. Vref V in. 2. CS. 1. V OS. A. Do Latch. Preamplifier Figure 1.3: Input offset storage(IOS) technique: (a) Comparator with IOS; (b) Offset storage phase(φ1 ); (c) Comparison phase(φ2 ). connected capacitor CS , and then compared with the offseted threshold level. The input offset voltage is thus eliminated in the comparison. The operation is decomposed into 2 phases: sampling phase in Fig. 1.4a and comparison phase in Fig. 1.4b. In sampling phase, assuming the preamplifier has an infinite voltage gain, its output node is pulled to VOS due to the virtual grounding, thus CS is charged to Vin − VOS . In comparison phase, the feedback loop is broken and CS is connected to the reference voltage. Since CS has been charged in the sampling phase, the input node of the preamplifier is pulled to: Vref − (Vin − VOS ) − VOS = Vref − Vin. (1.3). This leads to a zero-offset preamplification for the comparator. Another alternative operation mode for IOS is that the reference level, instead of the input signal, is sampled in reset phase[30]. Then, in the comparison phase, input signal is connected to the comparator input port. Hence the input offset voltage is also stored and eliminated. This operation mode is suitable for higher speed comparison since reference level is a fixed value and the settling time for capacitive charging in sampling phase is shorten. Compared with the input-sampled mode, the reference-sampled mode is lack of the sample-and-hold feature over the input signal. In multiple comparator scenario such as flash ADC application, clock jitter will cause more bubbles in the output code with the.

(26) 6. CHAPTER 1. INTRODUCTION. CS A. V OS. V in. Do Latch. (a). V ref. CS A. V OS. Do Latch. (b). Figure 1.4: Operation phases for IOS:(a) Offset storage phase(φ1 ); (b) comparison phase(φ2 ).. reference-sampled mode. The limitation of IOS technique is the finite gain of the preamplifier. For the preamplifier with infinite gain, feedback guarantees a perfect virtual grounding in input nodes. This is essential to charge CS correctly. However, due to high speed consideration, typical value for the preamplifier gain is about 5 ~10, resulting in a deviation on offset storage in sampling phase. Besides, the parasitic capacitance in the comparator input nodes shares the charge of CS in comparison phase. The charge sharing is equivalent to a voltage divider that degrades the precision of offset cancellation. Large CS is needed to reduce the effect of charge sharing. IOS requires extra phase to sample the input offset voltage, thus the clocking is more complex than a simple comparator. The operation speed may also be limited..

(27) 1.1. ADC ENHANCEMENT TECHNIQUES. 7. VR,j+1 Vi. VOS,j+1. V R,j. VOS,j. VR,j−1 VOS,j−1. Averaging netowrk Figure 1.5: Spatial averaging technique.. 1.1.3. Spatial Averaging Technique. Spatial averaging technique utilizes an averaging network to lower the offset variance of the comparator array[31]. A simplified averaging network is shown in Fig. 1.1.3. In Fig. 1.1.3, signal on the jth preamplifier output node is composed of not only the part from jth preamplifier, but also parts from (j±1) th , (j±2) th ... etc., through the resistive summation of the averaging network. Hence, the signal on this output node is effected by the input offset voltage of jth , (j±1) th , (j±2) th ...etc. in total. The comparator input offset voltage is originated from the random factors on semiconductor process, thus is a random variable itself. The random offset voltage is shown in Fig. 1.6a..

(28) 8. CHAPTER 1. INTRODUCTION. VOS. comp.# j−3 j−2 j−1. j. j+1. j+2. j+3. (a). VOS. comp.# j−3 j−2 j−1. j. j+1. j+2. j+3. (b). Figure 1.6: Random offset voltages on comparators: (a) without averaging; (b) with averaging..

(29) 1.1. ADC ENHANCEMENT TECHNIQUES. 9. Vo,amp g. ∆V. RL. m1. CL. Preamplifier (a). Vo,lat CL. RL. g. g. m1. m2. RL. CL. Latch (b). Figure 1.7: Small-signal equivalent circuit: (a) preamplifier; (b) latch The offset summation is equivalent to performing moving average over the comparator array. The moving average produces a spatial low-pass filtering to the ‘peaks’ of the random offsets. The output node of each preamplifier thus suffers a smaller equivalent offset voltage, which is shown in Fig. 1.6b. The limitation of the spatial averaging technique is that it need redundant comparators in both ends of the comparator array[32], since the comparators located near the ends do not have enough neighbors to provide the random offsets for averaging Specialized termination[33] and cyclic connection[14] have been applied to the averaging network to mintage the this overhead, but they still require extra power and area.. 1.1.4. Background Offset Trimming. The input offset storage and the spatial averaging techniques both require preamplifiers to apply. To verify the cost of the preamplification, small-signal equivalent circuits for a preamplifier and a latch are shown in Fig. 1.7..

(30) 10. CHAPTER 1. INTRODUCTION. Vi V R,j. Dc V OS. Latch. VOS Control Logic. Statistics Based Offset Detector. Calibration Processor(CP) Figure 1.8: Background offset calibration for a comparator And the transient voltage gains for them are: t h −t i , Av,lat = gm2 RL exp Av,amp = gm1 RL 1 − exp R L CL CL /gm2. (1.4). As an example, assuming RL = 1KΩ, CL =1pF, and the settling period is 0.5ns, to obtain a voltage gain of 10 requires gm1 =25.4 mA/V for the preamplifier and gm2 =2.65 mA/V for the latch. The preamplifier transconductance is about 9.6 times of the latch transconductance. However, the latch has large offset voltage and kickback noise so that the preamplification is necessary. In this thesis, we propose a background calibration technique shown in Fig. 1.8 to trim the offset voltage continuously. This background calibration technique adjust the offset voltage according to the code statistics of the latch outputs without interrupting the its operation. As the offset voltage of the latch can be trimmed to zero, and hence the device size is shrunk down, the preamplifier which is used to suppress the offset voltage and to block kickback noise is not necessary. Elimination of the preamplifier will greatly reduce the power consumption of the comparator. The proposed calibration loop operates in the digital domain and only minor modification is required on the analog path, hence the circuit speed will not degrade. The calibration can be applied concurrently to all latches in the flash ADC to improve its linearity..

(31) 1.2. ANALOG LATCH CIRCUITS. 11. Foreground offset trimming techniques have been proposed in [34][35][36][22]. it is executed only once in the beginning or repeatedly in some specific clock periods to detect the offsets and adjust the circuit configuration accordingly. In cases that temperature and supply voltage variate during the ADC operation, trimmed offset voltage may deviate from the zero. On the contrary, background offset calibration is capable to trace back the offset shifts and thus provides better conversion performance.. 1.2. Analog Latch Circuits. There are various types of analog latch circuits. Fig. 1.9 lists some of them. A simplest regenerative latch is composed of two cross-connected inverters shown in (a). A practical analog latch circuit requires the input coupling path and the clocked mechanism. In (b), (c), (d), (h) and (i), the input signal is parallel coupled. In other circuits, the input is series coupled. Parallel couping of the input signal does not limit the regenerative current, thus is faster then serial coupling. However, serial coupled input device will be turned off as the regenerative operation finished, thus the power consumption is less. In reset phase, the output nodes of the latch in (h), (i), (j) are equalized, while the output nodes of other latches are pulled high. Equalized output nodes will be separated faster in the regeneration phase, but they consume static power in the reset phase. The input offset voltage depends on whether the input devices are saturated or not in the regeneration phase. (b), (c), (g), (h), (i), and (k) have smaller input offset voltage than others since the saturated devices contribute more transient gain to pull the positive feedback loop. Kickback noise is decided by the coupling path between output and input nodes. For (e), (f), and (j), they have smaller kickback noise in nature. Although the output nodes of (h) and (i) do not directly couple back to the input nodes, the clock signal transition may also produce kickback noise. The input devices in (e) act as a voltage controlled resistor, thus is possible combined with preamplifier interpolation[37]. The circuit is very power efficient since no DC power is consumed. The disadvantage of this circuit is the weak controllability of the input signal over this device, thus its input offset voltage is quite large. Noise can also have.

(32) 12. CHAPTER 1. INTRODUCTION. VDD V ip. VDD. V in ck. V on V on. V op. V op. ck. (a). (b). VDD ck. VDD. ck. V on. V op. ck. ck. V on V ip. V op ck. V in V ip. ck. V in. (c). (d). VDD. VDD. ck. ck. V on. ck. V op. ck. V on. ck. V op ck. V ip. V in. V rn. V ip. (e). V in. (f). Figure 1.9: Analog latch circuits. V rp.

(33) 1.2. ANALOG LATCH CIRCUITS. 13. VDD ck. VDD. ck. V on. V op V ip. ck. V in V on. V op. ck. ck. ck. V ip. V in. (g). (h) VDD. VDD V ip. ck. V in ck. V on. V op. ck. ck. V ip. V on. V in. V op. Vb. (i). (j) VDD. ck. ck. V on. V op. V ip. V in. ck. (k). Figure 1.9: Analog latch circuits.

(34) 14. CHAPTER 1. INTRODUCTION. strong effect on the comparison results. (f) is similar to (e) except that it operates with differential input. (j) is nearly the same thing but with input signal couple by a P-type MOSFET. (i) is modified from (h). The added tail transistor may increase both its regeneration speed and the common-mode rejection ability.[13]. Although (c) and (k) have similar structure, the serial coupled input device in the latter will be cut off as the comparison is completed, thus is more power efficient that the former. (k) is usually used as sense amplify for the RAM cell. When applied in ADC circuit, its low power consuming, small input offset and hight comparison speed are very beneficial[38].. 1.3. Thesis Organization. This thesis is organized as follows. Chap.2 describes the design and analysis of a background-calibrated comparator(BCC). Chap.3 gives the system-level analysis for a flash ADC using the BCCs. Chap.4 illustrates an implementation of a ADC circuit using the proposed background calibration technique. Chap.5 draws conclusions and gives the recommendations for future works. Finally, the Appendix includes a mathematical analysis for the offset fluctuation behavior of the proposed BCC..

(35) Chapter 2 Digital Calibration for the Comparators 2.1. Random-Chopping Comparator. The proposed comparator calibration scheme is based on a random-chopping comparator(RCC) which is shown in Fig. 2.1. The RCC is used to replace each comparator in Fig. 1.1. For the jth RCC, input signal Vi is compared with the jth reference voltage VR,j , and then generates a corresponding binary output Dc ∈ {1, 0}. Due to the clocked operation, Dc can be represented as Dc [k] with the index k indicating the sampling count, or simply the time index. The comparator inside the RCC has an input offset voltage VOS . The two choppers, CHP1 and CHP2, are controlled by a binary-state random sequence q[k] ∈ {+1, −1}. The probability for q[k] = +1 and q[k] = −1 is equally 0.5.. q[k]. Vi. Dc. V R,j. Dc CHP1. V OS. CHP2. Figure 2.1: The random-chopping comparator(RCC). 15.

(36) 16. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. CHP1 passes the inputs unchanged when q = +1 and interchanges the inputs when q = −1. Similarly in the digital domain, CHP2 passes the outputs unchanged when q = +1 and invert the outputs when q = −1. In CMOS technology, CHP1 can be realized using 4 analog switches. CHP2 is composed of digital gates. The behavior of RCC can be described by: Dc =. i 1h 1 + q × SGN q(Vi − VR,j ) − VOS 2. (2.1). Where SGN is the sign function that return +1 if its independent variable is larger than 0 and -1 if its independent variable is smaller than 0. Since q is possibly only +1 or -1, it can be moved to the independent domain of the SGN function. The square of q is 1, thus (2.1) becomes: i 1h Dc = 1 + SGN Vi − VR,j − qVOS 2. (2.2). Equation (2.2) indicates that changing the CHP1/CHP2 states is equivalent to invert the polarity of the input offset voltage on the internal comparator. The SNG function can be represented as adding a quantization error to the normalized independent variable, thus (2.2) can be represented as: Dc =. i 2 1h (Vi − VR,j − qVOS ) + e 1+ 2 A0. (2.3). Where A0 is the maximum amplitude of (Vi − VR,j ). The factor of 2 above the denominator A0 implies the swing of (Vi − VR,j ) is normalized to ±2. In this case, the quantization error e is assumed to be a zero-mean value and is independent of q. If the random sequence q[k] is selected to be uncorrelated with Vi with a zero mean, the averaged value of (−q × Dc ) is described by (2.4): q q VOS q × e VOS −q × Dc = − − (Vi − VR,j ) + − = 2 A0 A0 2 A0. (2.4). Hence it is possible to obtain the value of VOS from the averaging of (−q × Dc ). This is based on the fact that there is no correlation between q and (Vi − VR,j + e). However, the averaging calculation requires data collection over a long period of time and a floating point arithmetic unit. The hardware overhead is too large for a single comparator. The correlation-based VOS detection can also be understood from the probability density function(PDF) of Vi − VR,j shown in Fig. 2.2. When q = +1, the probability for.

(37) 2.1. RANDOM-CHOPPING COMPARATOR. D c =1 D c =0. PDF. Vi P . V R,j. V OS. 0. q = +1. D c=1 D c=0 PDF. 17. V i P ∆ P q=. V R,j. 0 V OS. 1. Figure 2.2: Probability of Dc =1 for q = +1 and q = −1.. Dc = +1 is P . When q = −1, the probability for Dc = +1 is (P + ∆P ). If the random sequence q[k] is selected to be uncorrelated with Vi , the comparator can perceive identical PDF of (Vi − VR,j ) regardless of q[k]. In this case, the averaged value of (−q × Dc ) is proportional to ∆P . Since ∆P is also proportional to VOS , it is possible to trim VOS according to (−q × Dc ). For hardware implementation, to accumulate (−q × Dc ) is much easier that to calculate its averaged value. In mathematical meaning, to trim VOS based on the accumulation within a fixed interval is equivalent to do that based on the averaging. Fig. 2.3 is a calibration example that utilizes the offset detection[39][40]. The calibration loop cuts down the input offset voltage by a fraction of accumulated (−q × Dc ) at each sample. It is equivalent to a linear negative feedback loop. This configuration requires that the proportion parameter µ be small enough to prevent oscillation and large enough to perform a good tracking behavior. The main disadvantage for the loop in Fig. 2.3 is that a time-varying input signal distribution will cause a calibration fault. As shown in Fig. 2.4, when the distribution of the input signal changes, ∆P also changes. In this case, the calibration loop thinks of the changes on ∆P as the changes on offset and thus misadjust it. For a general-purpose ADC, the signal may have any type of distribution, so this linear feedback calibration scheme is not reliable for general use..

(38) 18. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. q. Vi. Dc. V R,j. Dc V OS. q µ. Figure 2.3: Calibration based on. Σ P. (−q × Dc ). PDF ∆P. . V OS. 0. V OS. Vi. Figure 2.4: Input signal with time-variant PDF. V R,j.

(39) 2.2. CALIBRATION PROCESSOR BASED ON OFFSET POLARITY. 19. On the contrary, the polarity of accumulated (−q × Dc ) is unchanged even if the input signal variates. Thus it is more reliable to detect the offset polarity according to (−q × Dc ) accumulation. Offset polarity implies the offset direction instead of the offset magnitude. Based on offset polarity detection, the calibration processor is designed to perform a fixedstep adjustment when trimming the offset voltage. A detailed explanation is given in section 2.2.. 2.2. Calibration Processor Based on Offset Polarity. The calibration processor based on offset polarity detection is shown in Fig. 2.2. An accumulation-and-reset(AAR) block is used for the detection. In the AAR shown in Fig. 2.2, the accumulated (q × Dc ), which is represented as R, is fed to a bilateral peak detector(BPD). BPD has two internal threshold levels ±NC . As R > +NC , the output of BPD, S, will be 1. As R < −NC , S will be -1. In both cases the accumulator itself is also reset and the (q × Dc ) accumulation restarts. Other than the two cases, S keeps in 0. Another accumulator is used to accumulate S. Its output T is used to control the offset voltage. The behavior of the calibration processor can be understood by Fig. 2.6. The variation of VOS and R is plotted versus the time index. Suppose that the comparator input offset voltage VOS is positive in the beginning, R tends to lean down and cross the lower boundary −NC of the BPD soon. At this time, the offset voltage is cut down by a fixed step and R is reset immediately, then another accumulation starts. The crossing and offset trimming repeat again and again until VOS is reduced to a value close to 0. In such a small offset, the leaning of R becomes very indistinctive and the offset trimming rarely happens. AAR is used to suppress the effect of input signal and extract the polarity information of input offset voltage from the comparator output. Its function resembles a discrete-time integrator in the digital domain [41] [42]. However, for outputs of a 1-bit quantizer such as the comparator, the offset information is accompanied with heavy quantization noise. A linear integrator may not effectively extract the offset information..

(40) 20. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. q Dc Reset. Σ R |R|>N C ? S {−1,0,1}. Bilateral Peak Detector(BPD). Accumulation And Reset (AAR). Σ T V OS Control Figure 2.5: Calibration based on accumulation and reset(AAR).

(41) 2.2. CALIBRATION PROCESSOR BASED ON OFFSET POLARITY. +NC. −NC. R. V OS. t. t Figure 2.6: R and VOS variations versus time.. 21.

(42) 22. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. q[k]. Vi. Dc. V R,j. Dc CHP1. Random Chopping Comparator. CHP2. V OS. Calibration Processor T[k]. Σ ACC. S[k]. Σ. R[k]. q[k]. AAR. Figure 2.7: A background-calibrated comparator. 2.3. Background-Calibrated Comparator. The background calibrated comparator(BCC) is composed of a random-chopping comparator and a calibration processor. Fig. 2.7 illustrates its block diagram. The proposed calibration scheme for BCC is suitable for general purpose application. No extra signals nor the exact information of Vi is needed. The effectiveness of the calibration only depends on the probability difference ∆P of Fig. 2.2. The offset of the internal comparator in BCC is adjusted by reconfiguring those lowspeed sections, which are separated from the high-speed signal path [34] [36] [35]. Thus the added VOS controllability for the calibration costs relatively low speed and power penalty. An alternative calibration scheme based on the offset polarity detection is to trim the offset voltage periodically[39]. Compared to the periodically-adjusted scheme, the proposed scheme has faster converging speed and lower offset fluctuation. Based on the AAR algorithm, the the offset trimming gets activated quite often and hence the offset converges very fast with large VOS in the beginning. When VOS has been trimmed close to 0, the ∆P.

(43) 2.3. BACKGROUND-CALIBRATED COMPARATOR. 23. also becomes small, then the trimming rarely get activated and VOS is more stationary. The time-varying offset voltage can be expressed as: VOS [k] = V0 + ∆V × T [k]. (2.5). where V0 is the inherent comparator offset at T [k] = 0, and ∆V is the step size of the offset control. ∆V , together with the BPD threshold level NC , are two important parameters in BCC. Both parameters affect the converging speed and the offset fluctuation. Large ∆V and small NC result in fast converging speed but large offset fluctuation. On the other hand, small ∆V and large NC result in small VOS fluctuation but also slow converging speed. The detail analysis for the two parameters is given in subsections 2.3.1 and 2.3.2. Circuit realization of the BCC is straightforward. As the blocks shown in Fig. 2.1, Fig. 2.2 and Fig. 2.7, there are only choppers, two accumulators and a few digital gates in CP. This digital parts can be easily synthesized using CAD tools. Since no multi-bit multiplier is required, the power and area overhead is quite small. The offset-variable comparator in RCC is the most area-consuming part, since it requires a fine-step offset control unit that covers a wide offset adjustment range. However, this area cost can be minimized by dense layout since there are no power or speed issues here.. 2.3.1. Transient Behavior. As the calibration starts, BCC suffers a period of transient response before the offset voltage is converged. This period is directly related to the tracking ability of the calibration. To resist the effect of environment parameter variation, such as temperature or supply voltage variation, the time constant of the transient response has to be small. Fig. 2.8 illustrates the front end of the BCC. In Fig. 2.8a, the input signal is randomly chopped by the chopper and becomes a zero-mean noise. Hence the signal in node Vc is composed of a DC value coming from the offset voltage and a noise coming from the chopped input signal. Chopped input signal is usually quite larger than the offset voltage. This is shown in Fig. 2.8b. CP suppress the effect of the chopped-input-signal noise and forces VOS moving toward 0 with feedback mechanism. Suppose that the input signal PDF over the range of.

(44) 24. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. q[k]. Vi. Vc. V R,j CHP1. V OS (a). Vc. VOS [0] t. (b). Figure 2.8: Transient behavior of BCC: (a) BCC front end; (b) Waveform on comparator input node..

(45) 2.3. BACKGROUND-CALIBRATED COMPARATOR. 25. VR,j ± VOS is a constant D(VR,j ), the value of ∆P in Fig. 2.2 can be expressed as: ∆P = 2D(VR,j )VOS. (2.6). Ignoring the disturbance from the input signal, the speed in which CP cuts VOS is proportional to ∆P . As an example, when ∆P becomes half of its original value, the P slope of accumulated (−q × Dc ) becomes half accordingly, and the period of which the BPD outputs non-zero value is doubled. This makes the speed for which CP cutting down VOS reduced by a half. According to (2.6), the above example implies that the decreasing rate of VOS is proportional to its value. Hence the transient behavior of VOS can be described by a single-pole model: 1 ∆VOS [k] = −∆V × D(VR,j )VOS [k] × ∆k NC. (2.7). From (2.7), transient response of VOS [k] can be expressed as: . ∆P VOS [k] = VOS [0] · exp −k D(VR,j ) Nc. (2.8). where the time constant of this feedback system is: τc =. NC ∆V · D(VR,j). (2.9). Shorter τc results in better tracking ability for the calibration loop. Fig. 2.9 shows an example of the VOS [k] transient response of a BCC. The initial offset, VOS [0], is set to 5.8 LSB. Calibration parameters are ∆V = (1/2) LSB and NC = 64. The BCC is assumed to be located in the middle of a 6-bit ADC. With a full-range sinusoidal input signal and VR,j = 0, we have D(VR,j ) =. 1 2 · π VF S. (2.10). In Fig. 2.9, the solid line is the discrete-time simulation result, and the smooth dashed line is the approximation using (2.8). The approximation manifests a good agreement with the simulation. The settling time constant is τc = π · 26 · 64 ≈ 12868..

(46) 26. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. 6 5. VOS / LSB. 4 3 2. Simulation. 1 0 -1 0. Approximation. 20000. 40000. 60000. 80000. k Figure 2.9: Transient response of a BCC example.. 100000.

(47) 2.3. BACKGROUND-CALIBRATED COMPARATOR. 27. V OS,j 2 V OS,j 1 V OS,j 0 V OS,j. k. −1 V OS,j −2 V OS,j (a). Probability V. V OS. 0 V. 2 OS. V. 1 OS. V. 0 OS. V. 1 OS. V. 2 OS. (b). Figure 2.10: Offset fluctuation phenomenon: (a) Offset fluctuation waveform; (b) Probability mass function(PMF) of the offset voltage..

(48) 28. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. 2.3.2. Offset Fluctuation. The digital calibration for BCC operates in background. Namely, it is never turned off even the offset voltage has been well trimmed. As the VOS is converged close to 0 due to the calibration process, the behavior of VOS [k] becomes a discrete random fluctuation around zero. This is shown in Fig. 2.10a. The stochastic behavior of VOS is described by a random sequence with discrete values, VOS [k]. Fig. 2.10b illustrates a possible probability mass function (PMF) for VOS which is represented as P (VOS ). +1 +2 −1 −2 0 0 The values for VOS includes VOS , VOS , VOS , VOS , VOS , . . . etc. VOS is the value point. closest to zero. The distance between two adjacent value points is the offset control step 0 0 ∆V . According to the definition of VOS , possible value for VOS is between −∆V /2 and 0 +∆V /2. The calibration loop forces the maximum value of P (VOS ) to occur at VOS . A. mathematical analysis for VOS [k] is included in chapter A, which includes the procedures to calculate P (VOS ) from ∆V , NC , and the PDF of input signal. Fig. 2.11 shows the P (VOS ) of a BCC with the condition identical to the Fig. 2.9. 0 Results from both calculation and simulation are presented. The value of VOS is chosen 0 to be (1/4)∆V . As expected, the maximum probability for VOS occurs at VOS . The 0 probability of VOS is diminishing when the distance to VOS is increased.. From P (VOS ), both the mean µ(VOS ), and the standard deviation σ(VOS ) of VOS can be calculated. The value of µ(VOS ) is always zero. This is enforced by the calibration 0 feedback mechanism. The value of σ(VOS ) depends on ∆V , NC , and VOS . If VF S is much 0 larger than ∆V so that P ∆P , the effect of VOS on σ(VOS ) becomes insignificant.. Fig. 2.12 shows the ∆V and NC dependence of σ(VOS ) for a middle BCC in the 0 6-bit ADC design case. The VOS dependence of σ(VOS ) is neglected since P ∆P .. The σ(VOS ) can be reduced by decreasing ∆V or increasing NC , but at the expense of increasing the convergence time constant τc . To achieve σ(VOS ) < (1/3) LSB in the 6bit ADC design case, one can choose ∆V = (1/8) LSB and NC = 25 for short τc , or ∆V = (1/2) LSB and NC = 28 for long τc . At circuit level, smaller ∆V is more difficult to implement if the offset adjust range is required to be the same. In this case, more digital bits are required for offset control..

(49) 2.3. BACKGROUND-CALIBRATED COMPARATOR. 29. 0.5. Probability. 0.4. Calculation Simulation. 0.3. 0.2. 0.1. 0 -2. -1. 0. 1. VOS / LSB Figure 2.11: P (VOS ) of a BCC example.. 2.

(50) 30. CHAPTER 2. DIGITAL CALIBRATION FOR THE COMPARATORS. 1.2 SB )L 1/2 =( SB ∆V )L 1/3 B =( LS ∆V 1/4) =( ∆V. σ(VOS) / LSB. 1 0.8 0.6. ∆V=(1/8)LSB. 0.4. ∆V=(1/7)LSB. 0.2 0 0. ∆V=(1/5)LSB. ∆V=(1/6)LSB. 1. 2. 3. 4. 5. log2 NC Figure 2.12: σ(VOS ) versus NC. 6. 7. 8.

(51) Chapter 3 Flash ADC with Digitally Calibrated Comparators 3.1 3.1.1. Input Windowing Technique Input Dependent Issues. The background-calibrated comparator(BCC), which is shown in Fig. 2.7, is designed to replace each comparators in a flash ADC. In the BCC, its CP is activated if the corresponding output Dc = 1, and the offset formation is available only when Vi falls within ∆P regions of Fig. 2.2. Since the VR,j for each BCC is different, and the input signal may not be a sine wave in practical applications, several issues need to be addressed while applying BCC into a real ADC design case: 1. Null-information input condition When the PDF of Vi has zero value near VR,j for a period of time, the jth BCC experiences a condition with ∆P = 0. This condition is illustrated in Fig. 3.1. The corresponding CP perceives no meaningful information about VOS . Since P 6= 0, VOS of the jth BCC may wander around the null-information region where ∆P = 0. This wandering phenomenon does not affect the quality of the ADC output as long as ∆P remains zero. However, as soon as the input condition is changed so that ∆P 6= 0, the ADC may suffer a large VOS at the jth BCC before its CP can make the 31.

(52) 32 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. PDF 2VOS,j. ∆ P=0 P . V R,1. V R,j. V R,2N−1. Vi. Figure 3.1: Null-information input condition.. PDF. 2VOS,j. ∆PP V R,1. V R,j. V R,2N−1. Vi. Figure 3.2: Small ∆P/P ratio in a real ADC case. necessary correction. 2. Small ∆P/P ratio The calibration is based on the detection of ∆P and hence the polarity of VOS . However, the comparator output contains offset information together with noise corresponding to Vi falling within P . This noise causes VOS fluctuation and is suppressed by the AAR loop. When applying BCC into an ADC, VOS of a single BCC is quite small compared with the ADC input swing range. The resultant small ∆P/P ratio is shown in Fig. 3.2. This condition leads to rare offset information accompanied with large noise, and thus the calibration loop introduces large VOS fluctuation. 3. Location dependent ∆P/P ratio In a flash ADC, different comparators are associated with different VR,j values, thus.

(53) 3.1. INPUT WINDOWING TECHNIQUE. PDF. 33. 2VOS. ∆ P P V R,1. V R,2 −1 N. Vi. (a). PDF. 2VOS. ∆P P V R,1. V R,2 −1 N. Vi. (b). Figure 3.3: Location-dependent ∆P/P ratio: (a) for the bottom comparator; (b) for the top comparator..

(54) 34 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. VR,3. VR,63. VR,2. VR,1. Vi BCC. q. 1. q. BCC. D c,63. 1. D c,3. q. BCC. 2. D c,2. q 1. BCC. D c,1. Thermometer−Code Edge Detector (TCED) D e,63. D e,3. D e,2. Encoder ROM. D e,1. 6. Do. Figure 3.4: Flash ADC incorporating input-windowed BCCs. perceives drastically different P values even if the input signal has an uniform distribution. This condition is illustrated in Fig. 3.3. It leads to different ∆P/P ratio for different comparators. For example, the comparator corresponding to the top-end reference level has a much greater ∆P/P ratio than the comparator corresponding to the bottom-end reference, since the former one has a relatively small P value. This condition complicates the choice of NC and ∆V parameters for each BCC if VOS fluctuation is considered.. 3.1.2. Input Windowing. The issues described in subsection 3.1.1 can be resolved by input windowing technique shown in Fig. 3.4. In this architecture, the BCC output Dc,j are fed to a thermometercode edge detector(TCED), where 1 ≤ j ≤ (2N − 1). Output of the TCED is a series of 0 except the bit in which the 0-to-1 edge of the thermometer code is located. This edge code is denoted with De,j for 1 ≤ j ≤ (2N − 1). By Fig. 3.4, the TCED simply consists of two-input AND gates, so that De,j = 1 if Dc,j = 1 and Dc,j+1 = 0. The CP of the jth BCC uses De,j , instead of Dc,j , as its input. With this arrangement, the jth CP is activated only when Vi appears within VR,j + qj VOS,j and VR,j+1 + qj+1 VOS,j+1 . In most flash ADC designs, the TCED is a building block of the.

(55) 3.1. INPUT WINDOWING TECHNIQUE. 35. 2VOS,j. PDF. ∆P P V R,j−1. V R,j+1. V R,j. V R,j+2. Vi. 1 LSB Figure 3.5: Input windowing for the jth BCC.. back-end encoder, thus no extra hardware is required for the proposed architecture. The arrangement of Fig. 3.4 introduces a windowing effect which can reduce the P value perceived by each BCC. As illustrated in Fig. 3.5, the P region for the jth BCC is now confined between (VR,j + VOS,j ) and VR,j+1 .The actual upper bound for the P region is either (VR,j+1 − VOS,j+1 ) or (VR,j+1 + VOS,j+1 ), depending on the random sequence qj+1 . The averaged value of VR,j+1 is used in Fig. 3.5. With this windowing mechanism, the ∆P/P ratio for every BCC is drastically increased, resulting in smaller VOS fluctuation. In addition, the difference in ∆P/P between different BCCs is also reduced in most input input cases, thus all BCCs in the ADC can employ identical NC and ∆V for offset calibration. The phenomenon of VOS wandering due to null-information input condition can still occur. However, if ∆V is assumed to be infinitesimal, the maximum distance around which VOS,j can wander is 1 LSB, which is the difference between VR,j and VR,j+1 . Whenever VOS,j ≥ 1 LSB, P becomes zero and VOS,j can no longer wander. Thus, for a properly designed ADC of Fig. 3.4, its worst-case differential nonlinearity (DNL) is 1 LSB plus the ∆V step size..

(56) 36 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. 3.1.3. Threshold Level Crossing. The windowing effect introduced by the TCED becomes complicated when the threshold levels of the BCC array are not monotonic. For jth BCC, the actual threshold level may deviate from the nominal level due to input offset voltage, and can be expressed as: Vt,j = VR,j + qj × VOS,j. (3.1). where qj ∈ {+1, −1} is the random sequence. The difference between two adjacent reference levels is one LSB, i.e., VR,j+1 − VR,j = 1 LSB. Under normal condition with VOS,j 1 LSB, we have Vt,j−1 < Vt,j < Vt,j+1 for all j. However, during the initial phase of calibration, it is possible that VOS,j > (1/2) LSB at some locations. This threshold level crossing is illustrated in Fig. 3.6. Threshold level crossing does not corrupt the calibration but slow down the converging speed a bit. The effect can be seen from Fig. 3.6b. Here the VOS of the jth BCC is assumed to be a positive value. When q = +1, the jth threshold level moves up above the (j+1). th. in the left of Fig. 3.6b, hence the output of (j+1) th BCC will certainly be 1 as the output of jth BCC becomes 1. From Fig. 3.6a, it is obvious that De,j will always be 0 in this case. When q = −1, the jth threshold level moves down under the (j-1) th , and the probability for De,j = 1 is the shadowed region in the right of Fig. 3.6b. Comparing Fig. 3.6b with Fig. 2.2, the accumulated (q × De,j ) still tend to the negative direction, although the tendency may be more gradual. The calibration loop thus operates correctly. As soon as VOS is trimmed less than 1 LSB, the threshold level crossing disappears and the converging speed of the calibration is recovered.. 3.1.4. Upward Locking. Due to the TCED, the offset perception of jth BCC may be interfered by (j+1) th BCC and thus the calibration locked. This upward locking phenomenon is illustrated in Fig. 3.7. As an example, it is assumed that VOS,j and VOS,j+1 are both positive, VOS,j < VOS,j+1 , and the jth and (j+1). th. BCC are controlled by the same random sequence q. The proba-. bility for De,j = 1 is shown as the shadowed region in Fig. 3.7b. Compared with Fig. 2.2,.

(57) 3.1. INPUT WINDOWING TECHNIQUE. 37. Vi. V R,j+1 D e,j V R,j V OS,j (a). Vi. V R,j+1. V R,j. VOS. V R,j V R,j−1 PDF. PDF. q = +1. V i V R,j+1 VR,j VR,j−1 V R,j VOS q=. 1. (b). Figure 3.6: Effect of threshold level crossing: (a)jth TCED and the preceded comparators; (b) probability of De,j =1..

(58) 38 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. Vi. V R,j+1. V OS,j+1 D e,j. V R,j. PDF. VR,j+1 V R,j . V OS,j (a). V R,j+1. V R,j. V OS,j+1. V OS,j. PDF. q = +1. V R,j+1 V R,j+1 V OS,j+1 V R,j V V R,j OS,j q=. 1. (b). Figure 3.7: Upward locking caused by offseted threshold levels: (a)jth TCED and the preceded comparators; (b) probability of De,j =1..

(59) 3.1. INPUT WINDOWING TECHNIQUE. 39. the integration of (q × De,j ) tends to incline upward because the larger VOS,j+1 expand the shadowed region for q = +1 and compress the region for q = −1. Since the jth calibration processor does not have any information about VOS,j+1 , the calibration for jth comparator will diverge due to the positive tendency of q × De,j . The calibration divergence will increase VOS,j until VOS,j = VOS,j+1 and then the upward locking is dismissed. In the case that the input distribution is extended to the upmost comparator, the upward locking forces the offset voltage of the upmost comparator VOS,2N −1 to converge to 0 sooner than other ones. Followed by VOS,2N −1 is the offset voltage next to it, VOS,2N −2 . Its convergence depends on VOS,2N −1 and will be slower than VOS,2N −1 . Followed by VOS,2N −2 is VOS,2N −3 , and so on. In the case that the input distribution is only extended to some reference level VOS,m , all comparator offset voltages corresponding to the lower reference levels will be confined by VOS,m and may never be calibrated to 0, unless there is some inherent comparator offset smaller than VOS,m . To eliminate the upward locking phenomenon, two independent random sequences are used for even and odd BCCs respectively. This configuration has been illustrated in Fig. 3.4 and the probability for De,j = 1 is shown in Fig. 3.8. Since qj is independent of qj+1 , the jth calibration processor perceives an averaged VOS,j+1 , which is equal to 0. It is shown in Fig. 3.8a. The shadowed region in Fig. 3.8b becomes exactly the same as in a single random-chopping comparator in Fig. 2.2.. 3.1.5. Offset Fluctuation. Since VOS,j for all j will be trimmed to less than (1/2) LSB after the calibration process converges, the threshold level crossing effect is eliminated, and the fluctuation analysis for the jth BCC is reduced to the calculation of the probability mass function P (VOS ) for a simple BCC. From Fig. 3.5, we have ∆P/P = 2VOS /(LSB − VOS ). It is assumed that the input signal is uniformly distributed within the window. Then we can calculate P (VOS ) using the procedures described in the Appendix. Notably, the P (VOS ) depends on ∆P/P , ∆V , and NC only. The larger probability of R = 0 introduced by the windowing effect does.

(60) 40 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. Vi. V R,j+1 D e,j V R,j V OS,j. V R,j . (a) comparators with thermometer-code edge detector.. PDF. q = +1. V R,j+1 V R,j V OS,j. PDF. V R,j q=. V R,j+1. V R,j. V OS,j. 1. (b) probability of De,j =1. Figure 3.8: Upward-locking-free operation: (a)jth TCED and the preceded comparators; (b) probability of De,j =1..

(61) 3.1. INPUT WINDOWING TECHNIQUE. 41. 0.4. σ(VOS) / LSB. 0.3 0. |VOS| = 0.5∆V. 0.2 0. |VOS| = 0.1∆V 0. |VOS| = 0.3∆V. 0.1. |V 0 O. S|. 0. |VOS| = 0.2∆V. 0 0. 1. 2. 3. 4. 5. =0. 6. 7. log2 NC Figure 3.9: σ(VOS ) of a windowed BCC in a 6-bit ADC not affect P (VOS ). Fig. 3.9 shows the calculated standard deviation of VOS for a windowed BCC, which is represented as σ(VOS ). The 6-bit ADC design case with ∆V = (1/2) LSB are assumed. 0 VOS denotes the offset control step closest to the comparator threshold level. 0 Unlike the calculation results shown in Fig. 2.12, the influence of VOS on P (VOS ). becomes evident due to a much larger value of the ∆P/P ratio. As NC increases, the 0 σ(VOS ) decreases and is saturated at different value for different VOS . The worst-case 0 saturation value for the σ(VOS ) occurs at |VOS | = (1/2)∆V . In this case and with large. NC , the VOS stays at either +(1/2)∆V or −(1/2)∆V , resulting in σ(VOS ) = (1/2)∆V = (1/4) LSB. Fig. 3.10 shows the ∆V and NC dependence of the σ(VOS ). The 6-bit ADC case using 0 windowed BCCs and the worst-case |VOS | = (1/2)∆V are assumed. Comparing with.

(62) 42 CHAPTER 3. FLASH ADC WITH DIGITALLY CALIBRATED COMPARATORS. 0.4. σ(VOS) / LSB. 0.3 ∆V=(1/2)LSB. 0.2. ∆V=(1/3)LSB ∆V=(1/4)LSB ∆V=(1/5)LSB. 0.1 ∆V=(1/6)LSB ∆V=(1/7)LSB. 0 0. 1. 2. ∆V=(1/8)LSB. 3. 4. 5. 6. 7. log2 NC 0 Figure 3.10: Worst-case σ(VOS ) with VOS = (1/2)∆V .. Fig. 2.12, the σ(VOS ) corresponding to the same ∆V and NC is reduced drastically by using windowed BCCs.. 3.2. A 6-bit ADC Design Case. In this section, system simulation is performed for an exemplified ADC design case illustrated in Fig. 3.4. All BCCs identically have ∆V = (1/4) LSB and NC = 16. They are also introduced with random offsets in the initial. The distribution for these random offset is a Gaussian distribution with a standard deviation of 2 LSB. The input signal for the ADC simulation is a full-range sine wave. The offset fluctuation of each BCC is ergodic, and there are 2N − 1 BCCs in this case, thus the ensemble standard deviation of the BCC array, instead of the standard deviation.

(63) 3.2. A 6-BIT ADC DESIGN CASE. 43. 2. σs(VOS) / LSB. 1.5 st. 1 order approximation. 1 Triangular wave as input signal Sine wave as input signal. 0.5. 0.13 0 0. 10000. 20000. 30000. 40000. 50000. k Figure 3.11: Transient behavior of a 6-bit ADC design case. of individual BCC, is checked here. There is no need to collect the offset data along the time axis for the calculation of the ensemble standard deviation, thus the offset fluctuation can be verified at each time index. Fig. 3.11 shows the transient behavior of the ensemble standard deviation of VOS , which is represented as σs (VOS ), from the simulation of the 6-bit ADC example. In Fig. 3.11, σs (VOS ) is initially set to 2 LSB. As calibration proceeds, it is forced to settle to a small but non-zero value. This value is closed to 0.13 LSB, which is consistent with the result of Fig. 3.10. As expected, the input signal affects the calibration transient behavior. Simulation with triangular-wave input, which has an uniform PDF, settles faster than the case with sine-wave input. Also plotted in Fig. 3.11 is the approximation of (3.2) and (2.8). The time constant is τc = NC × 26 × 4 = 4096. From (2.8), it will take 2.73τc , which is ap-.