InAs-based heterostructure field-effect
transistor using AlAs
0.16Sb
0.84double
barriers
Yue-Min Lin, Kun-Ping Lin, Ting-Chi Lee, Meng-Ying Li
and Chien-Ping Lee
An InAs-channel heterostructurefield-effect transistor on GaAs sub-strates is presented. The conduction channel was formed by the InAs/AlAs0.16Sb0.84/AlSb quantum well. With the addition of the
AlAs0.16Sb0.84layer, holes that are generated by impact ionisation at
high voltages are effectively confined in the InAs channel because of the largeΔEv in this type-I heterostructure. By suppressing the hole injection into and accumulation in the buffer layer, the feedback through the back gate is eliminated and excellent output characteristics were obtained. The fabricated devices had a threshold voltage of about −0.6 V with a channel mobility of 18 100 cm2
/V-s and a sheet carrier density of 1.2 × 1012cm−2.
Introduction: In(As,Sb)/(Al,Ga,In)Sb-based heterostructures have attracted much attention owing to their potential applications in high-speed, low-power electronic devices [1] and long-wavelength lasers and detectors. Heterostructurefield-effect transistors (FETs) built with the InAs/AlSb material system have been widely studied because of the high electron mobility and easily obtainable high sheet electron den-sities. However, almost all devices reported in the literature show very poor DC characteristics, with high drain conductance, which increases rapidly with drain voltage [2–4]. Owing to the narrow energy gap, ∼ 0.36 eV for InAs, impact ionisation occurs easily when the drain bias exceeds the energy gap in the channel. Furthermore, because of the staggered band lineup in the InAs/AlSb-based system, where the valence band edge of the AlSb barriers lies above that of the InAs channel [5,6], the holes generated by impact ionisation are not confined in the InAs channel. Some of them are swept to the negatively biased gate, resulting in a gate leakage current, and others escape into the AlSb buffer layer. The accumulated positive charges in the buffer layer act like a positively biased back gate, giving rise to an increased electron currentflow in the channel by the feedback mechanism [2].
One of the most effective ways [2,4,7,8] to solve the problem men-tioned above is to add a barrier beside the channel to block the hole injection into the buffer layer. However, to fabricate a type-I heterostruc-ture using InAs as the channel is not trivial. Sb-based compounds, which have a similar lattice constant as InAs, usually have a staggered band alignment with InAs with a negativeΔEv. Replacing the InAs channel with InAs0.8Sb0.2, a hole blocking barrier with ΔEv ∼ 0.1 eV can be
obtained using AlSb as the barrier [6]. Owing to the small barrier height, Lin et al. [4] adopted the idea of using an additional planar n-type-doped layer in the buffer to boost the barrier height and the hole confinement [8]. However, this may potentially cause subthreshold leakage and soft pinch-off problems due to the parallel conduction of this doped layer. Besides, the electron mobility is usually reduced in the InAs0.8Sb0.2channel because of the additional alloy scattering. To
increase quantum confinement for holes and at the same time maintain high electron mobility, in this Letter we incorporate an additional con-fining layer, AlAs0.16Sb0.84, between the InAs channel and the AlSb
bar-riers. This layer forms type-I band alignment with the channel layer and very effectively confines the holes in the channel. In this way, we suc-cessfully removed the feedback path caused by the holes leaking into the buffer/substrate, thus resulting in much improved DC characteristics and a wider usable drain voltage range. Devices with the InAs channel and InAs/InAs0.8Sb0.2 channels have been fabricated. The effect of the
additional AlAs0.16Sb0.84barrier layer is clearly seen.
Materials growth and device fabrication: The samples for this Letter were grown by a solid-source molecular beam epitaxy system on (001) semi-insulating GaAs substrates. The layer structure used in this Letter is shown in Fig.1. First, a GaAs buffer layer of 100 nm was grown at 580°C to obtain a smooth surface. A 1.3μm relaxed meta-morphic AlSb buffer layer grown at 520°C followed to accommodate the lattice mismatch between the channel layer and the GaAs substrate. The active region consisting of AlAs0.16Sb0.84 /InAs/AlAs0.16Sb0.84
(4 nm/13 nm/4 nm) was then grown on top of the buffer layers. The AlAs0.16Sb0.84 layer, which forms a type-I heterojunction with the
InAs channel (ΔEv ∼ 0.3 eV) [5], serves as a barrier for the holes
generated by the impact ionisation in the channel. A 6 nm-thick AlSb top barrier and a 4 nm-thick highly lattice-mismatched In0.5Al0.5As
cap layer were then grown. The In0.5Al0.5As layer keeps the underlying
layers from oxidation and forms a good Schottky barrier with the metal gate. All of them were grown at 500°C except the InAs channel, which was grown at 470°C. The growth rate was 0.65 ML/s for the AlSb and AlAs0.16Sb0.84layers. The InAs channel was grown at 0.2 ML/s and the
In0.5Al0.5As cap layer was grown at 0.45 ML/s. An InSb-like interfacial
layer was inserted at the InAs/AlAs0.16Sb0.84interface to enhance the
electron mobility in the channel. The carriers in the channel were pro-vided by a Te delta-doped layer at the upper AlAs0.16Sb0.84/AlSb
inter-face. Owing to the largeΔEv in our structure, no additional doped layer was used in the buffer to boost the hole confinement. The band diagram of the InAs/AlAs0.16Sb0.84/AlSb quantum well is shown in Fig.2. Both
electrons and holes are confined in the InAs channel. With this added AlAs0.16Sb0.84 barrier, a hole confining barrier of ΔEv ∼ 0.3 eV is
obtained. We have also prepared FETs with InAs/InAs0.8Sb0.2
com-posite channels with and without the AlAs0.16Sb0.84barriers for
compar-ison. The layer structure and the growth procedure were the same except the channel.
S.I. GaAs substrate
InAs channel AISb buffer 1.3 mm AISb Te delta-doping S G D In0.5Al0.5As AIAs0.16Sb0.84 AIAs0.16Sb0.84
Fig. 1 Complete structure used in this Letter
–1.5 –1.0 –0.5 0 0.5 1.0 1.5 In0.5Al0.5As AlAs0.16Sb0.84 AlSb InAs energy, eV AlSb Te 0 10 20 30 40 50 60
distance from surface, nm metal
Fig. 2 Band diagram of InAs/AlAs0.16Sb0.84/AlSb quantum well
The devices were fabricated using a conventional planar process. First, the source and drain ohmic contacts were fabricated. Pd/Ti/Pd/ Au was used as the ohmic metal. Then, device mesas were defined by a dry etching process using Ar/SiCl4for device isolation. The etch
stopped at the AlSb buffer layer, which was then covered by a 400 nm-thick Si3N4layer to prevent AlSb from oxidation [9]. The Ti/
Au Schottky gates and bonding pads were then defined to complete the process.
Results and discussion: The surface of the grown samples was very smooth. The surface roughness measured by atomic force microscopy had a root mean square of ∼0.5 nm. For the FETs with the InAs chan-nels, the contact resistance and sheet resistance, measured by the trans-mission line method, were typically 0.2Ω mm and ∼300 Ω/sq, respectively. The room temperature electron mobility and the sheet carrier density in the channel, determined by the Hall measurement, were 18 100 cm2/V-s and 1.2 × 1012cm−2, respectively. The source/
drain series resistances, Rs/Rd, were estimated to be 0.3Ω mm in the case of 1μm source-to-gate spacing. Fig.3a shows the typical room temperature I–V characteristics of our devices with a 2 μm-long gate. The device was in depletion mode with a threshold voltage of about −0.6 V. Compared with the devices made with the InAs/AlSb-based system [2–4], our devices had much improved saturation behaviour. Owing to the elimination of the feedback route that brings about the deleterious enhancement of the drain current during impact ionisation, dramatic improvements in the output characteristics were obtained. Fig. 3b shows the drain current and transconductance against gate
voltage at drain biases of 0.4 and 0.7 V. A peak transconductance of 340 mS/mm was obtained. a b 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 30 60 90 120 150 180 Vgs: top = 0 V, step = –0.1 V, bottom = –0.7 V Lg = 2 mm, W = 100 mm –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0 30 60 90 120 150 180 0 60 120 180 240 300 360 Lg = 2 mm W = 100 mm Vds = 0.4 V Vds = 0.7 V IDS , mA/mm IDS , mA/mm Gm , mS/mm VDS, V VGS, V
Fig. 3 Typical room temperature I–V characteristics of our devices with 2-μm long gate (Fig.3a), and drain current and transconductance against gate voltage at drain biases of 0.4 and 0.7 V (Fig.3b)
a b 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 30 60 90 120 150 180 IDS , mA/mm IG , mA/mm VDS, V VGS, V
without AlAs0.16Sb0.84 barrier Vgs: top = 0 V, step = –0.1 V, bottom = –0.9 V Lg = 2 µm, W = 100 µm –1.0 –0.8 –0.6 –0.4 –0.2 0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
without AlAs0.16Sb0.84 barrier Vds: top = 0.3 V, step = 0.1 V,
bottom = 0.8 V
W = 100 µm
Fig. 4 I–V characteristics of composite channel device without AlAs0.16Sb0.84
double barriers (Fig.4a), and gate leakage current against gate voltage at different drain voltages for same device (Fig.4b)
a b IDS , mA/mm IG , mA/mm VDS, V VGS, V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 30 60 90 120 150 180
with AlAs0.16Sb0.84 barrier Vgs: top = 0 V, step = –0.2 V bottom = –1.2 V Lg = 2 mm, W = 100 mm –1.0 –0.8 –0.6 –0.4 –0.2 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0
with AlAs0.16Sb0.84 barrier
Vgs: top = 0 V, step = 0.1 V bottom = 0.7 V
W = 100 mm
Fig. 5 I–V characteristics of composite channel device with AlAs0.16Sb0.84
double barriers (Fig.5a), and gate leakage current against gate voltage at different drain voltages for same device (Fig.5b)
For devices with a composite (InAs0.8Sb0.2/InAs/InAs0.8Sb0.2)
channel, we have compared the ones with and without the AlAs0.16Sb0.84barriers beside the channels. Figs.4a and b are the I–V
curves and the gate leakage plot for the device without the barriers and Figs. 5a and b are the ones from the device with the AlAs0.16Sb0.84barriers. Comparing the gate leakage characteristics of
Figs.4b and 5b, we can clearly see the difference between the two devices. The one without the blocking barriers shows bell-shaped curves. This is a clear indication of hot hole injection into the gate from the channel due to impact ionisation. Moreover, for the device with the AlAs0.16Sb0.84 barriers, the gate leakage shows a normal
monotonically increasing behaviour and the leakage is much lower. This is a direct result of the hole blocking barrier above the channel. It is also noticed, by comparing Figs.4a and5a, that the output conduc-tance of the device with the barriers is better than that of the device without the barriers. So even for the composite channel devices, the additional barrier at the bottom of the channel provides a better blocking for the holes that may otherwise go into the buffer layer causing a posi-tive feedback for the channel current to raise the output conductance. Conclusion: To improve the output characteristics of InAs-based FETs and to overcome the poor confinement for holes in the InAs channel, we have adopted an InAs/AlAs0.16Sb0.84/AlSb quantum well design for the
channel. The type-I quantum well has a hole barrier ofΔEv ∼ 0.3 eV to suppress the hole injection into the buffer layer. With the reduction of the feedback loop, the output I–V characteristics and the usable drain voltage range are greatly improved.
Acknowledgments: This work was supported in part by the National Science Council of Taiwan under contract no. NSC99-2221-E-009-079-MY3, in part by the Center for Nano Science and Technology of National Chiao Tung University and in part by the Nano Facility Center of National Chiao Tung University, Hsinchu 30010, Taiwan.
© The Institution of Engineering and Technology 2014 21 February 2014
doi: 10.1049/el.2014.0629
Yue-Min Lin, Ting-Chi Lee, Meng-Ying Li and Chien-Ping Lee (Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan)
E-mail: [email protected]
Kun-Ping Lin (Department of Electronic Engineering, National Changhua University of Education, Changhua 500, Taiwan)
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