Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

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Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory

fabricated by a simple sidewall spacer formation

Chun-Yu Wu

a

_{, Ta-Chuan Liao}

a

_{, Ming-H Yu}

a

_{, Sheng-Kai Chen}

a

_{, Chung-Min Tsai}

b

_{, Huang-Chung Cheng}

_a,* a

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

b

Department of Materials Science and Engineering, Nation Tsing-Hua University, Hsinchu, Taiwan

a r t i c l e

i n f o

Article history:

Received 30 November 2009

Received in revised form 8 January 2010 Available online 18 February 2010

a b s t r a c t

A novel omega-shaped-gated (X-Gate) poly-Si thin-film-transistor (TFT) silicon–oxide–nitride–oxide–sil-icon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. TheX-Gate structure inherently covered two sharp corners manufactured simply via a side-wall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, theX-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, theX-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an X-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications.

1. Introduction

Low-temperature poly-Si thin-ﬁlm-transistors (LTPS–TFTs) have been put emphasis not only on the switching pixel elements but also the integrated peripheral driving circuit in the same glass substrate to meet the system-on-panel (SOP) applications[1,2]. In order to realize the low-cost, thinner and lower-power portable electronic products, integration of various functional memories and controllers in a chip is necessary for value-added SOP applica-tions[3]. It is well known that the nonvolatile memory (NVM) is popularly used for portable memory because of the superior device durability and power saving. In addition, due to the potential de-vice scalability, silicon–oxide–nitride–oxide–silicon (SONOS)-type devices, instead of traditional ﬂoating-gate ones, have been consid-ered as a promising NVM candidate for SOP applications[4].

However, unlike floating gate NVM, the conventional planar (CP) TFT SONOS memories lack the gate-coupling design, thus suf-fering form the insufficient programming/erasing (P/E) efficiency

[5]. To overcome these problems, various ﬁeld-enhancement mem-ory structures with edge corner, such as tri-gate[6]or pi-gate[7]

nanowire TFT memories fabricated by e-beam lithography meth-ods have been demonstrated to enhance P/E efﬁciency. Although the memory characteristics could be improved by device structure schemes, e-beam lithography was an expansive and

low-through-put process, resulting in the cost concern. Likewise, another field-enhancement metal–oxide–nitride–oxide–polysilicon (MONOS) memory using sequential lateral solidified (SLS) crystallization method has been reported for the enlargement of the memory window[8]. Yet, the locations and heights of SLS tips were difficult to control which might arise the process complexity and device variation issues[9].

In this work, a simple and low-cost process was proposed to construct a novel ﬁeld-enhanced structure on poly-Si TFT SONOS with X-Gate structure. Especially, the X-Gate TFT SONOS pos-sessed excellent transistor performance and memory characteris-tics, thanks to the improved X-Gate controllability and the sharpened corner geometry.

2. Device fabrication

The process sequence ofX-Gate poly-Si TFT SONOS device is schematically shown inFig. 1 [10]. A 1.0-

l

m-thick thermal SiO2

was ﬁrst grown on single crystal silicon wafers for substituting glass substrate. Then, an etch-stop layer of Si3N4 (50-nm-thick)

and a sacriﬁcial layer of TEOS SiO2(300-nm-thick) were

sequen-tially deposited through the low pressure chemical vapor deposi-tion (LPCVD) system. After the sacriﬁcial SiO2 layer was

anisotropic etched with several dummy strips (100-nm depth) by reactive ion etch (RIE) process (Fig. 1a), a 100-nm-thick a-Si ﬁlm was conformally deposited by LPCVD at 550 °C. The source/drain pad photoresist (PR) was then patterned to overlap on the two

*Corresponding author. Tel.: +886 571 2121x54218; fax: +886 573 8343. E-mail address:[email protected](H.-C. Cheng).

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ends of those dummy strips, and followed by an anisotropic RIE process to remove a-Si layer; meanwhile, pairs of a-Si sidewall spacer with a common source/drain (S/D) pad were in situ resided against both sidewalls of SiO2dummy strips (Fig. 1b). The a-Si ﬁlm

was then transferred into poly-Si by solid phase crystallization at 600 °C for 24 h in N2ambient. Next, the diluted hydro-ﬂuoric acid

(DHF) solution was used to etch the SiO2strip for 25-nm-thick,

thus the external two sharp corners were exposed and the other one was still bound with the reminder SiO2strip to support the

poly-Si nanowire (Fig. 1c).

Afterwards, the oxide–nitride–oxide (ONO: 3 nm/10 nm/6 nm) layer and 200-nm-thick phosphorous in situ doped poly-Si (with a doping level of 5 1019_cm 3_{) were sequentially deposited to}

encompass two sharp corners and bevel edge of poly-Si spacer nanowires by LPCVD system.Fig. 2shows the cross section trans-mission electron microscopy (XTEM) image of poly-Si spacer nano-wire covered with ONO dielectrics and poly-SiX-Gate. According to XTEM photograph, the gate-covered width of the fabricated de-vice was 168 nm. It was worth mentioning that theX-Gate poly-Si TFT SONOS was fabricated by simple sidewall spacer formation without any advanced lithography[6,7]. Subsequently, the in situ doped poly-Si was patterned and etched to form the gate electrode (Fig. 1d). After self-aligned phosphorous S/D implantation (at 30 keV to a dose of 5 1015_cm 2_{), the 300-nm-thick passivation}

oxide deposition and S/D activation were sequentially performed. Finally, the contact opening and metallization were progressed. For the purpose of comparison, the conventional planar (CP) poly-Si TFT SONOS memory devices were also manufactured by using the same process sequence.

3. Results and discussion

The Fowler–Nordheim (FN) tunneling mechanism was em-ployed in this paper for both theX-Gate and CP-TFT SONOS mem-ory operations. For the programming and erasing operation, positive and negative voltage pulses were given at VGS= ±12 V

while S/D was grounded. The gate length (L) and channel width (W) of measured device were 1

l

m and 2.7

l

m, accordingly. The channel width ofX-Gate TFT SONOS was deﬁned by 16 nanowires with 8-strips structure[10].

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(a)

(c)

(d)

Fig. 1. Schematic diagrams of the fabrication process steps of the proposedX-Gate TFT SONOS: (a) the patterning of the dummy-oxide strips; (b) after source/drain (S/D)-pad lithography and its RIE process, couples of spacer nanowires were in situ resided against the sidewall of those designed strips and naturally connected to the S/D pads, which were formed to be the device active region, (c) the diluted hydro-ﬂuoric acid (DHF) solution was used to etch the SiO2strip for 25-nm-thick, and (d) the gate electrode

patterning.

Twin Sharp

Corners

O N O

Twin Sharp

Corners

O N O

Omega-Shaped

Gate

Fig. 2. The cross section transmission electron microscopy (XTEM) image of theX -Gate TFT SONOS structure with ONO dielectric conformally deposited on the two sharp corners and bevel edge of poly-Si spacer nanowires.

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The threshold voltage (Vth) was extracted by the constant drain current method and threshold current was speciﬁed at 10 nA (W/ L) for VDS= 0.1 V.Figs. 3 and 4present the measured transistor and

memory characteristics of bothX-Gate and CP-TFT SONOS devices, correspondingly. The initial Vth and subthreshold swing (SS) were 4.24 V and 635 mv/decade for the CP-TFT, while those values were 1.17 V and 289 mv/decade for theX-Gate TFT. It could be found that the transfer characteristics of freshX-Gate SONOS displayed larger on-current, smaller Vth and SS, as compared to CP devices. This was because the X-Gate structure possessed superior gate control capability by means of 3D device geometry[7].

Fig. 5a and b shows the programming and erasing speeds of the

X-Gate SONOS and CP SONOS, respectively. For the programming operation, the X-Gate SONOS exhibited a larger Vth shift of 3.02 V in 1 ms as compared to that of 1.34 V for CP one. Further-more, the erase characteristics also showed the similar trend that the X-Gate SONOS devices were much faster (a Vth shift of 2.97 V in 1 ms) than the CP counterparts (a Vth shift of 0.84 V in 1 ms). As seen clearly, the Vth shift ofX-Gate SONOS in 1

l

s pro-gramming time at VGS= 12 V was 1.46 V, while CP SONOS required

more than 1 ms programming time to achieve the identical Vth shift ofX-Gate SONOS. Therefore, the programming speed ofX -Gate SONOS at VGS= 12 V was about 1000 times larger than that

for CP device, and the erasing speed ofX-Gate SONOS at VGS= 12 V

was nearly 100 times higher than that for CP one. Since during the

X-Gate SONOS operation, the local electric field of channel/tunnel-ing oxide interface could be enhanced effectively through the two sharp corners and thereby improve the P/E efficiency. Additionally, the electric field in the blocking oxide was deservedly diminished

accompanying the suppression of electron back-injection from the gate[11]. In contrary, the CP SONOS structures did not have such corner effect; hence displayed the poor P/E activity. The endurance characteristics ofX-Gate SONOS under a program bias of 10 V for 1 ms and erase bias of 12 V for 1 ms are shown inTable 1. TheX -Gate SONOS revealed a good endurance that the memory window was well maintained with a small reduction after 10 K P/E cycles. One point was worth making aboutTable 1, since the trap charges in the deep level traps of silicon nitride were not easy to remove, both the Vth of program and erase states were shifted slightly up-ward with cycling stress[7]. After memory operation, it was desir-able to maintain the data as long as possible. Consequently, it was important to estimate the memory window for over 10 years.Fig. 6

shows the retention characteristics ofX-Gate SONOS after 1 cycle and 10 K cycles. The memory window of 10 K cycles would be re-mained 1.1 V after extrapolating to retention time of 10 years, which was almost equal to the memory window of 1 cycle (1.2 V). In order to demonstrate the enhancement of the sharp-corner electric ﬁeld across the ONO dielectrics in theX-Gate SONOS, a numerical simulation was also carried out using ISE. Fig. 7

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

I

DS

(A)

V

_GS

(V)

Initial 1E-6 sec 1E-5 sec 1E-4 sec 1E-3 sec 1E-2 sec Ω-Gate TFT SONOS Program bias: V_GS = 12V, V S = VD = 0V -2 -1 0 1 2 3 4 5 6 7 -2 -1 0 1 2 3 4 5 6 7 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 Initial 1E-6 sec 1E-5 sec 1E-4 sec 1E-3 sec 1E-2 sec

I

DS

(A)

V

_GS

(V)

Erase bias: V GS = -12V, V S = VD = 0V Ω-Gate TFT SONOS

(a)

(b)

Fig. 3. The IDS–VGScurves ofX-Gate TFT SONOS with: (a) programming and (b)

erasing operation at VGS= ±12 V. 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 Initial 1E-6 sec 1E-5 sec 1E-4 sec 1E-3 sec 1E-2 sec

I

DS

(A)

V

_GS

(V)

Program bias: V_GS = 12V, V S = VD = 0V CP TFT SONOS -2 -1 0 1 2 3 4 5 6 7 -2 -1 0 1 2 3 4 5 6 7 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 Initial 1E-6 sec 1E-5 sec 1E-4 sec 1E-3 sec 1E-2 sec

I

DS

(A)

V

_GS

(V)

Erase bias: V GS = -12V, V_S = V_D = 0V CP TFT SONOS

(a)

(b)

Fig. 4. The IDS–VGScurves of CP-TFT SONOS with: (a) programming and (b) erasing

operation at VGS= ±12 V.

Table 1

The endurance characteristics ofX-Gate TFT SONOS with a program bias of 10 V for 1 ms and an erasing bias of 12 V for 1 ms.

P/E cycles (times) 1E0 1E1 1E2 1E3 3E3 5E3 1E4 Program state (V) 3.02 3.09 3.20 3.29 3.34 3.37 3.40 Erase state (V) 0.3 0.42 0.57 0.75 0.97 1.06 1.25

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displays the simulated electrical ﬁeld distribution of both the

X-Gate and CP SONOS across the stacked gate dielectrics at VGS= 12 V. The sharp geometry of these two corners enhanced

the local electric ﬁeld (to be 40 MV/cm) at the channel/tunneling oxide interface, which was about 4.5 times higher for theX-Gate SONOS to the CP device (to be 8.7 MV/cm). The remarkable

electric field promotion at the channel/tunneling oxide interface enhanced the carrier-injection current into the nitride storage layer[12]. Moreover, the much lower electric field at the blocking oxide ofX-Gate SONOS revealed that electron back-injection from gate could be depressed effectively. Since the P/E activity was favorable between the channel and tunneling oxide rather than between the blocking oxide and the gate, the X-Gate SONOS expressed better P/E efficiency which was consistent with exper-imental results. Instead, the electric field (8.7 MV/cm) at tunnel-ing oxide of CP SONOS was always equal to the blocktunnel-ing oxide, leading to lower the efficiency.Fig. 8shows the simulated energy band diagram at VGS= 12 V. The electrons tunneling barrier width

ofX-Gate SONOS was much shorter than CP SONOS. Due to the tunneling probability was increased exponentially with the tun-neling length reduction, theX-Gate SONOS could provide greater memory window shift than that of the CP device.

4. Conclusions

A novel X-Gate TFT SONOS fabricated by a simple sidewall spacer formation has been demonstrated for the ﬁrst time with better transistor performance owing to the enhanced gate control-lability. In addition, theX-Gate TFT SONOS also exhibited superior memory characteristics with a faster Vth shift of 3.02 V and 2.97 V at VGS= ±12 V in 1 ms for programming and erasing operations,

respectively. The dramatic improvement was attributed to the

10-6 10-5 10-4 10-3 10-2 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5

Erase time (sec)

Ω -Gate TFT -12V Ω -Gate TFT -11V Ω -Gate TFT -10V CP TFT -12V CP TFT -11V CP TFT -10V

Vth shift (V)

(a)

(b)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Vth shift (V)

Program time (sec)

Ω-Gate TFT 12V Ω-Gate TFT 11V Ω-Gate TFT 10V CP TFT 12V CP TFT 11V CP TFT 10V 10-6 10-5 10-4 10-3 10-2

Fig. 5. (a) Programming and (b) erasing speed comparison ofX-Gate TFT SONOS and CP-TFT SONOS at VGS= ±10 V ±12 V. 100 101 102 103 104 105 106 107 108 109 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ~1.1V

Vth (V)

Times (sec)

Programed state (cycle=1) Erased state (cycle=1) Programed state (cycles=10K) Erased state (cycles=10K)

Program bias: V G = 12V,1ms Erase bias: V G = -10V,1ms 10 years ~1.2V

Fig. 6. The retention characteristics ofX-Gate TFT SONOS. The memory window of 10 K cycles would be remained 1.1 V after extrapolating to retention time of 10 years. 0 1x107 2x107 3x107 4x107

Electric Field (V/cm)

CP TFT SONOS Ω -Gate TFT SONOS V_G= 12V Tunneling oxide Nitride Storage Blocking oxide Channel Gate 2.5 nm -50 0 50 100 150 200 250 300

Distance form gate (Å)

CP TFT SONOS Ω -Gate TFT SONOS

Fig. 7. The distribution of electrical ﬁeld across the stacked ONO dielectrics for the

X-Gate TFT SONOS and CP-TFT SONOS at VGS= 12 V for programming operation.

Fig. 8. The energy band diagrams ofX-Gate and CP-TFT SONOS at VGS= 12 V for

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effective field enhancement at the two sharp corners and the sup-pressed electric field in the blocking oxide. The device simulation highlighted a larger electric field of external corner region could be obtained by the proposedX-Gate SONOS. Furthermore, theX -Gate TFT SONOS also revealed reasonable endurance and data retention characteristics. Such an X-Gate TFT SONOS memory would be very promising for the embedded NVM on the future SOP applications.

Acknowledgements

The authors would like to thank the National Nano Device Lab-oratories (NDL) and National Science Council, Taiwan, Republic of China for supporting this work under the Contract NSC-98-2218-E-009-004.

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