An All-Digital Phase-Locked Loop
(ADPLL)-Based Clock Recovery Circuit
Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee
Abstract— A new algorithm for all-digital phase-locked loops
(ADPLL) with fast acquisition and large pulling range is pre-sented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked band-width and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock ratefffclock; and 3) the function of nonreturn-to-zero clock recovery has a maximumfffclock/4 recovering capability with a locking range of ( input666 input/2), where input is the input period.
Index Terms— All-digital phase-locked loop (ADPLL), clock
recovery, frequency synthesizer, phase-locked loop.
I. INTRODUCTION
P
HASE-locked loops (PLL’s) have been developed for a long time. The major concept is used as an oscillator to lock or track input signals in both phase and frequency [1]. In communication applications, PLL’s can make local clocks synchronous with other signals. Because digital designs are popular presently, and they fit in baseband designs, digital PLL’s (DPLL’s) are widely used in many modern applications, such as ethernet, asynchronous transfer mode, wireless local-area network, microprocessors, digital signal processing, etc. In digital communications, information is expressed by a series of 1’s and 0’s. To process the received data correctly, it is necessary to synchronize a local clock to received data. However, some design issues must be taken into account when DPLL is to be used as clock recovery, such as phase detection, frequency accumulation, initial constraints, etc. The key characteristics of the clock recovery are 1) pulling range and 2) lock-in time ( ). As a result, the major goal in this paper is to design a digital PLL-based clock recovery with both large pulling range and short lock-in time.For advances and improvements of digital very-large-scale-integration circuits (VLSI’s), all-digital phase-locked loops (ADPLL’s) have good abilities to meet the requirements of computer and communication applications. The portable1
Manuscript received September 28, 1998; revised April 27, 1999. This work was supported by the National Science Council of Taiwan, R.O.C., under Grant NSC88-2215-E-009-068.
The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 300 R.O.C. (e-mail: cylee@cc.nctu.edu.tw).
Publisher Item Identifier S 0018-9200(99)06161-2.
1By portable, we mean that the design can be done by hardware description
language (HDL) and targeted to different CMOS processes through synthesis tools.
design is an important issue in digital VLSI. A problem of portable ADPLL’s is the source of on-chip high-speed clocks. Theoretically, this high-speed clock should be fast enough and act as a reference clock. When ADPLL’s operate in high-data-rate environments, a number of issues must be taken into account, such as power dissipation, logic propagation delay, process variation, and so on. Hence the characteristics of on-chip high-speed clocks must be limited for a target process and flexible enough to meet design requirements. It means that an on-chip high-speed clock must be controllable to operate at a special rate.
Many PLL/DPLL-based designs have been developed. In [2], a nonreturn-to-zero (NRZ) timing recovery with a digital phase detector (PD), analog loop filter (LF), and voltage-controlled oscillator (VCO) are introduced for band-limited applications. In [3] is shown a fully integrated CMOS fre-quency synthesizer with an analog LF and current-controlled ring oscillator. Reference [4] presents several design tech-niques to improve the performance of a PLL with an analog LF and current steering amplifier ring oscillator. They are usually based on conventional design techniques. In [5], an idea of implementing a variable-bandwidth DPLL by finite state machine (FSM) is described and simulated. It can be completed by all-digital implementations; however— fully custom layout still has to be performed.
In this paper, an ADPLL-based clock recovery is introduced here, which has already met requirements of large pulling range, short lock-in time, high data rate, high operating fre-quency, and portable solution. It is different from conventional DPLL’s in tracking and locking mechanism. In implementa-tions, all parts belong to portable cell-based designs and have been verified on silicon using an in-house 0.6- m CMOS single-poly, triple-metal (SPTM) cell library. According to testing results, the proposed clock recovery can operate at a
maximum rate of MHz to recover 4 NRZ
data within one data transition and with a locked bandwidth
of ( 2), where is the input period. An
extra frequency-synthesizer module, cascaded with NRZ clock recovery, can produce expected frequencies whose maximum output frequency is equal to the fastest chip clock. The on-chip clock generator can generate any number of frequencies with a maximum output rate of 165 MHz.
The rest of this paper is organized as follows. The proposed algorithm and architecture of ADPLL is first addressed in Section II. The ADPLL-based clock recovery with an extra frequency-synthesizer module and on-chip clock generator for portable cell-based design is presented in Section III.
(a) (b)
Fig. 1. Basic concept for estimating input’s phases and frequencies within two input edges in two different conditions of period: (a)T (DCO) > N(input) and (b) T (DCO) < N(input).
Implementations and test results of the proposed solutions are then described and discussed in Section IV.
II. THE PROPOSED ADPLL
A. Algorithm Description
The general concept of ADPLL and its two basic structures can be found in [6]. In practical situations, input information is very important for tracking or recovering desired signals correctly. To extract accurately and track immediately input information, it is necessary to estimate both phases and fre-quencies of input signals continuously. As a result, the object of the proposed ADPLL algorithm is to achieve fast acquisition and large pulling range.
It is assumed that a high-speed clock is used as reference timing, and all signals must be referred to this clock. The periods of a digital-controlled oscillator (DCO) and input signal are equal to and , where and are constant and is the period of high-speed clock (reference). After normalization with , the new (normalized) periods of DCO and input are and , respectively. The proposed algorithm is illustrated in Fig. 1(a) and (b) for two conditions. Fig. 1(a) shows the case of the DCO’s frequency (1/period) which is slower than input signals, i.e., (DCO) (input). Fig. 1(b) shows the other case of the DCO’s frequency, which is faster than the input signal, i.e., (DCO) (input). Note that all values are referred (normalized) to a high-speed clock , and all processes are under normalized conditions. The major problem is how to adjust DCO accurately to follow the input signal based on received data information.
Assume that and stand for normalized periods of the DCO and input signal, respectively. It is shown that is equal to for estimating correct input information in Fig. 1(a), where (“M times” period of high-speed clock) is the normalized phase error between the DCO and input. At (time), the system starts to synchronize phases for the first valid edge of the input and DCO output. During (time) to , a phase error is detected. Then the correct phase
for the second edge of DCO is equal to the phase error, and the correct period is determined by comparing and . In Fig. 1(b), tracking procedures for are similar to the above case, but the correct phase of DCO is “0,” not “ .” If there is a special case of , a phase error will exceed , and the phase of DCO becomes undecidable. To solve this problem, the system must resynchronize again with the previous estimation ( ). Thus, the correct phase and period are estimated for setting DCO to reach minimum errors. Mathematically, a correct phase for the second edge of DCO corresponding to input is , and the (normalized) period is
equal to for . Hence at time , input
and DCO output are completely synchronous in both phases and frequencies. For the case of , it is the same as the above discussions for , and the phase of DCO equals zero. A new period is calculated by both phase error and previous result . Therefore, the lock-in time includes two conditions—DCO output, which is slower than input, and DCO output, which is faster than input. For the first case, we need one DCO normalized period to determine the correct phase and frequency. Thus, the lock-in time of the ADPLL is equal to ; however, two clocks have the same phase at , as shown in Fig. 1(a). For the case of , the correct tracking period is equal to and can be completed by one input normalized period . Thus, the lock-in time is equal to , and the two clocks have the same phase at , as shown in Fig. 1(b). Hence the lock-in time , which is defined by the time needed to determine both correct phase and frequency, can be written as follows:
(1) It is important to select suitable parameters for DCO’s to reduce the lock-in time. A flowchart is shown in Fig. 2. Note that the proposed algorithm does not need to set accurate time, and the dynamic range of ADPLL is not limited by initialization. This is because both input phase and frequency are already available in ADPLL. In other words, characteristics of the proposed algorithm are irrelevant to input signal.
Fig. 2. Flowchart of the proposed ADPLL algorithm.
B. The Proposed Architecture
A block diagram of the proposed ADPLL is shown in Fig. 3. There are six major functional blocks, namely:
1) differentiator with first edge detection (DFED), whose function is to generate differential pulses [6] for in-creasing resolutions and detect the first edge from input signals to meet synchronous conditions, as indicated in Fig. 1;
2) phase detector (PD), which is a JK flip-flop [6] to indicate phase differences between differential pulses and DCO output;
3) filter counter, which is used to determine the phase errors of two signals by referring to a high-speed clock; 4) phase and frequency estimator, which is used to measure
new phases and frequencies based on original informa-tion and new phase errors;
5) programmable DCO, which is used for generating a target signal;
6) high-speed clock generator, which is used as an on-chip reference timing for controlling and synchronizing all modules to avoid timing errors.
To fit the above requirements, a programmable DCO with adjustable phase and frequency is required to operate in jumping conditions. In other words, it must be able to change instantaneous phase and operating frequency at any controlled cycle to minimize both phase and frequency errors. Based on this DCO, the proposed ADPLL can dynamically determine instantaneous phase and frequency to correctly track input signals in minimal time. For practical situations, dynamic control is necessary to compensate for noise effects and
process variations to make ADPLL more accurate in tracking. The operation for this architecture is explained as follows.
After initial settings are loaded, the first input valid edge must be detected by DFED to fit a synchronous condition, as shown in Fig. 1. By using the first valid edge to trigger all modules for extracting input information, the phase errors are estimated by filter counter to calculate the difference between the second valid edge of the input and DCO output. This phase error ( ) is used to determine a target period and phase for the DCO. If the phase error is greater than 2 (or in Fig. 1), the DCO must be stopped to make correct relations of phases until the next input edge. Last, both correct phase and period (frequency) are determined and fed into the DCO to generate synchronous signals for the next cycle. These procedures run once per valid input transition to ensure ADPLL with minimum phase and period errors. In a noisy environment, both phase and period of input signals change randomly, and all noisy phenomena can be classified into two cases. One is input phase lagging DCO output and the other is input phase leading DCO output. In both cases, the proposed ADPLL estimates new phase and period to minimize errors during tracking input signals. Although the ADPLL becomes stable with any initial setting or any condition, the lock-in time is always proportional to initial settings, as given in (1). The operating speed of this architecture is limited by the critical path from filter counter to phase and frequency estimator, as shown in Fig. 3. Note that both phase and period estimations need one high-speed clock. In addition, input tracking needs at least one high-speed clock. Hence the maximum tracking frequency is equal to (without differentiator).
III. CLOCK RECOVERY A. Kernel of the Clock Recovery
1) Algorithm: The purpose of clock recovery is to search
a correct timing for input signals, such as NRZ, RZ, and so on, because these signals do not include timing information in their bitstream. Theoretically, a series of 1’s and 0’s of NRZ or RZ always have some uncertain problems of received phases and frequencies. To overcome these problems, DCO’s are limited to certain finite dynamic ranges in phase and frequency jumping for clock recovery. To recover a NRZ signal, a differentiation process is often requested to improve resolution. Based on the proposed ADPLL algorithm, constraints for phase and frequency are added into systems to avoid uncertain problems and discussed below.
To transmit more than two 1’s (or 0’s), the maximum phase error of these 1’s is at least 2 (input period). The detection becomes failed in DCO without constrained dynamic ranges of phases and frequencies. Then the frequency of DCO cannot be adjusted over one input period because a minimum number of continuous 1’s (or 0’s) is two. The limitations of pulling up for calculating new frequencies are similar to the case of pulling down. Hence for equal probability of phase errors in both pulling-up and pulling-down cases, the maximum adjusted region is (input_period)/2. According to the above controlled constraints, the dynamic-control range of DCO’s is
Fig. 3. Block diagram of the cell-based ADPLL architecture.
equal to or , where
is the input period, and . Both stability and bandwidth must be taken into account and traded off in designs. Two detection constraints of phase errors are included in the phase and frequency estimator to ensure systems operate correctly even having errors caused by phase uncertainty of NRZ signals. Both phases and frequencies of DCO’s can be accurately judged to prevent failures of locks during series of 1’s or 0’s. This algorithm can be restored only after one data transition.
For conventional designs, it is difficult to combine both clock recovery and a frequency synthesizer into a single sys-tem. In some applications, if a system includes several modules to process received information in parallel and the final data must be combined, multiple clocks synchronous to the recov-ered data clock are often needed to control data paths (such as code-phase multiplexed algorithms for direct-sequence spread spectrum [7]). Since the input period (frequency) can be extracted by a phase and frequency estimator, it is possible to directly make use of the information to generate any number of frequencies. To eliminate the instability of a feedback loop in a conventional frequency synthesizer, an extra module cascaded with clock recovery, namely, a multiple-frequency generator, is introduced to realize the above concept. A flowchart of the NRZ clock recovery with a frequency synthesizer is shown in Fig. 4. By using such an extra module, it is able to generate any number of frequencies without having influence from the divided-feedback loop. For taking the finite-precision issue into account
the function of the extra module is modified to minimize processing errors by
(2)
where is a constant (if we want to approach ).
Fig. 4. Flowchart of the NRZ clock recovery algorithm with a function of the synthesizer, where the dotted line indicates extra blocks for the frequency synthesizer.
2) Architecture: A block diagram of the proposed clock
recovery is shown in Fig. 5(a). In practical situations, it is essential to adjust the output of clock recovery with a fixed or programmable phase delay to correctly guarantee output timing [6]. Hence the output of clock recovery is set to delay
(a)
(b)
(c)
Fig. 5. Application example of NRZ clock recovery: (a) block diagram of NRZ clock recovery with a function of the synthesizer, (b) structure of phase and frequency estimator, and (c) structure of multiple-frequency generator.
phases, corresponding to numbers of the high-speed clock. In other words, the output can also be corrected within input-phase errors (jitter).
In Fig. 5(a), seven major functional blocks form the com-plete clock recovery. They are DFED, PD, up/down filter counter, phase and frequency estimator, high-speed clock, and
programmable DCO. Due to the limitations of unpredictable phases, it cannot use conventional three-state PD’s [1] to detect input phases. Compared to Figs. 3 and 5(a), the main differ-ences are the structure of the phase and frequency estimator and filter counters. Up and down channels are separate to measure different phase errors and uncertainty problems. The
Fig. 6. Searching flow of the proposed clock generator.
most important and complex module of clock recovery is the phase and frequency estimator used to determine lock-in time, dynamic ranges, stability of phase uncertainties, jitters, etc. The structure of the phase and frequency estimator is shown in Fig. 5(b). In estimating new phase and period (frequency), the function of clock recovery is similar to ADPLL. Both phase error and frequency estimations are limited to {maximum }. With this assignment, it can prevent an overlock event during any number of series of 1’s or 0’s within received data streams in a noisy environment. All tracking procedures are recycled to make information correct during each valid transition. Because the bandwidth of DCO’s is limited within a certain range proportional to input signals, the initialization must be considered carefully to prevent recovering process failure. Generally, the data rate of input signals is known, so it is not difficult to meet these constraints, as discussed in Section III-A1. In implementations, two high-speed clocks are requested to estimate correct phases and periods, and at least two high-speed clocks must be allocated for phase jitter. So, the overall operating frequency is equal to the maximum 4. In Fig. 5(c), the structure of the multiple-frequency generator is mainly based on a digital constant divider and adder to calculate the appropriate period (frequency). After the correct information of received signals is estimated by clock recovery, the period (frequency) information is extracted into the multiple-frequency generator for achieving functions of frequency synthesizers. By this scheme, the output of a normal DCO and synthesizer are separated, and both the clock recovery and frequency synthesizer can connect together. Compared to conventional designs, the major difference is the multiple-frequency generator used to approach an expected period ( -time frequency) for the second DCO. Both normal and -frequency (multiple frequency) DCO’s are independent, but are synchronous to each other. The normal DCO is used to lock received signals, and a multiple-frequency (second) DCO is applied to approach -time frequency.
Fig. 7. Block diagram of cell-based clock generator.
B. Clock Generator Submodule
The above approach essentially needs a high-speed clock as a reference for tracking. To provide a full cell-based integration solution, it is necessary to generate this high-speed clock on chip.
1) Algorithm: An algorithm for digital cell-based
oscilla-tors is presented below to meet our requirements for full inte-gration. Two major functional blocks are identified, namely, a frequency controller and ring-oscillator pair. Their functions are to search and control the output clock to meet design specifications and then to generate target clocks.
A default clock generated by a ring-oscillator pair is com-pared to an input reference for checking whether its frequency error is within a locked window. The compared result is then fed into a frequency controller to determine new controlled status or frequency-search commands for a ring-oscillator pair to update the output clock. These procedures are repeated until a target clock can synchronize to an input reference. To ensure that these search procedures are accurate and efficient, the frequency-search algorithm includes two stages: a coarse search based on a “prune-and-search” algorithm [8] and a fine search based on a “fix-step” algorithm. Two cost functions for search and lock-in processes are derived to determine
Fig. 8. Structure of frequency-tracking module in on-chip clock generator.
Fig. 9. Structure of cell-based digital-controlled oscillator.
which scheme should be applied to search a target frequency and locked status. If frequency errors are higher than both search and locked thresholds, a coarse search is activated to estimate a nearby frequency. On the other hand, a fine search is only activated when frequency error is between the search and locked thresholds. By properly assigning these two thresholds, the search performance and output resolution can be improved, such as the search time and frequency error. The search flow is shown in Fig. 6. It is assumed that a default frequency is set to {(min frequency max frequency 2)}, denoted by Mid. If a target frequency is higher than Mid and its frequency error is greater than the threshold or out of a cost window, the default frequency must move from Mid to a new frequency {Mid (max frequency min frequency) 2} based on a prune-and-search scheme. If its frequency error is smaller than the threshold or within the cost window, the search algorithm is switched to the “fix-step” fine-tune stage. Because the threshold is fixed, the worst case time complexity of fine search is a constant. Hence the worst case
time complexity [8] is given below
(3) where
Note that is a constant, is the complexity
of the last step, and is the complexity of the prune-and-search algorithm. The overall time complexity for the condition of a target frequency slower than Mid is also equal to (3). In this way, the search process can be implemented simply by a digital design technique.
to generate controlled timing for searching frequency. Since propagated delays have to be taken into account, overall operations are divided into two types: 1) an active region for searching a target frequency and 2) a preset region for restoring commands. Due to the physical constraints of digital VLSI, such as setup time and hold time, the decisions of frequency search must be determined carefully. Hence, in order to pre-vent timing violation, a divider is applied to extend decision regions. In this way, the cost or threshold can be determined without a timing violation. To compensate for temperature and supply-voltage variations, the search procedure must be a recycled action (continuous), even if a target clock is found. The locked and tracking commands in Fig. 7 include both coarse-search and fine-search commands. The structure of frequency tracking is shown in Fig. 8. A cell-based digital-controlled oscillator is shown in Fig. 9. It is a kind of ring oscillator with stages, whose characteristics are determined by a inverter. A free-running frequency is determined by the number of inverters. Note that the dynamic controlled range is determined by the number of path selectors, and frequency resolution is dependent on scales of a delay matrix. Both a path selector and a delay matrix are used to perform coarse and fine searches, and the resolution of ring oscillators is decided by the minimum scale of a delay matrix. It is important for systems not only to maintain a stable clock but also to ensure minimum frequency error. Hence two equivalent cell-based DCO’s are allocated within a clock pair: one for frequency searches and the other for a target clock.
To ensure that the proposed architecture can generate any target frequency, both temperature and voltage variations have to be taken into account. From [9], it is shown that the output frequency of inverter chains is dependent on and of inverters (inverter delays). However, inverter delays are functions of temperature, supply voltage, loading capacitance, etc. For simplification without losing generality,
it is assumed that and for
. In practical applications, the output frequency can be allowed a certain frequency error, denoted by .
That is, , where % is a percentage
of frequency error, and %. Hence, when
the output frequency is equal to (or less than) , the size of a locked window must be smaller than frequency error to meet output specifications. Based on Fig. 9, the output
Fig. 10. Relationship among jitter, target frequency, and possible sites of a locked window.
TABLE I
GATECOUNT OFEACHSYNTHESIZEDMODULE INCLOCKRECOVERY
frequency of cell-based digital-controlled oscillators is (4) where
(5) and is a constant for a free-running frequency, is the total number of inverters
is the model of the delay matrix, and it represents the delay of the th path in total delay paths. In other words, the delay matrix owns paths to pass signals with different delays, and relative delays of each path are almost linear. Note that (5) must satisfy an inequality of frequency errors as indicated below
(6) In (6), for any given and , we can find a to satisfy the above constraints. The larger a dynamic range of is, the wider an output bandwidth is. For increasing in designs, resolutions of cell-based digital-controlled oscillators can be improved. To satisfy (6), both and are controlled by a frequency-tracking module to search a proper combination based on prune-and-search and fix-step algorithms.
TABLE II
FEATURES OFEACHMODULEUSED IN CLOCKRECOVERY
Fig. 11. Measured result of clock recovery at 125-MHz high-speed clock/(12.5- and 9-Mbps) NRZ input.
From the above description, it is shown that effects of temperature and supply voltage can be eliminated by proper selection of and . Practically, a reference clock is not ideal (it includes some frequency jitter) and influences target frequency. According to the above description, the frequency-tracking module uses a locked window to make a decision. Although the site of a locked window is also influenced by jitter, the locked status of a certain target frequency is not out of locked regions (if a locked window is large enough). Generally, the size of the locked window is at least double input jitter. As a result, influences of jitter can be decreased because the target frequency is located at the window’s center, as shown in Fig. 10.
IV. IMPLEMENTATION AND DISCUSSION
The clock recovery with a function of frequency synthesizer and an on-chip clock generator are fabricated in a 0.6- m CMOS SPTM process. First, the whole design (including all functional modules) is described by Verilog-HDL with timing information from an in-house target standard-cell library. Then Verilog source codes are synthesized to generate gate-level netlists and schematics for further simulations and verifica-tions. The synthesis result of each module is shown in Table I. These gate-level netlists are verified with original codes to check their behaviors and timing. In addition, the cost and timing of whole systems must be carefully considered to meet requirements in this step. After timing and functions have been verified correctly, we use CADENCE/OPUS to do physical
designs. To minimize mismatch of the clock pair in an on-chip clock generator, two DCO’s are arranged symmetrically during floorplan and layout, i.e., one DCO is performed first, then the second DCO is duplicated. Last, two DCO’s are placed together to complete the clock pair.
In digital designs, all logic streams are controlled by the phase of a reference clock. Ideally, each logic gate receives an identical phase of reference clock. However, both clock skew and signal racing significantly degrade overall performance. As a result, we use clock tree distribution to manage system clocks. The overall features of each module are given in Table II. Testing results show that the function of clock recov-ery can recover 4 NRZ data at a maximum
MHz within one-data-transition acquisition with (
2) pulling range. Fig. 11 shows the measured result of clock recovery at 125-MHz high-speed clock/12.5- and 9-Mbps NRZ input. The histogram of an on-chip clock generator at 166 MHz/3.3 V is shown in Fig. 12 with rms : 11.42 ps/ : 74 ps (reference: 40 MHz 116 ps/output: 119 MHz with rms : 12.73 ps/ : 88 ps). The relation between the reference and target clock is shown in Fig. 13, with reference at 33 MHz 108 ps and output at 166 MHz 37 ps . Mismatched problem within a clock pair is less than 0.069 ns or 0.83%. Comparison data with conventional frequency synthesizers in items of acquisition time, jitter, operation frequency, power consumption, pulling, and locking range are shown in Table III. A chip microphoto of the clock recovery with the function of frequency synthesizer and on-chip clock generator is shown in Fig. 14.
Fig. 12. Histogram of the on-chip clock generator at 166 MHz/3.3 V.
(a)
(b)
Fig. 13. Test results of the on-chip clock generator clock for L = 1,
M = 40, and N = 8 with (a) reference clock at 33 MHz 6 108 ps and
(b) output at 166 MHz6 37 ps (mismatch < 0.069 ns).
V. CONCLUSION
To exploit advances of digital VLSI, a new algorithm with fast acquisition and large pulling range has been presented in this paper. Based on an in-house 0.6- m CMOS SPTM standard cell library, several test keys have been designed, fabricated, and tested. Results show that these cell-based
solu-Fig. 14. Microphoto of the clock recovery and the on-chip clock generator.
tions can meet many requirements in data communications. In addition, the design cycle can be greatly reduced. Also, system turnaround can be reduced during technology migration. As a result, the proposed portable and cell-based fully CMOS integrated solutions become available for communications.
ACKNOWLEDGMENT
The authors would like to thank the members of the SI2 Lab of the Department of Electronics Engineering, National Chiao Tung University, for many fruitful suggestions on physical implementations. They would also like to thank the Multiple-Project Chip support from NSC/CIC.
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Terng-Yin Hsu received the B.S. and M.S. de-grees from Feng Chia University, Taichung, Taiwan, R.O.C., in 1993 and 1995, respectively, both in electrical engineering. He is currently pursuing the Ph.D. degree at the Institute of Electronics Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
His research interests include VLSI architectures, CDMA power control, wireless LAN communica-tions, high-speed networking, system-on-chip de-sign technology, and related ASIC dede-signs.
Bai-Jue Shieh was born in Taipei City, Taiwan, R.O.C., on August 9, 1974. He received the B.S. degree from the Department of Electronics Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1996. He currently is pursuing the M.S. degree at the Institute of Electronics Engi-neering, National Chiao Tung University.
His specialties include IC design flow, cell-based and fully custom VLSI design, video signal process-ing, cell library design, and memory circuit design.
Chen-Yi Lee received the B.S. degree from Na-tional Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1982 and the M.S. and Ph.D. degrees from the Katholieke University Leuven, Belgium, in 1986 and 1990, respectively, all in electronic engineering.
From 1986 to 1990, he was with IMEC/VSDM working in the area of architecture synthesis for DSP. In 1991, he joined the Faculty of the Electron-ics Engineering Department, National Chiao Tung University, where he is currently a Professor. His research interests mainly include VLSI algorithms and architectures for high-speed networking, system-on-chip design technology, very-low-bit-rate coding, and multimedia signal processing.
