A New Approach for Characterizing
Structure-Dependent Hot-Carrier Effects
in Drain-Engineered MOSFET’s
Steve S. Chung,
Senior Member, IEEE, and Jiuun-Jer Yang
Abstract— In this paper, we have demonstrated successfully
a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based
on an understanding of the interface state(Nit) distribution, instead
of substrate current or impact ionization rate, for evaluating the
hot-carrier reliability of drain-engineered devices. The position of the peakNitdistribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the charac-terizedNit spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.
I. INTRODUCTION
T
HE spacer-induced degradation resulting from hot-carrier injection is believed to be intrinsic to the conventional LDD structure with n -to-gate offset [1], [2]. In recent years, several improved drain-engineered MOSFET’s, such as MLDD [3], ITLDD [4], GOLD [5], and LATID [6], have received much attention because of their abilities to enhance current drivability and alleviate spacer-induced degradation [2]. However, there is no unified solution for analyzing the hot-carrier reliability in various drain-engineered devices.In the past, normally we use drain current degradation , threshold voltage shift voltage shift , transconductance degradation , or substrate current for comparing the hot-carrier reliability of MOS devices [7]. However, to compare the hot-carrier effect in drain-engineered MOSFET’s, the commonly used substrate current or total amount of generated interface states is not a sufficient Manuscript received December 3, 1998. This work was supported by the National Science Council, Taiwan, R.O.C., under Contract NSC82-0404-E009-377. The review of this paper was arranged by Editor M. Fukuma.
S. S. Chung is with the Department of Electronic Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
J.-J. Yang was with the Department of Electronic Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. He. is now with WSMC, Hsinchu 300, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9383(99)05067-4.
TABLE I
MAJORDEVICEPARAMETERS FORDEVICESUSED INTHISSTUDY
criterion. On the other hand, since interface state generation is the dominant mechanism responsible for the variation of the above characteristics, determination of the interface states, in particular its spatial distributions, becomes critical to a device engineering work. For example, the drain current degradations are closely related to the distribution of hot-carrier induced interface states and device parameters such as n doping profile and gate oxide thickness [1], [8]. Therefore, to get insight into the degradation process of drain-engineered device in more detail, it is essential to first physically characterize the interface state profile.
To deal with the aforementioned problems, in this paper, we will propose an efficient profiling technique to characterize the lateral distribution of and to show its applications for a drain engineering work. Section II describes the device parameters and hot-carrier stress conditions used in this study. Section III presents an improved charge pumping profiling technique and the characterization results of distributions. Section IV demonstrates an application of this new method to study the structure-dependent hot-carrier degradation in vari-ous drain-engineered MOSFET’s. A summary and conclusion are given in Section V.
II. DEVICEPREPARATION AND EXPERIMENTALCONDITIONS Various submicron n-channel LDD devices with different drain-engineering were fabricated using standard polysilicon gate CMOS process. Table I lists the device process condi-tions. Threshold voltage adjustment was performed by 70 KeV
BF ions at a dose of cm . For 45 LATID
device, the phosphorus implanted n region was performed by a 45 tilt angle implantation from the source and drain 0018–9383/99$10.00 1999 IEEE
1372 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 7, JULY 1999
(a)
(b)
Fig. 1. (a) Experimental setup and principles of the interface state profiling technique. (b) Time evolution of measured ICP-Vgh relationship during hot-carrier stress using fixed based level CP measurement.
sides by rotating the wafer automatically. Sidewall spacer were processed by CVD SiO deposition followed by reactive ion etching, the resultant width is 0.15 m for all device. N source and drain were formed by 80 KeV arsenic implantation at a dose of cm . The masked gate width of all devices are 20 m. Several important device parameters such as drawn channel length , extracted geometrical effective channel length , threshold voltage , and current drivability (evaluated at V) are also listed in Table I. All devices were stressed at
V and V for hot-carrier reliability evaluation. III. THEINTERFACE STATE PROFILINGTECHNIQUE A. Experimental Setup of CP Measurement
The experimental setup for CP measurement is shown in Fig. 1. The source, drain and bulk electrodes of tested device were grounded. A 1 MHz square pulse waveform provided by HP8110A with fixed base level and varying high level was applied to the gate. We keep at 6 V and increase from 6 V to 6 V with 0.1
V step. The voltage step will affect the profiling resolution. Parameter analyzer HP4145B was used to measure the charge pumping current .
B. Derivation of from - Relationship The local threshold voltage and local flatband voltage
along the surface of a device is not laterally uniform due to the variation of doping profile. As illustrated in Fig. 1(a), for a certain value, only interface states in the region can be detected and contribute to , where is the difference
between and and are the
positions where local equals and local equals , respectively. V is believed to be much lower than local at the most right end of damaged region along the SiO /Si interface. The measured versus characteristics for fresh and stressed devices are shown in Fig. 1(b). increases with stress time, which means that is generated continuously.
In a fixed base level CP measurement [9], the ( (stressed)- (fresh)) as a function of the can be analytically expressed as
(1a)
(1b) in which, (in unit cm V ) is the density of hot-carrier induced interface states at a position where the local threshold voltage is is the gate pulses frequency, is the channel width and . Taking the first derivative
of with respect to gives
(2) Since increasing widens the detectable damaged region toward the channel direction, indeed, the versus detected length relationship implies the spectroscopy of local threshold voltage. In other words, ( is position coordinate, the origin is set at the point where ) relationship is identical to that of . By changing the integral variable from voltage to position, (1b) becomes
(3) in which is the position where equals . Let
(4) (3) can be rewritten as
(5) where (in unit cm ) is the lateral distribution of generated . Substituting (2) into (4), is rearranged as
(6a) (6b)
Fig. 2. Simulated local threshold voltage(Vth) and local flat-band voltage (Vfb) of LDD device.
Assuming no fixed oxide charges are generated during stress at bias, local threshold voltage will not be altered. By calculating local threshold voltage from two-dimensional
(2-D) device simulation and from measured
- curves, (6b) provides us a simple and accurate way to a simple and accurate way to characterize directly from CP measurement.
C. Simulation of the Local Threshold Voltage
For an n-MOSFET in CP measurement, the local threshold voltage (or flat-band voltage) of a point at the interface is defined as the gate voltage at which the free electron (or hole) concentration ( for electron, for hole) at the surface is sufficiently large so that the fast interface states can capture electrons (or holes) during the time the gate pulse is applied [10]. The minimum required surface concentration for electrons (holes) with time constant and capture cross section is given by
(7) For a 1 MHz symmetrical square gate pulse, we have
s. With
cm and cm/s, cm . Thus,
for the given gate pulse train, the local threshold (flat-band) voltage of a point at interface is defined as the gate voltage that accumulates cm electrons (holes) at the surface. The simulated shapes of and relationship using Minimos 4.2 [11] are shown in Fig. 2.
D. Characterization Results and Discussion Based on (6b), Figs. 1(b) and 2, the calculated
distributions for the LDD device are given in Fig. 3. Minimos 4.2 was used to simulate the lateral surface electric field and normalized hot-carrier injection current density are also shown together for examining the appropriateness of the profile. The hot-carrier injection current density at each position,
, is calculated as
(8)
Fig. 3. Time evolution of characterized interface state profiles during hot-carrier stress for LDD device. The distributions of surface electric field and normalized hot-carrier injection current are also shown for comparison.
Fig. 4. The comparison of the drain current characteristics between simula-tion and measurement for both fresh and stressed devices.
where and are lateral components of local surface current density and electric field, respectively, eV,
˚
A and coulomb. is normalized
to its maximum value. As illustrated in Fig. 1(a), we divide the hot-carrier damaged area into three regions: Region I is the channel region, Region II is the gate-to-n overlapped region, and Region III is the sidewall spacer region. The discussion of the above results follows.
1) To show the validity of the characterized results in Fig. 3, the distributions of was incorporated into Minimos 4.2 [11] to simulate the drain current characteristics of stressed devices. First, by following
1374 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 7, JULY 1999
Fig. 5. Simulated local threshold voltage of LDD device without considering Nit effect (solid lines) and with consideringNiteffect (dashed lines). The insert using GIDL current measurement is used to show no fixed oxide charges were generated during the stress.
the procedure described in [11] that process flow was set up and the channel profile, source/drain doping profile, and key mobility factors have been calibrated. The solid lines and dotted circles in Fig. 4 are the measured and simulated drain current characteristics respectively for devices before the stress (fresh). Results show pretty good agreements. This is to ensure the accuracy of the results in this work. Then, to simulate the device drain current by including the effect, an empirical mobility degradation formula [12] including Coulomb scattering and surface roughness enhanced scattering was incorporated for the 2-D device simulation. The dashed lines and solid rectangles in Fig. 4 shows the measured and simulated drain current characteristics after the stress at 10 s which shows very good match with measurement.
2) The electric field and hot-carrier injection current were simulated using DD (Drift-Diffusion) models. The peak position of after 11 000 s stress is separated from that of and by 150 ˚A. Advanced device simulation [13] proved that this discrepancy is very rea-sonable due to nonlocal effect in submicron MOSFET’s, because carriers need to travel sufficient distance to become energetic.
3) The peak values of generated interface states in LDD device are mostly located in Region III. The negatively charged interface states here are prone to reduce con-ducting carriers that increases series resistance, thus is degraded. The characterized interface state profile gives direct evidence for the degradation mechanism of spacer-induced degradation in LDD devices.
4) For the characterization in Fig. 3, it was assumed that no fixed oxide charge was generated which will make the method more simple. To show that the fixed oxide charge was not generated, we took a measurement of Gate Induced Drain Leakage (GIDL) current as shown in the insert of Fig. 5 ([14]) where we see that no oxide charge was generated in our device stress conditions. This can avoid the complicate determination of fixed oxide charge. On the other hand, the effect of
Fig. 6. The calculated interface state distributions of LDD device without consideringNiteffect (solid lines) and with consideringNiteffect (dashed lines).
on the calculated is shown in Fig. 5 (in dashed lines). Again, if these values of are used for calculation (6b), the distribution is given in Fig. 6. The solid lines are the results without considering effect, while the dashed lines are the results considering
effect. Here, we see that although there are much more difference for low values of , there is not much difference at the near peak region. More importantly, the device degradation characteristics are determined mainly by the peak values and the position of as will be described in the next section. In such a case, it is reasonable to calculate term in (6b) using
curves (Fig. 2) of fresh devices.
IV. APPLICATIONS TODRAIN-ENGINEERINGSTUDY In the past, substrate current [7] or impact ionization rate is generally used as a monitor to evaluate MOS device hot-carrier reliability. But, in some cases, a device with larger substrate current may not have poorer drain current degradation. We will show in this section how to evaluate the drain current degradation correctly using the interface state profiling results. The application of the present method to the hot-carrier effect evaluation of MLDD, 45 LATID and LDD devices will be demonstrated. These include the substrate current , effective impact ionization rate , the spacer-induced degradation, and the drain current degradation of these devices. A. The Comparison of Hot-Carrier Related
Static Characteristics
Fig. 7 compares the and characteristics for three devices. MLDD device has the maximum and values. LDD device has minimum values over the whole
range, while its at low is larger than 45 LATID due too its lower current drivability. Also, by compar-ing Figs. 7 and 8, we see that is proportional to . If we use as a monitor of the generated interface states, the induced total amount of is proportional to the value at stressed biases. Under this argument, the MLDD device is expected to suffer the most severe drgradation, 45 LATID device is medium, and LDD device is the minimum. However,
Fig. 7. Comparison ofIB andIB=ID characteristics for the MLDD, 45 LATID and LDD devices.
Fig. 8. Time evolution of1ID=IDand1ICPduring hot-carrier stress for the devices MLDD1, LATID45 and LDD.
the results are just the opposite. From the comparison shown in Fig. 8, the drain current degradation for three devices, we see that LDD device suffers the most severe degradation than the others at the same stress time, 45 LATID has the minimum degradation. Obviously, the above indicator using (Fig. 7) can not explain the results shown in Fig. 8. B. Structure-Dependent Hot-Carrier Effect
In order to solve the discrepency between Figs. 7 and 8, our results of distributions in Fig. 9 can be used to explain the drain current degradation correctly. As a consequence, we can draw a criterion by using profiles as a good monitor of device hot-carrier reliability. Fig. 9 compares the profile for the MLDD, 45 LATID and LDD devices after 11 000 s stress. Channel electric field is also plotted together for comparing its correlation with profile. More details are described as follows.
1) The peaks of interface state profiles are all located out-side gate edge, therefore, all three devices suffer spacer-induced degradation. The spacer-spacer-induced degradation [2] is driven by the increase of drain region series resistance. Fig. 10 shows that the trend of variation of the series resistance increment (extracted using a method in [15]) is the same as that of . LDD device suffers the
Fig. 9. Comparison of interface state profile for MLDD, 45 LATID and LDD devices after 11 000 s stress. The surface electric field profiles are also shown for examining their relations with interface state profiles. Positions A, B, and C are the drain/bulk junctions for MLDD, 45LATID and LDD devices, respectively.
Fig. 10. Linear region drain current degradation and series resistance incre-ment versus the amount of generated interface states.1ID=IDis evaluated atVDS = 0:1 V and VGS = 5 V.
most severe spacer-induced degradation since it has the largest peak values underneath the spacer. While, in MLDD, spacer-induced degradation is smaller and is less significant in 45 LATID device. This reveals that the spacer-induced degradation dominates the drain current degradations for LDD devices with spacer structure. 2) From the calculated total amount of interface states
in each damaged region, we found that the dominant damaged region for MLDD device is Region II, for 45 LATID device is Region II, and for LDD device
1376 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 7, JULY 1999
(a)
(b)
(c)
Fig. 11. Reduction of surface electron concentration after 11 000 s stress for the devices (a) LDD, (b) LATID45, and (c) MLDD.
is Region III. Fig. 11 shows the simulated variation of device surface electron concentration before stress and after stress 11 000 s for LDD and LATID45 respectively. For LDD, it has the largest peak and the position of peak is located far from gate edge as compared with the others such that the reduction of electron concentration [Fig. 11(a)] is very significant owing to its lighter n region doping concentration, which increase the series resistance in the spacer region. It is this serious series resistance effect that causes LDD having the largest degradation.
3) In contrast to LDD device, MLDD device has a lit-tle higher n concentration than that of LDD device such that the resistance effect is weaker as shown in Fig. 11. By examining profils of MLDD and LDD, increasing n dosage can move the dominant damaged region toward channel direction as illustrated in Fig. 12, which increases gate controllability over damaged region. This fact helps alleviating the series resistance effect in MLDD.
4) The n tilt angle implantation makes the LATID45 having the peak values inside the gate edge. The electric field is distributed widely with smallest peak value among all three devices. In addition, LATID45 has smaller reduction of electron concentration in the
(a)
(b)
Fig. 12. Schematic diagrams for (a) the conventional LDD devce and (b) the MLDD device. The bell-shape regions indicate the location of maximum hot-carrier injection regions. The n0dosage of the MLDD device is larger than that of conventional LDD device.
gate/n overlapped region as given in Fig. 11(b) and hence much less resistance increment effect in Fig. 10. These show that LATID45 has the smallest degra-dation and why LATID45 device can alleviate the hot-carrier effect.
C. Discussion
The present method is superior to those in [16]–[18]. First, in [16] and [18], the depletion width is calculated by analytical formula [16] (based on the depletion approximation formula between and depletion layer width) or determined exper-imentally [18] which may limit profiling accuracy. Secondly, the measurement causes unintentional re-stress effect repeat-edly in [16], [17] since a large drain bias is applied during the experiments. Thirdly, the method in [18] can not be applied to LDD device structures since it used the gate length as a reference point where is determined inside the gate length (Figs. 6 and 8 in [18]). For the devices being studied, the re-gion under the spacer rere-gion will also contribute to the charge pumping current such that most of the distribution will cover both the gate-drain overlap region and the spacer region. The present method can achieve this purpose based on the -plot and the simulated curves. While, the method in [18] based on the experimentally determined profile is not adequate for application in LDD device structures. Finally, both papers only dealt with the spatial distribution of , no criterion was provided to correlate the device degradation with
distributions for a device drain engineering study. In short, the conventional criterion using for monitoring the device reliability is not a sufficient criterion for device drain engineering study. The degradation of a drain-engineered MOSFET should be compared based on the extent of the peak position of and its peak values. In other words, the more the interface statesare generated inside the spacer region, the larger the drain current degradation becomes. With a tradeoff between the use of n implantation dosage and angle, the design optimization of a hot-carrier
resistant MOS device can be better understood through the use of the newly proposed method.
V. CONCLUSION
In this paper, an efficient interface state profiling tech-nique is proposed to study the hot-carrier reliability of drain-engineered submiron LDD n-MOSFET’s. Interface state pro-filing was first developed based on the charge pumping mea-surement technique. The developed profiling technique is then applied to study the structure-dependent hot-carrier effects in various drain structure LDD devices. In particular, a new criterion based on the observation of the distribution is a good and correct monitor for hot-carrier reliability evaluation. We should keep the peak values of far away from the spacer region in order to obtain better device reliability. For LDD structure devices in our studies, spacer-induced degradation is inevitable. The series resistance effect induced by the interface state is the origin of device drain current degradation. The larger the generated interface states in the spacer region, the worse the device drain current degradation. LATID device or increasing n doping of an LDD device provides a way to reduce hot-carrier effect since most of generated interface states are located away from the spacer region such that the above series resitance effect becomes weak. With a tradeoff between the use of n implantation dosage and angle, we conclude that the design optimization of a hot-carrier resistant MOS device can be better understood through the use of the newly proposed method.
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Steve S. Chung (S’83–M’85–SM’95) received the B.S. degree (highest honors) from the National Cheng-Kung University, Taiwan, R.O.C., in 1973, the M.Sc. degree from the National Taiwan Uni-versity in 1975, and the Ph.D. degree from the University of Illinois, Urbana-Champaign, in 1985, all in electrical engineering.
From 1976 to 1978, he was with an electronic in-strument company as Director of the R&D Division and subsequently, as Manager of the Engineering Division. From 1978 to 1983, he was with the Department of Electronic Engineering and Technology at the National Taiwan Institute of Technology (NTIT) as a Lecturer. He was also in charge of an Instrument Calibration Center at NTIT. From 1983 to 1985, he held a research assistantship in the Solid State Electronics Laboratory and the Department of Electrical and Computer Engineering at the University of Illinois. In September 1985, he served at NTIT again as an Associate Professor in the Department of Electronic Engineering. Since August 1987, he has been with the Department of Electronic Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, and has been a Full Professor since the Fall of 1989. His current teaching and research interests are in the areas of device physics, deep-submicron CMOS VLSI technology; SPICE device modeling; numerical simulation and modeling of submicron and deep-submicron MOS devices, SOI devices, nonvolatile memories and TFT’s; characterization and reliability study of VLSI devices and circuits; and computational algorithms for VLSI circuits. He is a co-holder of ten US and ROC patents.
Dr. Chung has served on various technical program committees of IEEE ASIC Conference (U.S.), International Electron Devices and Materials Sympo-sium (IEDMS, Taiwan), and HPC (High Performance Computing)-ASIA’95. He is the recipient of the 1996–1998 Distinguished Research Award from the National Science Council, Taiwan.
Jiuun-Jer Yang received the B.S. degree from Nation Cheng-Kung University, Tainan, Taiwan, R.O.C., and the M.S. and Ph.D. degrees from Na-tional Chiao-Tung University, Hsinchu, Taiwan, all in electrical engineering, in 1989, 1991, and 1995, respectively.
Currently, he is a Deputy Manager at the Technol-ogy Development Center, Worldwide Semiconduc-tor Manufacturing Corporation, Hsinchu Science-Based Industrial Park, Taiwan, where he is en-gaged in TCAD and reliability evaluation for ad-vanced processes. His research interests include process/device reliability, process/device modeling, device design, and TCAD.
