CSIE 1000 Introduction to Computers National Taiwan University
Fall 2013 Department of CSIE
Sample Exam
November 13, 2013
• Signed integers are represented using two’s complement representation.
• Please use the following notations for logic gates. Feel free to change the orientations of the gates and the positions of inputs and outputs. You are free to use other circuits. However, if they are not introduced in the class, you have to implement them before using them.
NOT gate AND gate OR gate NAND gate XOR gate
1. (10%) What are the 8-bit binary representations of the following signed decimal integers? Convert them into hexadecimal.
a. 37 b. -18
2. (10%) Prove that (a){NOT, AND} and (b) {NOR} are universal.
3. (10%) Let Q= A + B(A + C) + AC. Prove that (a) Q = A + BC. (b) Draw a circuit to implement Q.
4. (10%) (a) Create the truth table for the 3-input Boolean function, Ones, which returns the number of 1’s in the input. For example, if the input X2X1X0= 101, then the output Z1Z0= 10 as there are two 1’s in the input. (b) Implement this function with logic gates AND, OR and NOT.
5. (15%) As shown in the following diagram, design a 4-bit comparator which has two 4-bit unsigned integer inputs, X3X2X1X0and Y3Y2Y1Y0, and a 3-bit output for the conditions of X > Y , X = Y and X < Y , respectively. Hint: design a 1-bit comparator first.
4-bit comparator
X Y
4 4
X>Y X=Y X<Y
X>Y X=Y X<Y
6. (20%) Design a binary multiplier that multiplies two 3-bit unsigned integers, X = X2X1X0 and Y = Y2Y1Y0, and a 6-bit output Z = Z5Z4. . . Z0and Z = X × Y , where X0, Y0and Z0are LSBs. You may use the notation X[n..m] to identify a portion of wires. For example, X[2..1] means the set of wires, X2X1. 7. (15%) Refer to the following figure for TOY architecture. Please specify the operations of M U XA, M U XB, M U XC, M U XD, M U XE, REGW, M EMW and ALUOP during the execution stage for the instructions ”subtract”, ”load”, and ”jump register”. For example, the answer for ”jump and link” would be M U XA = 0, M U XB = ∗, M U XC = ∗, M U XD = 1, M U XE = 01, REGW = 1, M EMW = 0, ALUOP = ∗.
8. (10%) Draw the required datapath on page 4 for (a) instruction fetch and (b) the set of instructions{”xor”,
”store”, ”branch zero” and ”jump and link”}. Only draw the necessary part but not the whole TOY datapath.
Add multiplexers if necessary. Remember to return page 4 with your answer sheet.
1
1 2
1 2
1 2
1 2 11
12 21
MUXA
MUXB
MUXC
MUXD MUXE
000 add/sub 001 and 010 xor 011 shift 100 input 2
ALUOP
MEMW
REGW
PC
Registers
W W Data
A Data B Data W Addr A Addr B Addr +
1
Memory
W W Data Addr
R Data
IR op
d s t
A L U Cond
Eval
2
