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(1)常見名詞電晶體 (Transistor) Chip: 矽晶片或微晶片積體電路 (Integrated Circuit, IC) Small Scale IC [SSI] Medium Scale IC [MSI] Large Scale IC [LSI] Very Large Scale IC [VLSI] Ultra Large Scale IC [ULSI] Giga Scale IC [GSI] Kilo: K 仟 Mega: M 百萬 Giga: G 十億 Tera: T 兆. Introduction to VLSI Design.

(2) Historical Perspective Era. Date. Complexity. Single Transistor. 1958. <1. Unit logic (one gate). 1960. 1. Multi-function. 1962. 2–4. Complex Function. 1964. 5 – 20. Medium Scale Integration (MSI). 1967. 20 – 200. Large Scale Integration (LSI). 1972. 200 – 2000. Very Large Scale Integration (VLSI). 1978. 2000 – 20000. Ultra Large Scale Integration (ULSI). 1989. 20000 - ?. Introduction to VLSI Design.

(3) Historical Perspective (Cont.) The monolithic integration of a large number of functions on a single chip usually provides: – Less area/volume and therefore, compactness – Less power consumption – Less testing requirements at system level – Higher reliability, mainly due to improved on-chip interconnects. – Higher speed, due to significantly reduced interconnection length – Significant cost saving Introduction to VLSI Design.

(4) Integration Level When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Moore’s Law: 每三年提升一個新世代 – 最小線幅寬度: 70% Smaller – 電路速度: 1.7 times Faster – 晶片複雜度: 3 times Higher – 成本價格: 70 % Lower Introduction to VLSI Design.

(5) 製程技術研發的演進公元. 1990. 1992. 0.8 µm. 1995. 0.6 µm. 0.5 µm. 2000. 0.35 µm. 2003. 0.25 µm. 2006. 0.18 µm. 2010. 0.1 µm. 1 µm: 1 微米. 次微米 Submicron. 深次微米 Deep Submicron. Introduction to VLSI Design. 奈米 Nanometer.

(6) 單晶片系統 (Systems-on-a-Chip, SOC). Introduction to VLSI Design.




(10) Chip Design & Manufacturing Flow IC Fabrication. Idea Wafer (hundreds of dies). Architecture Design. Sawing & Packaging. Block diagram. Final chips. Circuit & Layout Design. Testing. Layout customers Bad chips. Introduction to VLSI Design. Good chips.

(11) Design Styles Full Custom Design Flow – Circuit is created by composing a transistor netlist – SPICE simulation is performed to verify the circuit – Known as “capture-and-simulate” paradigm – Layout is mostly done manually – Popular for high-performance microprocessors & memories. Cell-Based Synthesis Flow – Design is first described by Hardware Description Language (e.g., Verilog and VHDL) – Based on a cell library, netlist is created by synthesis tools – Known as “describe-and-synthesize” paradigm – Layout can be done through automatic tools Introduction to VLSI Design.

(12) Custom Design Flow System Requirement Architecture and Logic Design Logic Diagram / Description Circuit & Layout Design fail Design Verification pass. Design Rules for Layout SPICE Models Circuit Simulation (SPICE) LVS: Layout Versus Schematic Check DRC: Design Rule Check. Mask Generation Wafer Fabrication. Wafer Testing & Packaging. Introduction to VLSI Design.

(13) Detailed Custom Design Flow Block Specification (Finite State Machine, Arithmetic Expression, Boolean Expression). Logic Design. Layout Design. Layout Rules. Layout Design Rule Checking (DRC) Layout vs. Schematic Check (LVS). Gate-Level Netlist Parasitic (or wiring) RC extraction Technology Mapping Post-Layout SPICE Simulation SPICE Model. Transistor Netlist SPICE Simulation. Check if SPEC is met ? If yes, done. Otherwise, go back to optimize the design. Introduction to VLSI Design.

(14) A Circuit Design Example Functionality – One-bit binary full-adder Technology – 0.8 µm twin-well CMOS technology Speed – Propagation delay times of sum and carry_out signals < 1.2 ns (worst case) – Transition delays times of sum and carry_out signals < 1.2 ns. Area < 1500 µm2 Power Dissipation – < 1 mW at VDD = 5 V and fmax = 20 MHz Introduction to VLSI Design.

(15) A Circuit Design Example (Cont.) A B. Sum_out. A B C. Full-adder Carry_out. C. Boolean Description Sum_out = A ♁ B ♁ C = ABC + AB’C’ + A’B’C + A’C’B Carry_out = AB + BC + CA (majority function). 0 0 0 0 1 1 1 1. 0 0 1 1 0 0 1 1. 0 1 0 1 0 1 0 1. Introduction to VLSI Design. Sum_ 0ut. Carry _out. 0 1 1 0 1 0 0 1. 0 0 0 1 0 1 1 1.

(16) Logic Design. x = Carry_out. Logic minimization trick: The carry_out signal is used to realize the function of signal sum in order to reduce the overall circuit size. Today’s logic synthesis tools (such as Design Compiler) incorporating some advanced algorithms, is able to perform automatic logic minimization.. Introduction to VLSI Design.

(17) Transistor-Level Schematic. x. x. y. y x = (AB+BC+CA) y = (A+B+C) x + ABC). Technology mapping – Many simple AND OR gates are merged into a complex gate (or a cell in the cell library). Transistor aspect ratio – pMOS (W/L) is usually larger than nMOS (W/L), e.g., 2:1 Introduction to VLSI Design.

(18) Initial Layout. Ratio of channel widths 2:1. Introduction to VLSI Design.

(19) Initial Layout (Cont.) The designer must confirm, using an automatic design rule checker (DRC) tool, that none of the physical layout design rule are violated in the adder layout. Post-layout SPICE simulation – Extract the “parasitic resistance & capacitance” – It is more accurate than the pre-layout simulation (pre-sim) – Assuming that the outputs of this adder circuit may drive a similar circuit, both output nodes are loaded with capacitors which represent the typical input capacitance of a full adder.. Design Verification Introduction to VLSI Design.

(20) I/O Simulation Waveforms Sum C (Carry_in). Propagation time tPHL or tPLH as defined above The worst-case delay is found to be about 2.0 ns – Need to go back to optimize the design !!!. Introduction to VLSI Design.

(21) Optimized Layout Propagation Delay < 5 ns !. Transistor Sizing – Changes the aspect ratios (W/L) of selected transistors – A larger aspect ratio may lead to a higher speed Wire Sizing is also more recently proposed Introduction to VLSI Design.

(22) Optimized Layout (Cont.) The propagation delay is about 1.0 ns, a reduction of 50%. The dynamic power dissipation of this circuit is estimated to be 460 µW.. Introduction to VLSI Design.

(23) Simulated Input and Output Waveforms. Introduction to VLSI Design.

(24) Modified Layout of the Full-Adder Circuit. Introduction to VLSI Design.

(25) Simulated Output Waveforms. Introduction to VLSI Design.

(26) 8-Bit Binary Adder S0. S1. S2. FA. FA. FA. A0 B0 A1 B1. S7 …. A2 B2. FA. A7 B7. The overall speed of the carry ripple adder is limited by the delay of the carry bits rippling through the carry chain. Introduction to VLSI Design.

(27) Mask Layout of the 4-bit Adder Fig. 1.16. Introduction to VLSI Design.

(28) Simulation Results. Introduction to VLSI Design.

(29) Overview of VLSI Design Methodology The design complexity of logic chips increases almost exponentially with the number of transistors to be integrated. This is translated into an increase in the design cycle, which is the time period from the start of chip development until the mask-tape delivery time. The level of circuit performance which can be reached within a certain design time strongly depends on the efficiency of the design methodologies, as well as on the design style. Introduction to VLSI Design.

(30) Impact of Different Design Styles. Introduction to VLSI Design.

(31) VLSI Design Flow: Y-Chart Behavioral Domain. Structural Domain Processor Register, ALU. Algorithm. Leaf Cell. Finite State Machine. Transistor Mask. Module Description. Boolean Equation. Cell Placement. Design Process: Module Placement 從抽象到具體 (行為→結構→實體). 從巨觀到微觀. Chip Floorplan. Geometrical Layout Domain Introduction to VLSI Design.

(32) A Simplified Design Flow System Spec. Circuit Design Functional (Architecture) Design. Functional Verification. Circuit Verification Physical Design. Logic Design Physical Verification Logic Verification Introduction to VLSI Design.

(33) Design Hierarchy The use of hierarchy technique involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. A hierarchy structure can be described in each domain separately.. Introduction to VLSI Design.

(34) Structural Decomposition of a 4-Bit Adder. Introduction to VLSI Design.

(35) Layout of a 16-Bit Adder. Introduction to VLSI Design.

(36) Regularity Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible.. Introduction to VLSI Design.

(37) Modularity and Locality Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces Modularity allows that each block or module can be designed relatively independently from each other. The concept of modularity enables the parallelization of the design process. The well-defined functionality and signal interface also allow the use of generic modules in various designs. The concept of locality also ensures that connections are mostly between neighboring modules. Introduction to VLSI Design.

(38) VLSI Design Styles⎯FPGA FPGA consists of an N x N array of PLB and programmable I/O blocks, connected by a programmable interconnect network. Programmable Logic Blocks Programmable I/O Blocks Programmable Interconnect. Introduction to VLSI Design.

(39) Design Flow of an FPGA Chip The typical design flow of an FPGA chip starts with the behavior description of its functionality, using a hardware description language such as VHDL. The synthesized architecture is then technologymapped into circuits or logic cells. Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs) After routing is completed, the on-chip performance of the design can be simulated and verified before downloading the design for programming of the FPGA chip. The largest advantage of FPGA-based design is the very short turn-around time. Introduction to VLSI Design.

(40) Gate Array Design In terms of fast prototyping capability, the gate array (GA) ranks second after the FPGA with a typical turnaround time of a few days. Metal mask design and processing is used for GA Gate array implementation requires a two-step manufacturing process – The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. – These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array. Introduction to VLSI Design.

(41) Basic Processing Steps for GA Implementation. Introduction to VLSI Design.

(42) A Corner of a Typical Gate Array Chips. Introduction to VLSI Design.

(43) Metal Mask Design. Introduction to VLSI Design.

(44) GA with Two Embedded Memory Banks. Introduction to VLSI Design.

(45) Sea-of-Gates (SOG) Chips. Introduction to VLSI Design.

(46) Comparison Between GA and SOG Chips. Introduction to VLSI Design.

(47) Standard-Cells Based Design The standard-cells based design is one of the most prevalent full custom design styles which require development of a full custom mask set. All of the commonly used logic cells are developed, characterized, and stored in a standard cell library. Each cell is characterized according to several different characterization categories: – – – – – –. Delay time versus load capacitance Circuit simulation model Timing simulation model Fault simulation model Cell data for place-and-route Mask data Introduction to VLSI Design.

(48) A Standard Cell Layout Example. Introduction to VLSI Design.

(49) A Simplified Floorplan Fig. 1. 37. Introduction to VLSI Design.

(50) A Simplified Floorplan (with a Common Signal Bus). Introduction to VLSI Design.

(51) Full Custom Design In a truly full-custom design, the entire mask design is done anew without use of any library. The development cost of such a design style is becoming prohibitively high. For logic chip design, a good compromise can be achieved by using a combination of different design style on the same chip. In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high-performance microprocessors, and FPGA masters. Introduction to VLSI Design.

(52) Mask Layout of the Intel Pentium Microprocessor Chip. Introduction to VLSI Design.

(53) Design Quality Testability – Generation of good test patterns – Availability of reliable test fixture at speed. – Design of testable chip Yield and manufacturability – Functional yield – Parametric yield Reliability Technology updateability Introduction to VLSI Design.

(54) Signal Integrity Problems Electro-migration – Excessive current density along metal wires may cause the drifting of metal atoms, leading to open circuits IR Drop – Too narrow power/ground lines may cause significant voltage drops at the VDD nodes of cells Ground Bounce – Inductance effect of bonding wires may cause voltage increase at ground lines because ∆V = L (di/dt) Cross Talk – Coupling capacitance between long running wires affects circuit’s timing or even functionality. Introduction to VLSI Design.

(55) Computer-Aided Design technology High level synthesis Logic synthesis Circuit optimization Layout Simulation Design rules checking Formal verification. Introduction to VLSI Design.

(56) Taxonomy of Synthesis Tasks. Struc tural View. Behavioral View. Architectural Level. Logic Level. Circuit Level. state. a b. 0. (i: 1..16) :: sum = sum*z–1 + coeff[i]*In*z–1. 2. 1 3. tp Logic Synthesis. Architecture Synthesis. Circuit Synthesis. a b. mem. x. c. 4. fsm. c. *. x. D. Introduction to VLSI Design. a. 2. b. 2. 1. c.

(57) Advances in Design Methodology HDL Modeling and Simulation – VHDL & Verilog for Behavior Modeling at Higher Level RTL Synthesis – A Short-Cut from RTL to Logic Netlist Structural Behavioral Physical Design Automation – Automatic Placement & Route Design for Testability – Scan and Built-In Self-Test Static Design Verification – Formal Verification, Static Timing Analysis Design automation leads to higher productivity ! but not always better performance !! Introduction to VLSI Design. Physical.

(58) Various Levels of Simulation HDL Simulation – Behavioral HDL simulation – Register-Transfer-Level (RTL) simulation – Gate-Level simulation Switch-Level Simulation Transistor-Level Simulation – (e.g., PowerMill, Hsim) Circuit Simulation – (e.g., SPICE) Introduction to VLSI Design.

(59) Cell-Based Design Flow Architecture design Testbench. Functional model. RTL coding & simulation RTL code. synthesis view RTL-synthesis (Design Compiler). layout. Netlist. Cell Library physical view. Place & Route (Apollo) Layout. SDF: standard delay format. SDF. Post-Layout Timing Check (Design Time) No violation System-level integration Introduction to VLSI Design. Memory module. violation.

(60) Design Flow and Defect Level spec.. # bad chips Defect Level: --------------------------(可能的退貨率) # total shipped chips. design flow. The quality of test patterns dictates the defect level. layout. test patterns. manufacturing. Introduction to VLSI Design.

(61) Design for Testability (DFT) spec. Design flow. layout. design activities for generating higher-quality test patterns (or improving the testability). DFT flow better test patterns. manufacturing. Introduction to VLSI Design. good chips.

(62) Topics in CMOS Digital Design Regular Structures (RAMs, ROMs, PLAs). µP, Custom Logic. Logic Circuits, Gates, Latches. 2-Transistor Circuits (Inverters). Device Electronics. Device Physics. Introduction to VLSI Design.

(63) Department of Electronic Engineering, FJU. Introduction to VLSI Design. End of Introduction !. Introduction to VLSI Design.

(64) Lecture 2. Fabrication of MOSFETs. Introduction to VLSI Design.

(65) Simplified Process Sequence Wells or tubs – To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. Twin-tub CMOS technology Active region. Createn-well n-wellregions regions Create Andchannel-stop channel-stopregions regions And Growfield fieldoxide oxideand and Grow gateoxide oxide(thin (thinoxide) oxide) gate Depositand andpattern pattern Deposit Polysiliconlayer layer Polysilicon Implantsource sourceand anddrain drain Implant regions,substrate substratecontacts contacts regions, Createcontact contactwindows windowsDeposit Deposit Create andpattern patternmetal metallayer layer and. Introduction to VLSI Design.

(66) MOSFET Transistor P-channel. N-channel D. D B. G S. G. D G. S. B. G S. S. S. S. D. Introduction to VLSI Design. G. G D. D.

(67) Basic Steps Each processing step requires that certain areas are defined on chip by appropriate masks. The integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal, and insulating silicon dioxide. The process used to transfer a pattern to a layer on the chip is called lithography. The lithographic sequence must be repeated for every layer, using a different mask.. Introduction to VLSI Design.

(68) Oxidation & Lithography (微影). Si-substrate. lithography. Thermal oxidation SiO2 (Oxide). Si-substrate photoresist SiO2 (Oxide). Si-substrate. Mask 光罩 - defines the pattern Lithography - to pattern silicon dioxide Photoresist 光阻 - acid-resistant material before UV-light, but soluble after. Introduction to VLSI Design.

(69) Etching (蝕刻). Chemical etch (HF acid) or dry etch (plasma). (after baking) Hardened Photoresist SiO2. Introduction to VLSI Design.

(70) Window of Active Region. solvent. Pattern transfer: from mask to silicon dioxide, polysilicon, or metal requires lithography + etching Introduction to VLSI Design.

(71) Fabrication of the nMOS Transistor Deposit the Poly (by CVD (Chemical Vapor Deposition). Field Oxide. Deposit a layer of thin oxide Pattern the poly gate. Introduction to VLSI Design.

(72) Diffusion (擴散) or Ion Implantation Self-Align Doping: – The poly gate is patterned before doping so that the channel and source/drain regions are accurately positioned. – Less gate-to-source/drain overlapping, better performance. Poly Gate Resistance – Relatively high originally, reduced after the doping process. Introduction to VLSI Design.

(73) Metallization – for Interconnect Aluminum or Copper Multiple Layers – dielectric layers in between Via: contact hole between layers of metals. B C. A. A: thin oxide B: metal-poly insulator C: field oxide Introduction to VLSI Design.

(74) Local Oxidation of Silicon (LOCOS) Selectively grow the Field Oxide (FOX), Instead of selectively etching away the active regions – FOX recesses into the silicon surface, thus, more planar surface – Provides better isolation for adjacent transistors. Introduction to VLSI Design.

(75) LOCOS Steps Si3N4 as the shield of oxidation. Si3N4: silicon nitride. Introduction to VLSI Design.

(76) Department of Electronic Engineering, FJU. Introduction to VLSI Design. The CMOS n-Well Process Oxidation Lithography Etching Diffusion. (微影) 微影 (蝕刻). Introduction to VLSI Design.

(77) Layout and Cross-Section View of Inverter VDD. In. In. GND. VDD In. Out VDD. Out. Out. GND Legend of each layer. Cross-Section View. N-well P-diffusion N-diffusion Polysilicon Metal contact. Introduction to VLSI Design.

(78) Detailed Cross-Section View. Introduction to VLSI Design.

(79) 3-D Structure of a CMOS Inverter In. VDD. GND Out. IC = patterned layers of - doped silicon - polysilicon - metal - insulating silicon dioxide Introduction to VLSI Design.

(80) Simplified CMOS Process Flow Create n-well and active regions Grow gate oxide (thin oxide) Deposit and pattern polysilicon layer Implant source and drain regions, substrate contacts. Create contact windows, deposit and pattern metal layers Introduction to VLSI Design.

(81) N-well, Active Region, Gate Oxide. Top View. Cross Section. Introduction to VLSI Design.

(82) Polysilicon Layer. Introduction to VLSI Design.

(83) N+ and P+ Regions. Ohmic contacts. Introduction to VLSI Design.

(84) SiO2 Upon Device & Contact Etching. Introduction to VLSI Design.

(85) Metal Layer – by Metal Evaporation. Introduction to VLSI Design.

(86) A Complete CMOS Inverter. Introduction to VLSI Design.

(87) Layout Design Rules A set of constraints put on layout to accommodate process variations – Minimum spacing: to avoid short circuits – Minimum width: to avoid break open – Enclosure or extension: to make sure of overlapping To avoid S. D. S. D. source and drain might be shorted in real silicon !. Gate extension rule. Objective: To achieve high yield with smallest area Micron rules: the constraints are in micrometers Lambda rules: constraints are in terms of a single parameter λ, more scalable but less area efficient Introduction to VLSI Design.

(88) Design Rule Illustration. metal. Active. poly. Active poly. metal Introduction to VLSI Design.

(89) Design Rules and Dimensions of Minimizesize Transistor. Minimum width Of the active area. Minimum separation from Contact to active edge. Minimum width of polysilicon. Introduction to VLSI Design.

(90) Substrate & Well Contacts Source & Drain Contacts: - surrounded by p+ region in the n-well - surrounded by n+ region in the p-substrate N-well Contacts: - surrounded by n+ region in the n-well - connect n-well to VDD Substrate Contacts: - surrounded by p+ region in the p-substrate - connect p-substrate to GND Many substrate & well contacts are needed to avoid latch-up problem, sometimes form a guard-ring Introduction to VLSI Design.

(91) Lecture 3 MOS Transistor Theory. Introduction to VLSI Design.

(92) Outline. • Structure and Operation of MOS Transistor • Threshold Voltage Calculation • Current-Voltage Characteristic • MOS Scaling • MOS Capacitance. Introduction to VLSI Design.

(93) Structure and Operation of MOSFET In Logic Circuits: MOSFETs are used as voltage-controlled switches + D N-MOS+ G ON-switch: when VGS > VT VDS OFF-switch: when VGS < VT VGS S Where VT is called threshold voltage and P-substrate is always grounded Common source. • The physical structure of an n-channel enhancement-type MOSFET. Introduction to VLSI Design.

(94) Small Positive VGS (Depletion Mode) Majority carriers (holes) are repelled back into the substrate The surface of p-type substrate is depleted. Introduction to VLSI Design.

(95) Larger VGS (Inversion Mode) Definition: Threshold voltage VT is the gate-to-source voltage needed to cause surface inversion to create the conducting channel.. Introduction to VLSI Design.

(96) Linear Mode (Small VD) In Linear Mode, channel region acts as a voltage-controlled resistor The channel depth on the drain side decreases as VD increases. Introduction to VLSI Design.

(97) Edge of Pinch-Off Mode (As VD = VDSAT ) Def: VDSAT is the min. voltage of VD forcing the channel to pinch-off The device starts to operate in saturation mode. Introduction to VLSI Design.

(98) Saturation Mode (As VD > VDSAT) Channel Length Modulation: In Saturation Mode, the effective channel length reduced, while the voltage across remains constant (VDSAT). Introduction to VLSI Design.

(99) Body Effect Nonzero source-substrate bias (i.e., VSB>0) affects the threshold voltage (VT is higher for n-device, lower for pdevice). VT = VT 0 + γ ⋅ ( | −2φF + VSB | − | 2φF | ) 2q ⋅ N A ⋅ ε Si γ= Cox Body-effect coefficient NAND 1/2. Body-effect constant (e.g., 0.42 V Introduction to VLSI Design. ).

(100) Influence of Body-Effect. Introduction to VLSI Design.

(101) Outline. Department of Electronic Engineering, FJU. Introduction to VLSI Design. • Structure and Operation of MOS Transistor • Threshold Voltage Calculation • Current-Voltage Characteristics • MOS Scaling • MOS Capacitance. Introduction to VLSI Design.

(102) Drain I-V Before Pinch-Off k' W 2 I D = ⋅ ⋅ [2 ⋅ (VGS − VT 0 )VDS − VDS ] 2 L k ' = µ n ⋅ Cox VGS ≥ VT 0 VGD = VGS − VDS ≥ VT 0 Peak at VDS=VGS-VT0. Introduction to VLSI Design.

(103) Saturation Current k' W I D = ⋅ ⋅ [(VGS − VT 0 ) 2 ] 2 L k ' = µ n ⋅ Cox VGS ≥ VT 0 VGD = VGS − VDS ≤ VT 0. Introduction to VLSI Design.

(104) Saturation Current v.s. Gate Voltage. Introduction to VLSI Design.

(105) Channel Length Modulation (I). When VDS > VDSAT (i.e., VGS-VT) Channel voltage at pinch-off point (i.e., L’) remains: VDSAT Introduction to VLSI Design.

(106) Channel Length Modulation (II) µ nCOX W 1 I D ( SAT ) = ⋅ (VGS − VT 0 ) 2 ∆L 2 L 1− L L’ = L – ∆L ∆L ∝ VDS − VDSAT. (Effective channel Length). ∆L 1− ≈ 1 − λV DS L µ nCOX W (VGS − VT 0 ) 2 (1 + λV DS) I D ( SAT ) = 2 L. λ is called channel length modulation coefficient ( ~ 0.1 to 0.005 V-1) Introduction to VLSI Design.

(107) Drain Current. Channel Length Modulation (III). Introduction to VLSI Design.

(108) Substrate Bias Effect. I D (lin ) =. µ nCOX W. 2 (2(VGS − VT (VSB ))VDS − VDS ). 2 L µC W I D ( SAT ) = n OX (VGS − VT (VSB )) 2 (1 + λV DS) 2 L I D = f (VGS , VDS , VBS ) Introduction to VLSI Design.

(109) Measurement of Parameters. kn I D ( SAT ) = (VGS − VT 0 ) 2 2 kn ID = (VGS − VT 0 ) 2 Introduction to VLSI Design.

(110) Test Circuit Arrangement. kn (VGS − VT 0 ) 2 (1 + λVDS ) 2 1 + λVDS 2 = 1 + λVDS1. I D ( SAT ) = I D2 I D1. Introduction to VLSI Design.

(111) Example 3. 5 (I) Determine the type of the device, and calculate the parameters kn, VT0, and γ, assume φF = -0.3V. Neglecting the channel-length modulation effect. VGS(V). VDS(V). VSB(V). ID(µA). 3 4 5 3 4 5. 3 4 5 3 4 5. 0 0 0 3 3 3. 97 235 433 59 173 347. Introduction to VLSI Design.

(112) Example 3.5 (II) This device is a n-channel MOSFET Assume that the transistor is enhancement-type and, operating in saturation mode for VGS = VDS. ID =. kn (V GS − VT ) 2 ⇔ 2. ⇒. I D1 =. ID2 = I D1 − ∴. ID =. kn (V GS − VT ) 2. kn (V GS 1 − VT ) 2. kn (V GS 2 − VT ) 2 ID2 =. kn (V GS 1 − V GS 2 ) 2. I D1 − I D 2 kn = = 2 V GS 1 − V GS 2. 433 µ A − 97 µ A = 5 . 48 × 10 − 3 A1 / 2 / V 5V − 3V. Introduction to VLSI Design.

(113) Example 3. 5 (III) ∴ k n = 2 × ( 5 .48 × 10 − 3 ) 2 = 60 × 10 − 6 A / V 2 = 60 µ A / V 2 kn (V GS − VT 0 ) 2 ... when ID = V SB = 0 2 2 I D 1/ 2 ) = 1 .2V ∴ VT 0 = V GS − ( kn VT (V SB = 3V ) = V GS. γ =. 2 I D 1/ 2 2 × 173 µ A 1 / 2 ) = 1 .6V −( ) = 4V − ( 2 60 µ A / V kn. VT (V SB = 3V ) − VT 0 = | 2φ F | +V SB − | 2φ F |. 1 .6V − 1 .2V 0 .6V + 3V − 0 .6V. Introduction to VLSI Design.

(114) Device Scaling (Shrinking) The reduction of the size of MOSFETs is commonly referred to as scaling. Types: (1) Full Scaling (2) Constant Voltage Scaling A new generation for every 2 ~ 3 years S: Scaling factor > 1 (1.2 ~ 1.5 from one generation to the next). Introduction to VLSI Design.

(115) Scaling of a Typical MOSFET. Introduction to VLSI Design.

(116) Full Scaling of MOSFET. Introduction to VLSI Design.

(117) Full Scaling (Constant-Field Scaling) Physical dimensions: 1/S Power Supply: 1/S Doping Density: S. P = I D ⋅ VDS P ' = I D ⋅ VDS = '. '. 1 P ⋅ = I V D DS S2 S2. Cox' =. ε ox t. ' ox. =S⋅. ε ox tox. = S ⋅ Cox. k n' ' '2 − VDS I (lin) = [2(VGS' − VT' )VDS ] 2 S ⋅ kn 1 2 = − − V V V V [ 2 ( ) GS T DS DS ] 2 S2 I D (lin) = S k n' ' I D ( sat ) = [(VGS' − VT' ) 2 ] 2 S ⋅ kn 1 2 = − [( V V ) ] GS T 2 2 S I ( sat ) = D S ' D. Introduction to VLSI Design.

(118) Full Scaling (Constant-Field Scaling) Quantity Oxide Capacitance Drain Current Power Dissipation Power density. Before Scaling. After Scaling. Cox ID P P/Area. Cox‘ = SCox ID‘ = ID/S P”= P/S2 P’/Area’ = P/Area. The gate oxide capacitance is scale down by a factor of S.. Introduction to VLSI Design.

(119) Constant Voltage Scaling Physical dimensions: 1/S Power Supply: 1 Doping Density: S2. ' k ' '2 I D' (lin) = n [2(VGS' − VT' )VDS ] − VDS 2 S ⋅ kn 2 = [2(VGS − VT )VDS − VDS ] ' ' ' P = I D ⋅ VDS = S ⋅ I D ⋅ VDS = S ⋅ P 2 = S ⋅ I D (lin) Power density Increase by S3 →. with possible adverse effects on device reliability. k n' I ( sat ) = [(VGS' − VT' ) 2 ] 2 S ⋅ kn = [(VGS − VT ) 2 ] 2 = S ⋅ I D ( sat ) ' D. Introduction to VLSI Design.

(120) Effect of Constant-Voltage Scaling. Introduction to VLSI Design.

(121) Short Channel Effects (I) A MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions. Alternately, a MOSFET can be defined as a shortchannel device if the effective channel length is approximately equal to the source and drain depth. The short-channel effects that arise in this case are attributed to two physical phenomena: – The limitations imposed on electron drift characteristic in the channel – The modification of the threshold voltage due to the shortening channel length. Introduction to VLSI Design.

(122) Short-Channel Effects (II). trapezoidal region. Introduction to VLSI Design.

(123) Short-Channel Effects (III). Introduction to VLSI Design.

(124) Narrow-Channel Effects (I) A device is defined to have a narrow channel if channel width W is on the same order of magnitude as the maximum depletion region thickness xdm VT tends to increase due to the shallow depletion region charge underneath the GATE-to-FOX overlap area, QNC V T0(narrow channel) = VT0 + ∆ VT0. Introduction to VLSI Design.

(125) Narrow-Channel Effects (II). Introduction to VLSI Design.

(126) Hot-Carrier Injection In small-geometry devices, – carrier has a higher kinetic energy, and thus might be able to inject into the thin-oxide area – resulting a higher VT, thereby a lower transconductance – causing a reliability problem. Introduction to VLSI Design.

(127) MOSFET Capacitance Important in deciding the transient (AC) response of digital circuits consisting of MOSFETs Depends on layout geometry and process Two types – Device-related capacitances • Oxide-related capacitances – Cgs, Cgd, Cgb • Junction capacitances • Csb, Cdb – Interconnect capacitances (discussed in chapter 6). Introduction to VLSI Design.

(128) Cross-Sectional View and the Top View of a NMOS. Introduction to VLSI Design.

(129) Parasitic MOSFET Capacitance. Introduction to VLSI Design.

(130) Overlap Capacitance CGS (overlap) = Cox·W ·LD, CGD (overlap) = Cox·W ·LD where Cox = εox/tox → Voltage-independent. Introduction to VLSI Design.

(131) Cut-Off Mode Oxide Capacitance. Cgb = Cox·W ·L (3.96) Cgs = Cgd = 0 Introduction to VLSI Design.

(132) Linear Mode Oxide Capacitance. Cgs = 0.5 · Cox · W · L Cgd = 0.5 · Cox · W · L Cgb = 0 Introduction to VLSI Design.

(133) Saturation Mode Oxide Cap.. Cgs = (2/3) · Cox·W ·L Cgd = Cgb = 0 Introduction to VLSI Design.

(134) Summary of Oxide-Capacitance (I). Introduction to VLSI Design.

(135) Summary of Oxide-Capacitance (II). Introduction to VLSI Design.

(136) Junction Capacitance. Introduction to VLSI Design.

(137) Junction Capacitance. For source or drain 3 sides surrounded by p+ 1 side by p-substrate 1 side by channel. Introduction to VLSI Design.

(138) Detailed View of Source Junction. Introduction to VLSI Design.

(139) Depletion Region Charge Barrier voltage. Bias-dependent depletion width. Depletion region charge. φ0. Introduction to VLSI Design.

(140) Junction Capacitance. m is the grading coefficient ½ for an abrupt junction 1/3 for linearly graded junction. Zero-bias junction capacitance per unit area. Large-signal average capacitance. Introduction to VLSI Design.

(141) Voltage Equivalence Factor. (abrupt pn-junctions) (e.g., 68 fF with A=20um x 20 um)). (e.g., 2.9x10-8 F/cm2). (e.g., 0.57 with 5 volts swing ). Keq is the voltage equivalence factor (0 < Keq< 1) Introduction to VLSI Design.

(142) Sidewall Junction Capacitance Zero-bias cap. per unit area Zero-bias cap. per unit length. Example number: Cdb = A· Cj0 · Keq + P · Cjsw · Keq(sw) = 3.86 + 7.7 (fF) = 11.6 (fF) Introduction to VLSI Design.

(143) Department of Electronic Engineering, FJU. Introduction to VLSI Design. Lecture 4 MOS Inverter: Static Characteristics. Introduction to VLSI Design.

(144) Ideal Inverter truth table A. B = A’. A 0 1. B 1 0. Voltage transfer characteristic (VTC) of the ideal inverter Positive logic convention Inverter threshold voltage. Introduction to VLSI Design.

(145) General Circuit Structure of an nMOS Inverter nMOS Driver as a high-active switch: (1) On state: Cout is discharged to logic ‘0’ (2) Off state: Cout is charged to logic ‘1’ thru load component (3) The voltage transfer characteristic describing Vout as a function of Vin. ID(Vin, Vout) = IL(VL) Load. Driver Transistor. Introduction to VLSI Design.

(146) Definitions Of VOH, VOL, VIL, VIH, VTH Uncertain or transition region VIL: max. input for logic ‘0’ VIH: min. input for logic ‘1’ VOH: max. output for logic ‘1’ VOL: min. output for logic ‘0’ The inverter threshold voltage Vth is defined as the point where Vin = Vout on the VTC. Introduction to VLSI Design.

(147) Tolerance to External Signal Perturbation Circuit Noise: unwanted signals coupled to some part of circuit from neighboring lines by capacitive or inductive coupling or from outside of the system.. Introduction to VLSI Design.

(148) Noise Margins VIN. VOUT VOH. VIH VIL VOL. Noise Margin for Logic ‘1’ NMH = VOH – VIH Noise Margin for Logic ‘0’ NML = VIL – VOL Introduction to VLSI Design.

(149) Power and Area Considerations Why power dissipation is important: – Tj = Ta + θP – PDC = VDDIDC = (VDD/2)[IDC(Vin = low) + IDC(Vin = high)] – Heat dissipation, (I.e., the removal of thermal energy, or the cooling of the chip) becomes expensive – More and more devices are operated by battery. Design Trade-off – – – – –. Noise Margin Power Dissipation Area (or Die size) Speed (or Performance) Testability Introduction to VLSI Design.

(150) Resistive-Load Inverter Approximation by regarding the nMOS as RD: Vin= HIGH, Vout=(RD/(RL+RD) ~ hopefully low Vin=LOW, Vout=VDD. Input Voltage Range. Operating Mode. Vin < VT0 VT0 ≤ Vin < Vout + VT0 Vin ≥ Vout + VT0. Cut-off Saturation linear. Introduction to VLSI Design.

(151) Output voltage. Example Voltage Transfer. Input voltage Introduction to VLSI Design.

(152) Example Voltage Transfer Calculation of VOH: VOH = VDD Calculation of VOL Assume the input voltage = VOH → linear region IR =. VDD − Vout RL. Q IR = ID ∴. VDD − Vout k n 2 = [2(VDD − VT 0 )VOL − VOL ] RL 2. VOL − 2(VDD − VT 0 + 2. VOL = VDD − VT 0 +. 1 2 VDD = 0 )VOL + k n RL k n RL. 1 1 2 2 − (VDD − VT 0 + VDD ) − k n RL k n RL k n RL Introduction to VLSI Design.

(153) Calculation of VIL The driver transistor VDD − Vout = k n (V − V ) 2 in T0 RL 2 operates in saturation 1 dVout − = k n (Vin − VT 0 ) RL dVin. −. 1 (−1) = k n (VIL − VT 0 ) RL. VIL = VT 0 +. 1 k n RL. Vout (Vin = VIL ) = VDD − = VDD −. k nRL 1 (VT 0 + − VT 0 ) 2 2 k n RL. 1 2k n RL. Introduction to VLSI Design.

(154) Calculation of VIH The driver transistor operates in linear region. VDD − Vout k n 2 = [2(Vin − VT 0 )Vout − Vout ] RL 2 −. dV dV 1 dVout k n = [2(Vin − VT 0 ) out + 2Vout − 2Vout out ] R L dVin dVin dVin 2. −. 1 (−1) = k n [2(VIH − VT 0 )(−1) + 2Vout ] RL. 1 ⎧ = + − 2 V V V 0 IH T out ⎪ k nRL ⎪ ⎨ ⎪VDD − Vout = k n [2(V − V )V − V 2 ] in T0 out out ⎪⎩ RL 2 VDD − Vout k n 1 2 ] = [2(VT 0 + 2Vout − − VT 0 )Vout − Vout 2 k nRL RL Vout (Vin = VIH ) = VIH = VT 0 +. 2 VDD 3 k n RL. 8 VDD 1 − 3 k n RL k n RL. Introduction to VLSI Design.

(155) Impact of knRL on VTC. Introduction to VLSI Design.

(156) Power Consumption and Chip Area The average DC power consumption of the resistive-load inverter circuit is found by considering two cases, Vin = VOL(low) and Vin = VOH (high). When the input voltage is equal to VOL, the driver transistor is in cut-off. ID = IR = 0, and the DC power dissipation is equal to zero. When the input voltage is equal to VOH,. ID = IR = Example 5. 1. PDC ( average). VDD − VOL RL. VDD VDD − VOL = RL 2. Introduction to VLSI Design.

(157) Sample Layouts of Resistive Inverters Diffusion’s resistance: 20 ~ 100 Ω/square Undoped poly’s resistance is very high ~ 10 MΩ/square. Introduction to VLSI Design.

(158) Enhancement-Load nMOS Inverter VOH is only VDD-VT because nMOS cannot pass VDD. VOH is improved to VDD at the cost of another supply VGG. Always in Linear region. Introduction to VLSI Design.

(159) Depletion-Load nMOS Inverter. ID. VSB,load = Vout Vin. Introduction to VLSI Design. Vout.

(160) Typical VTC VOH = VDD. Introduction to VLSI Design.

(161) Calculation of VOL ID. Vout Driver in linear, depletion-load in saturation. Introduction to VLSI Design.

(162) Calculation of VIL Driver in Saturation, Depletion-load in Linear. ID differentiate both sides. Vout. set dVout/dVin = -1. Introduction to VLSI Design.

(163) Calculation of VIH Driver in Linear, Depletion-load in Saturation. ID differentiate both sides. Vout set dVout/dVin = -1. Needs to be included Introduction to VLSI Design.

(164) Impact of kR on VTC. Introduction to VLSI Design.

(165) Sample Layout of Depletion-Load Inv. Donor implant to make VT0,load negative. Buried contact: contact between gate and diffusion. Donor Implant. Introduction to VLSI Design.

(166) CMOS Inverter. Vin=LOW, Vout is charged to VDD thru pMOS Vin=HIGH, Vout is discharged to GND thru nMOS Introduction to VLSI Design.

(167) Operating Region. Introduction to VLSI Design.

(168) Operating Region (Cont.). Introduction to VLSI Design.

(169) Inverter VDD. Out. Drain current (x0.1 mA). Current-Voltage Surface of nMOS. VGS = Vin VDS = Vout. GND. Introduction to VLSI Design.

(170) Inverter VDD. S In. D Out. Drain current (x0.1 mA). Current-Voltage Surface of pMOS VGS = Vin-VDD VDS = Vout-VDD. GND. Introduction to VLSI Design.

(171) Intersection of Two I-V Surfaces Intersection dictates the curve that satisfies: ID,p = ID, n (steady-state condition). Inverter VDD. ID,p In Out. ID,n GND. Introduction to VLSI Design.

(172) Operation Points - continue VDD. ID In. Out. C. GND D. B. A E. VGS,p = Vin-VDD VGS,n = Vin. Vout. Introduction to VLSI Design.

(173) Impact of kR on VTC Symmetric Inverter: VIL = 1/8 (3VDD + 2VT0,n) VIH = 1/8 (5VDD - 2VT0,n). NML = NMH = VIL. Introduction to VLSI Design.

(174) Steady-State (DC) Power Dissipation. PDC = VDD · IDC ~ VDD/2 · (IDC(Vin = low) + IDC(Vin= high)) = 0 for CMOS Inverters Note: dynamic (or switching power) is not zero Introduction to VLSI Design.

(175) Supply Voltage Scaling. Introduction to VLSI Design.

(176) Sample Layouts. Introduction to VLSI Design.

(177) Pros and Cons nMOS Logic (Depletion-load). CMOS Logic. Noise Margin. smaller. larger. Area. smaller. larger. Speed Power Dissipation. unbalanced rise & fall time larger Introduction to VLSI Design. balanced rise & fall much smaller.

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