Sequential Circuits

Digital Logic Design

B i

„

Basics

„

Combinational Circuits

„

Sequential Circuits

Pu-Jen Cheng

Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design.

Introduction to Digital Logic Basics

„

Hardware consists of a few simple building blocks

¾ These are called logic gates

„ AND, OR, NOT, …

„ NAND, NOR, XOR, …

L i t b ilt i t i t

„

Logic gates are built using transistors

„ NOT gate can be implemented by a single transistor

„ AND gate requires 3 transistors

„

Transistors are the fundamental devices

„ Pentium consists of 3 million transistors

„ Compaq Alpha consists of 9 million transistors

„ Now we can build chips with more than 100 million transistors

Basic Concepts

„ Simple gates

¾ AND

¾ OR

¾ NOT

„ Functionality can be

expressed by a truth table

¾ A truth table lists output for each possible input

combination

„ Precedence

¾ NOT > AND > OR

¾ F = A B + A B

= (A (B)) + ((A) B)

Basic Concepts (cont.)

„ Additional useful gates

¾ NAND

¾ NOR

¾ XOR

„ NAND = AND + NOT

„ NOR = OR + NOT

„ NOR = OR + NOT

„ XOR implements

exclusive-OR function

„ NAND and NOR gates require only 2 transistors

¾ AND and OR need 3 transistors!

Basic Concepts (cont.)

„

Number of functions

¾ With N logical variables, we can define 2^2N functions

¾ Some of them are useful

AND NAND NOR XOR

„ AND, NAND, NOR, XOR, …

¾ Some are not useful:

„ Output is always 1

„ Output is always 0

¾ “Number of functions” definition is useful in proving completeness property

Basic Concepts (cont.)

„

Complete sets

¾ A set of gates is complete

„ If we can implement any logical function using only the type of gates in the set

„ You can uses as many gates as you want

¾ Some example complete sets

¾ Some example complete sets

„ {AND, OR, NOT} Not a minimal complete set

„ {AND, NOT}

„ {OR, NOT}

„ {NAND}

„ {NOR}

¾ Minimal complete set

„ A complete set with no redundant elements.

Basic Concepts (cont.)

„ Proving NAND gate is universal

„ NAND gate is called universal gate

Basic Concepts (cont.)

„ Proving NOR gate is universal

„ NOR gate is called universal gate

Logic Chips

Logic Chips (cont.)

„

Integration levels

¾ SSI (small scale integration)

„ Introduced in late 1960s

„ 1-10 gates (previous examples)

¾ MSI (medium scale integration)

„ Introduced in late 1960s

„ 10-100 gates

¾ LSI (large scale integration)

„ Introduced in early 1970s

„ 100-10,000 gates

¾ VLSI (very large scale integration)

„ Introduced in late 1970s

„ More than 10,000 gates

Logic Functions

„

Logical functions can be expressed in several ways:

¾ Truth table

¾ Logical expressions Graphical form

¾ Graphical form

„

Example:

¾ Majority function

„ Output is 1 whenever majority of inputs is 1

„ We use 3-input majority function

Logic Functions (cont.)

3-input majority function

A B C F

0 0 0 0

0 0 1 0

„ Logical expression form F = A B + B C + A C

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Logical Equivalence

„ All three circuits implement F = A B function

Logical Equivalence (cont.)

„

Proving logical equivalence of two circuits

¾ Derive the logical expression for the output of each circuit

¾ Show that these two expressions are equivalent

„ Two ways:

„ Two ways:

„ You can use the truth table method

„ For every combination of inputs, if both expressions yield the same output, they are equivalent

„ Good for logical expressions with small number of variables

„ You can also use algebraic manipulation

„ Need Boolean identities

Logical Equivalence (cont.)

„ Derivation of logical expression from a circuit

¾ Trace from the input to output

„ Write down intermediate logical expressions along the path

Logical Equivalence (cont.)

„

Proving logical equivalence: Truth table method

A B F1 = A B F3 = (A + B) (A + B) (A + B) 0 0 0 0

0 1 0 0

0 1 0 0 1 0 0 0 1 1 1 1

Boolean Algebra

Boolean Algebra (cont.)

Boolean Algebra (cont.)

„

Proving logical equivalence: Boolean algebra method

¾ To prove that two logical functions F1 and F2 are equivalent

„ Start with one function and apply Boolean laws to

„ Start with one function and apply Boolean laws to derive the other function

„ Needs intuition as to which laws should be applied and when

„ Practice helps

„ Sometimes it may be convenient to reduce both functions to the same expression

¾ Example: F1= A B and F3 are equivalent

A B = (A + B) (A + B) (A + B)

Logic Circuit Design Process

„ A simple logic design process involves

¾ Problem specification

¾ Truth table derivation

¾ Derivation of logical expression

¾ Simplification of logical expression

I l t ti

¾ Implementation

Deriving Logical Expressions

„

Derivation of logical expressions from truth tables

¾ sum-of-products (SOP) form

¾ product-of-sums (POS) form

„

SOP form

W i AND f h i bi i h

¾ Write an AND term for each input combination that produces a 1 output

„ Write the variable if its value is 1; complement otherwise

¾ OR the AND terms to get the final expression

„

POS form

¾ Dual of the SOP form

Deriving Logical Expressions (cont.)

„ 3-input majority function

A B C F

0 0 0 0

0 0 1 0

„ SOP logical expression

„ Four product terms

¾ Because there are 4 rows with a 1 output

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

F = A B C + A B C + A B C + A B C

Deriving Logical Expressions (cont.)

„ 3-input majority function

A B C F

0 0 0 0

0 0 1 0

„ POS logical expression

„ Four sum terms

¾ Because there are 4 rows with a 0 output

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

F = (A + B + C) (A + B + C) (A + B + C) (A + B + C)

Logical Expression Simplification

„

Two basic methods

¾ Algebraic manipulation

„ Use Boolean laws to simplify the expression

„ Difficult to use

„ Don’t know if you have the simplified form

¾ Karnaugh map (K-map) method

¾ Karnaugh map (K-map) method

„ Graphical method

„ Easy to use

„ Can be used to simplify logical expressions with a few variables

Algebraic Manipulation

„

Majority function example

A B C + A B C + A B C + A B C =

A B C + A B C + A B C + A B C + A B C + A B C Added extra

„

We can now simplify this expression as

B C + A C + A B

„

A difficult method to use for complex expressions

Karnaugh Map Method

Note the order

Karnaugh Map Method (cont.)

Simplification examples

Karnaugh Map Method (cont.)

First and last columns/rows are adjacent

Karnaugh Map Method (cont.)

Minimal expression depends on groupings

Karnaugh Map Method (cont.)

No redundant groupings

Karnaugh Map Method (cont.)

„

Example

¾ Seven-segment display

¾ Need to select the right LEDs to display a digit

Karnaugh Map Method (cont.)

Karnaugh Map Method (cont.)

Don’t cares simplify the expression a lot

Implementation Using NAND Gates

„

Using NAND gates

¾ Get an equivalent expression

A B + C D = A B + C D

¾ Using de Morgan’s lawU g d o ga a

A B + C D = A B

C D

¾ Can be generalized

„ Majority function

A B + B C + AC = A B

BC

AC

Idea: NAND Gates: Sum-of-Products, NOR Gates: Product-of-Sums

Implementation Using NAND Gates (cont.)

„ Majority function

Introduction to Combinational Circuits

„

Combinational circuits

„ Output depends only on the current inputs

„

Combinational circuits provide a higher level of abstraction

H l i d i d i l it

¾ Help in reducing design complexity

¾ Reduce chip count

„

We look at some useful combinational circuits

Multiplexers

„

Multiplexer

¾ 2ⁿ data inputs

¾ n selection inputs

¾ a single output

4-data input MUX

„

Selection input

determines the

input that should

be connected to

the output

Multiplexers (cont.)

4-data input MUX implementation

Multiplexers (cont.)

MUX implementations

Multiplexers (cont.)

Example chip: 8-to-1 MUX

Multiplexers (cont.)

Efficient implementation: Majority function

Demultiplexers (DeMUX)

„

Demultiplexer

¾ a single input

¾ n selection inputs

¾ 2ⁿ outputs

Decoders

„ Decoder selects one-out-of-N inputs

Decoders (cont.)

Logic function implementation

Comparator

„ Used to implement comparison operators (= , > , < , ≥ , ≤)

Comparator (cont.)

4-bit magnitude comparator chip

A=B: O_x = I_x (x=A<B, A=B, & A>B)

Comparator (cont.)

Serial construction of an 8-bit comparator

1-bit Comparator

x y

x>y x=y x<y

CMP

x y x>y x=y x<y

8-bit comparator

x y

x>y x=y x<y

CMP

x_n>yⁿ xⁿ=yⁿ xⁿ<yⁿ

x y

Adders

„

Half-adder

¾ Adds two bits

„ Produces a sum and carry

¾ Problem: Cannot use it to build larger inputs

F ll dd

„

Full-adder

¾ Adds three 1-bit values

„ Like half-adder, produces a sum and carry

¾ Allows building N-bit adders

„ Simple technique

„ Connect C_out of one adder to C_in of the next

„ These are called ripple-carry adders

Adders (cont.)

Adders (cont.)

A 16-bit ripple-carry adder

Adders (cont.)

„

Ripple-carry adders can be slow

¾ Delay proportional to number of bits

„

Carry lookahead adders

¾ Eliminate the delay of ripple-carry adders

¾ Carry-ins are generated independently

¾ Carry ins are generated independently

„ C₀ = A₀ B₀

„ C₁ = A₀ B₀ A₁ + A₀ B₀ B₁ + A₁ B₁

„

. . .

¾

Requires complex circuits

¾

Usually, a combination carry lookahead and

ripple-carry techniques are used

Programmable Logic Arrays

„

PLAs

¾ Implement sum-of-product expressions

„ No need to simplify the logical expressions

¾ Take N inputs and produce M outputs

Each input represents a logical variable

„ Each input represents a logical variable

„ Each output represents a logical function output

¾ Internally uses

„ An AND array

„ Each AND gate receives 2N inputs

„ N inputs and their complements

„ An OR array

Programmable Logic Arrays (cont.)

A blank PLA with 2 inputs and 2 outputs

Programmable Logic Arrays (cont.)

Implementation examples

Programmable Logic Arrays (cont.)

Simplified notation

1-bit Arithmetic and Logic Unit

Preliminary ALU design

2’s complement

Required 1 is added via C_in

1-bit Arithmetic and Logic Unit (cont.)

Final design

Arithmetic and Logic Unit (cont.)

16-bit ALU

Arithmetic and Logic Unit (cont’d)

4-bit ALU

Introduction to Sequential Circuits

„

Output depends on current as well as past inputs

¾ Depends on the history

¾ Have “memory” property

„

Sequential circuit consists of

C bi i l i i

„ Combinational circuit

„ Feedback circuit

¾ Past input is encoded into a set of state variables

„ Uses feedback (to feed the state variables)

„ Simple feedback

„ Uses flip flops

Introduction (cont.)

Main components of a sequential circuit

Clock Signal

Clock Signal (cont.)

„

Clock serves two distinct purposes

¾ Synchronization point

„ Start of a cycle

„ End of a cycle

Intermediate point at which the clock signal changes

„ Intermediate point at which the clock signal changes levels

¾ Timing information

„ Clock period, ON, and OFF periods

„

Propagation delay

¾ Time required for the output to react to changes in the inputs

Clock Signal (cont.)

SR Latches

„ Can remember a bit

„ Level-sensitive (not edge-sensitive)

A NOR gate implementation of SR latch

SR Latches (cont.)

„ SR latch outputs follow inputs

„ In clocked SR latch, outputs respond at specific instances

¾ Uses a clock signal

D Latches

„ D Latch

¾ Avoids the SR = 11 state

Positive Edge-Triggered D Flip-Flops

„ Edge-sensitive devices

¾ Changes occur either at positive or negative edges

Notation for Latches & Flip-Flops

„ Not strictly followed in the literature

Latches Flip-flops

Low level High level Positive edge Negative edge

Example of Shift Register Using D Flip-Flops

74164 shift Register chip

Memory Design Using D Flip-Flops

Require separate data in and out lines

JK Flip-Flops

JK flip-flop

(master-slave)

J K Qn+1

0 0 Q

0 0 Qn

0 1 0 1 0 1 1 1 Q_n

Examples of D & JK Flip-Flops

Two example chips

D latches JK flip-flops

Example of Shift Register Using JK Flip-Flops

„ Shift Registers

¾ Can shift data left or right with each clock pulse

A 4-bit shift register using JK flip-flops

Example of Counter Using JK Flip-Flops

„

Counters

¾ Easy to build using JK flip-flops

„ Use the JK = 11 to toggle

¾ Binary counters

„ Simple designp g

„ B bits can count from 0 to 2^B−1

„ Ripple counter

„ Increased delay as in ripple-carry adders

„ Delay proportional to the number of bits

„ Synchronous counters

„ Output changes more or less simultaneously

„ Additional cost/complexity

Modulo-8 Binary Ripple Counter Using JK Flip-Flops

LSB

Synchronous Modulo-8 Counter

„

Designed using the following simple rule

¾ Change output if the preceding count bits are 1

„ Q1 changes whenever Q0 = 1

„ Q2 changes whenever Q1Q0 = 11

Example Counters

Sequential Circuit Design

„

Sequential circuit consists of

¾ A combinational circuit that produces output

¾ A feedback circuit

„ We use JK flip-flops for the feedback circuit

Si l t l i JK fli fl

„

Simple counter examples using JK flip-flops

¾ Provides alternative counter designs

¾ We know the output

„ Need to know the input combination that produces this output

„ Use an excitation table

„ Built from the truth table

Sequential Circuit Design (cont.)

Sequential Circuit Design (cont.)

„

Build a design table that consists of

¾ Current state output

¾ Next state output

¾ JK inputs for each flip-flop

Bi t l

„

Binary counter example

¾ 3-bit binary counter

¾ 3 JK flip-flops are needed

¾ Current state and next state outputs are 3 bits each

¾ 3 pairs of JK inputs

Sequential Circuit Design (cont.)

Design table for the binary counter example

Sequential Circuit Design (cont.)

Use K- maps to simplify expression s for JK inputs

Sequential Circuit Design (cont.)

„ Final circuit for the binary counter example

¾ Compare this design with the synchronous counter design

Sequential Circuit Design (cont.)

„ A more general counter design

¾ Does not step in sequence

0→3→5→7→6→0

„ Same design process

„ One significant change

¾ Missing states

„ 1, 2, and 4

„ Use don’t cares for these states

Sequential Circuit Design (cont.)

Design table for the

general counter example

Sequential Circuit Design (cont.)

K-maps to simplify JK input p

expressions

Sequential Circuit Design (cont.)

Final circuit for the general counter example

General Design Process

„

FSM can be used to express the behavior of a sequential circuit

„ Counters are a special case

¾ State transitions are indicated by arrows with labels X/Y X: inputs that cause system state change

„ X: inputs that cause system state change

„ Y: output generated while moving to the next state

„

Look at two examples

¾ Even-parity checker

¾ Pattern recognition

General Design Process (cont.)

„ Even-parity checker

¾ FSM needs to remember one of two facts

„ Number of 1’s is odd or even

„ Need only two states

„ 0 input does not change the state

„ 1 input changes state

„ 1 input changes state

¾ Simple example

„ Complete the design as an exercise

General Design Process (cont.)

„

Pattern recognition example

¾ Outputs 1 whenever the input bit sequence has exactly two 0s in the last three input bits

¾ FSM requires thee special states to during the initial phase

phase

„ S0 − S2

¾ After that we need four states

„ S3: last two bits are 11

„ S4: last two bits are 01

„ S5: last two bits are 10

„ S6: last two bits are 00

General Design Process (cont.)

State diagram for the pattern recognition example

General Design Process (cont.)

„

Steps in the design process

1. Derive FSM

2. State assignment

∗ Assign flip-flop states to the FSM states

Necessary to get an efficient design

∗ Necessary to get an efficient design

3. Design table derivation

∗ Derive a design table corresponding to the assignment in the last step

4. Logical expression derivation

∗ Use K-maps as in our previous examples

5. Implementation

General Design Process (cont.)

„

State assignment

¾ Three heuristics

„ Assign adjacent states for

„ states that have the same next state

„ states that are the next states of the same state

„ states that are the next states of the same state

„ States that have the same output for a given input

¾ For our example

„ Heuristic 1 groupings: (S1, S3, S5)² (S2, S4, S6)²

„ Heuristic 2 groupings: (S1, S2) (S3, S4)³ (S5, S6)³

„ Heuristic 1 groupings: (S4, S5)

General Design Process (cont.)

State table for the pattern

pattern recognition example

General Design Process (cont.)

State assignment K-map for state assignment

General Design Process (cont.)

Design table

General Design Process (cont.)

K-maps for JK inputs

K-map for the output

General Design Process (cont.)

Final implementation