MuxMux ALU

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 5: Computer Architecture slide 1

www.nand2tetris.org

Building a Modern Computer From First Principles

Computer Architecture

Von Neumann machine

(circa 1940)

Arithmetic Logic Unit (ALU)

CPU

Registers

Control Memory

(data + instructions)

Input device

Output device

Andy Grove(and others) ... made it small and fast.

John Von Neumann(and others) ... made it possible

Stored program concept!

Arithmetic Logic Unit (ALU)

CPU

Registers

Control Memory

(data + instructions)

Input device

Output device

Processing logic: fetch-execute cycle

Executing the current instruction involves one or more of the following micro-tasks:

 Have the ^ALUcompute some function out = f (register values)

 Write the ^ALUoutput to selected registers

 As a side-effect of this computation,

figure out which instruction to fetch and execute next.

The Hack chip-set and hardware platform

Elementary logic gates

 Nand

 Not

 And

 Or

 Xor

 Mux

 Dmux

 Not16

 And16

 Or16

 Mux16

 Or8Way

 Mux4Way16

 Mux8Way16

 DMux4Way

 DMux8Way

Combinational chips

 HalfAdder

 FullAdder

 Add16

 Inc16

 ALU

Sequential chips

 DFF

 Bit

 Register

 RAM8

 RAM64

 RAM512

 RAM4K

 RAM16K

 PC

Computer Architecture

 Memory

 CPU

 Computer

done

this lecture

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The Hack computer

Main parts of the Hack computer:

 Instruction memory (ROM)

 Memory (RAM):

• Data memory

• Screen (memory map)

• Keyboard (memory map)

 CPU

 Computer (the logic that holds everything together).



A 16-bit Von Neumann platform



The instruction memoryand the data memoryare physically separate



Screen: 512 rows by 256 columns, black and white



Keyboard: standard



Designed to execute programs written in the Hack machine language



Can be easily built from the chip-set that we built so far in the course

Lecture / construction plan

 Instruction memory

 Memory:

 Data memory

 Screen

 Keyboard

 CPU

 Computer

Instruction memory

out

15 16

address

ROM32K

Function:

 The ^ROMis pre-loaded with a program written in the Hack machine language

 The ^ROMchip always emits a 16-bit number:

out = ROM32K[address]

 This number is interpreted as the current instruction.

Data memory

Low-level (hardware) read/write logic:

To read ^RAM[k^]: set âddressto k, probe ôut To write ^RAM[k^]=x: set âddressto k,

set into x, set loadto 1, run the clock

High-level (OS) read/write logic:

To read RAM[k]: use the OS command out = peek(k) To write ^RAM[k^]=x: use the OS command ^poke(k^,x⁾

peekand ^pokeare OS commands whose implementation should effect the same behavior as the low-level commands

More about peekand pokethis later in the course, when we’ll write the OS.

load

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Lecture / construction plan



^ Instruction memory

 Memory:

 Data memory

 Screen

 Keyboard

 CPU

 Computer



Screen

The Screen chip has a basic RAM chip functionality:

 read logic: out = Screen[address]

 write logic: if load then Screen[address] = in Side effect:

Continuously refreshes a 256 by 512 black-and-white screen device

load

out in

16

15 address 16

Screen

Physical Screen

The bit contents of the Screen chip is called the

“screen memory map”

The simulated 256 by 512 B&W screen

When loaded into the hardware simulator, the built-in Screen.hdlchip opens up a screen window;

the simulator then refreshes this window from the screen memory map several times each second.

Simulated screen:

Screen memory map

How to set the (row,col)pixel of the screen to black or to white:

 Low-level (machine language): Set the col%16 bit of the word found at Screen[row*32+col/16] to ¹or to ⁰ (col/16is integer division)

 High-level: Use the OS command drawPixel(row,col)

 (effects the same operation, discussed later in the course, when we’ll write the OS).

0 1

255 . . .

. . .

0 1 2 3 4 5 6 7 511

0011000000000000 0000000000000000

0000000000000000 0

1

31 .. .

row 0

0001110000000000 0000000000000000

0000000000000000 32

33

63 .. .

row 1

0100100000000000 0000000000000000

0000000000000000 8129

8130

8160 .. .

row 255

. . . . . .

. . . . . .

refresh several times each second Screen

In the Hack platform, the screen is implemented as an 8K 16-bit RAM chip.

Keyboard

Keyboard chip: a single 16-bit register Input: scan-code (16-bit value) of the currently

pressed key, or 0 if no key is pressed Output: same

How to read the keyboard:

 Low-level (hardware): probe the contents of the Keyboardchip

 High-level: use the OS command keyPressed()

 (effects the same operation, discussed later in the course, when we’ll write the OS).

Special keys: The keyboard is implemented as

a built-in Keyboard.hdlchip.

When this java chip is loaded into the simulator, it connects to the regular keyboard and pipes the scan-code of the currently pressed key to the keyboard memory map.

The simulated keyboard enabler button Simulated keyboard:

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Lecture / construction plan



 Memory:

 Data memory

 Screen

 Keyboard

 CPU

 Computer



Memory: conceptual / programmer’s view

Using the memory:

 To record or recall values (e.g. variables, objects, arrays), use the first 16K words of the memory

 To write to the screen (or read the screen), use the next 8K words of the memory

 To read which key is currently pressed, use the next word of the memory.

Data

Screen memory

map Keyboard map

Memory

Keyboard Screen

Memory: physical implementation

Access logic:

 Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part

 Access to any address from 16,384 to 24,575 results in accessing the Screenchip-part

 Access to address 24,576 results in accessing the ^keyboardchip-part

 Access to any other address is invalid.

load

out in

16

15

16 RAM16K

(16K mem. chip)

address 0

16383

Screen (8K mem. chip) 16384

24575

24576 Keyboard (one register) Memory

Keyboard Screen

The Memory chip is essentially a package that integrates the three chip- parts RAM16K, Screen, and Keyboard into a single, contiguous address space.

This packaging effects the programmer’s view of the memory, as well as the necessary I/O side-effects.

Lecture / construction plan



 Memory:

 Data memory

 Screen

 Keyboard

 CPU

 Computer

 



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CPU

instruction inM

16

1

15

16 outM

16

writeM

addressM

pc reset

1

CPU

to data memory

to instruction memory from

data memory

from instruction memory

CPU internal components (invisible in this chip diagram): ALUand 3 registers: A, D, PC CPU execute logic:

The CPU executes the instructionaccording to the Hack language specification:

 The ^Dand ^Avalues, if they appear in the instruction, are read from (or written to) the respective CPU-resident registers

 The Mvalue, if there is one in the instruction’s RHS, is read from inM

 If the instruction’s LHS includes M, then the ALU output is placed in outM, the value of the CPU-resident Aregister is placed in addressM, and writeMis asserted.

a Hack machine language instruction like M=D+M, stated as a 16-bit value

CPU

instruction inM

16

1

15

16 outM

16

writeM

addressM

pc reset

1

CPU

to data memory

to instruction memory from

data memory

from instruction memory

CPU internal components (invisible in this chip diagram): ALUand 3 registers: A, D, PC CPU fetch logic:

Recall that:

1.the instructionmay include a jump directive (expressed as non-zero jump bits) 2.the ALUemits two control bits, indicating if the ALUoutput is zero or less than zero If reset==0:the CPU uses this information (the jump bits and the ALU control bits)as follows:

If there should be a jump, the PCis set to the value of A; else, PCis set to PC+1 If reset==1:the PCis set to 0. (restarting the computer)

a Hack machine language instruction like M=D+M, stated as a 16-bit value

The C-instruction revisited

jum p dest

com p

1 1 1 a c 1 c 2 c 3 c 4 c 5 c 6 d 1 d 2 d 3 j 1 j 2 j 3

binary:

dest = com p; jum p

Execute logic:

 Decode

 Execute

Fetch logic:

If there should be a jump, set ^PCto ^A

else set PCto PC+1

ALU

Mux

D

Mux

reset inM

addressM

pc outM

instruction A/M

decode

C C

C

C D

A

PC C C

A A A

M ALU output

writeM

C C

jum p dest

com p

1 1 1 a c 1 c 2 c 3 c 4 c 5 c 6 d 1 d 2 d 3 j 1 j 2 j 3

binary:

dest = com p; jum p

CPU

implementation

Cycle:

 Execute

 Fetch

Resetting the computer:

Set resetto 1, then set it to 0. Chip diagram:

Includes most of the CPU’s execution logic

The CPU’s control logic is hinted: each circled “c”

represents one or more control bits, taken from the instruction

The “decode”

bar does not represent a chip, but rather indicates that the instruction bits are decoded somehow.

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Lecture / construction plan



 Memory:

 Data memory

 Screen

 Keyboard

 CPU

 Computer



Computer

-on-a-chip

interface

Computer reset

Keyboard Screen

Computer

-on-a-chip

implementation

Data Memory

(Memory) instruction

CPU

Instruction Memory

(ROM32K)

inM

outM addressM writeM

pc

reset CHIP Computer {

IN reset;

PARTS:

// implementation missing }

Implementation:

Simple, the chip-parts do all the hard work.

Perspective: from here to a “real” computer



Caching



More I/O units



Special-purpose processors (I/O, graphics, communications, …)



Multi-core / parallelism



Efficiency



Energy consumption considerations



MuxMux ALU

www.nand2tetris.org

Computer Architecture

Von Neumann machine

Processing logic: fetch-execute cycle

The Hack chip-set and hardware platform

The Hack computer













Lecture / construction plan

Instruction memory

Data memory

Low-level (hardware) read/write logic:

High-level (OS) read/write logic:

Lecture / construction plan





Screen

Screen memory map

Keyboard

Lecture / construction plan









Memory: conceptual / programmer’s view

Memory: physical implementation

Lecture / construction plan



 





CPU

CPU

The C-instruction revisited

CPU

Lecture / construction plan







Computer

interface

Computer

implementation

Perspective: from here to a “real” computer

Caching

More I/O units

Special-purpose processors (I/O, graphics, communications, …)

Multi-core / parallelism

Efficiency

Energy consumption considerations

And more ...