PAPER
An Ultra-Low Power Variable-Resolution Sigma-Delta Modulator
for Signals Acquisition of Biomedical Instrument
Chen-Ming HSU†, Nonmember, Tzong Chee YO†, Student Member, and Ching-Hsing LUO†a), Member
SUMMARY In this paper, an ultra-low power variable-resolution sigma-delta (Σ∆) modulator for biomedical application is presented. The resolution of proposed modulator can be adjusted by switching its sampling frequency and architecture. The architecture is switched between second-order single-loop modulator and fourth-second-order cascaded second stage noise shaped modulator to reach different resolution requirement. The proposed sigma-delta modulator is implemented by single phase integrators based on a fully differential switched-capacitor circuit. The digital cancellation logic is embedded in the chip so that it would easily be integrated with biomedical instrument for effective acquisition. Experimental results of the proposed variable-resolutionΣ∆ modulator fabricated in standard CMOS 0.18µm technology confirm the expected specifications from 65 dB signal-to-noise distortion to 96 dB with 1 kHz bandwidth and power consumption range from 48µW to 360 µW with a 1.8 V battery supply.
key words: sigma-delta modulator, variable-resolution, ultra low power, biomedical
1. Introduction
With the rapid advancement of the microelectronics pro-cess in the recent years, low power integrated circuits for biomedical application have been widely used to acquire or analyze the vital physiological signals [1], [2]. Differ-ent biomedical signals are with differDiffer-ent signal bandwidths from dc to 10 kHz and amplitudes from a few micro-volts to several hundreds of millivolts [3]. Therefore several medical portable commercial devices are only oriented for specific biomedical signals and are not suitable for other bio-signals. These systems that comprise a low-noise programmable gain amplifier, an anti-aliasing filter and a Nyquist-rate ADC that introduce performance limitations such as limit resolu-tion and fixed signal bandwidth that are determined by the cutoff frequency of anti-aliasing filter [4]. The high resolu-tion analog-to-digital converter (ADC) with unfixed signal bandwidth becomes an essential component in medical de-vices for acquisition of several biomedical signals, besides; the frequency of physiological signal is low thatΣ∆ modu-lator implemented by switch capacitor circuit does not need an additional anti-aliasing filter; with this property,Σ∆ mod-ulator is the appropriate ADC structure for biomedical ap-plications [4]–[6]. Figure 1 is the block diagrams of typical medical measurement devices and the one implemented by theΣ∆ modulator.
Low power consumption is the other critical point in
Manuscript received November 30, 2006. Manuscript revised March 14, 2007.
†The authors are with the Wireless Mixed Biochip Laboratory,
EE, NCKU, Tainan 70146, Taiwan. a) E-mail: robinluo@mail.ncku.edu.tw
DOI: 10.1093/ietele/e90–c.9.1823
Fig. 1 Block diagram of typical medical instrument and medical instrument implemented by sigma-delta modulator.
portable medical instruments for monitoring applications [7]. But high resolution and low power consumption, as a trade off, would not exist simultaneously. In biomedical monitoring application, the signals are steady in usual time that needn’t high resolution ADC to acquire, but when dis-eases happen in human body, the signals become unsteady and varying acutely. These unsteady signals with drastically variation are usually important than others in diagnosis and need higher resolution ADC for accurate analysis that can help doctors diagnose immediately. The ADC which can adjust its resolution in response to the biomedical signals’ condition should be implemented in medical portable instru-ments for increasing power efficiency.
The proposedΣ∆ modulator in this paper is suitable for battery-powered portable medical equipment such as, trooculogram (EOG), electroencephalogram (EEG), elec-trocardiogram (ECG) and eletromyogram (EMG) but not for axon action potential (1 kHz to 10 kHz bandwidth). EMG is the most challenging biomedical signal in design because it has the highest frequency (1 kHz) and the widest amplitude range (10−1to 10−5volt) of these signals [2]. The signal-to-noise distortion ratio (SNDR) ofΣ∆ modulator can be modi-fied by the oversampling ratio and the order of the modulator [8]. In order to adjust the resolution, the architecture of pre-sentedΣ∆ modulator can be switched between the second-order and the fourth-second-order modulator and the oversampling ratio can be switched between 64 and 256. Furthermore, the single phase integrator technique is employed to improve the dynamic performance. In this technique, the integration can be completed twice in a clock period that can reduce power dissipation by 50% compared with conventional switched capacitor integrator [4], [9]. The modulator has the embed-ded digital canceling logic to relax the digital circuit com-plexity and can be easily integrated with commercial dig-ital filter chip to implement the medical equipment. The measured SNDR in a bandwidth of 1 kHz is about 65 dB Copyright c 2007 The Institute of Electronics, Information and Communication Engineers
product that adopts two different ADC with different speci-fications or one with high specification and high power con-sumption, therefore it can significantly reduce the chip area and save power consumption in the biomedical application. The proposed modulator architecture is based on the 2+2 fourth-order multi-stage noise shaped (MASH)Σ∆ modula-tor comprises four integramodula-tors, two comparamodula-tors, two one-bit digital to analog converters (DAC), a clock generator with divider and a digital canceling logic, as presented in Fig. 2. The components of 2+2 Σ∆ modulator are all turned on with higher sampling rate (frequency divider is turned off) that in-duces higher resolution for advanced analysis when needed. Normally, the first stage components are turned off to save power consumption and biomedical signal is converted only by the second stage 2nd order Σ∆ modulator with lower sampling rate (frequency divider is turned on). The second-orderΣ∆ modulator is absolutely stable because it has only two poles and proposed 2− 2 MASH Σ∆ modulator also has the advantage that is suitable for unsteady biomedical signals in high resolution application [10].
In the high orderΣ∆ modulator design, the capacitor value of the first switch-capacitor circuit should be large
Fig. 2 Block diagram of proposed sigma-delta modulator in different operation mode.
nique can improve the dynamic performance and, simulta-neously, reduce the circuit complexity, substrate noise and area [4]. Figure 3 shows the proposed modulator topology using single phase integrator technique. In phase 1, the first integrator is turned on for integration while the second one is turned off. In phase 2, the first integrator is turned off while the second is turned on that achieves the second-order Σ∆ modulator. The two integrators are turned on and off in different phase that reduce 50% power consumption of in-tegrators compared with traditionalΣ∆ modulator. The op-erational amplifier in first integrator consumes more power than the others to drive large capacitor and the 2nd order Σ∆ modulator implemented by single operational amplifier would consume more power (it integrates twice in the same component) [4]. The method for decreasing power of the first stage 2nd orderΣ∆ modulator is by using two differ-ent operational amplifiers to replace the single one that can save additional power in phase 2 by low power integrator. Although the chip area would be increased doubled, the low power consumption is the most critical issue in biomedical applications.
The different gain parameters (a1–d2) are adjusted to the forward and feedback loops respectively to reduce the possibility of saturation of the integrator, thus ensuring the ADC linearity of among input signal amplitude range. The gain parameters except c1 are all 0.5 and c1, e1 are 2; they are the finest coefficients for 2 − 2 MASH Σ∆ mod-ulator topology with optimum performance [12]. The cir-cuits in proposedΣ∆ modulator are all fully differential ar-chitectures with following advantages: double input voltage swing, common-mode noise elimination, charge injection effect reduce and even order harmonic distortion extermi-nation [13].
The implemented integrator is the most critical block inΣ∆ modulator because it directly influences the perfor-mance by its non-ideal characteristics. Besides the single phase integrator technique, the correlated double sampling (CDS) integrators that employ switch-capacitor technology have high precision and low flicker noise [14]. Figure 4 is the differential CDS circuit diagram. The CDS integra-tor can eliminate the offset voltage of operational amplifier (OPAMP) or operational transconductance amplifier by its double sampling on additional capacitor Cos. TheΣ∆ mod-ulator implemented by single phase CDS integrators can
re-Fig. 3 Proposed sigma-delta modulator with digital canceling logic topology.
Fig. 4 Schematic diagram and timing of correlated double sampling integrator.
duce not only layout matching error but also power con-sumption.
2.3 The Implemented OPAMP
In order to reduce the integrator non-ideal characteristics caused by operational amplifier for high resolution appli-cations, the OPAMP should be designed toward high gain, high slew rate and high gain bandwidth [15]. The frequency of biomedical signals isn’t high compared with other appli-cations, although the sampling frequency ratio ofΣ∆ mod-ulator is higher than other Nyquist-rate ADCs, the OPAMP requirement for gain bandwidth and slew rate aren’t very tight. For high gain and applicable input voltage swing, the two-stage OPAMP with ON/OFF switch is employed to im-plement single phase CDS integrator. In fully differential two-stage OPAMP design, it needs two common mode feed-backs (CMFB) in both stages to fix the output node’s voltage level. Figure 5 presents the circuit diagrams of two-stage OPAMP with self CMFB and output stage CMFB circuit. The cross-coupled circuit (M51, M52, M61, and M62) is the self-CMFB that can fix the first stage common mode level by detecting the first stage output. The CMFB circuit of output-stage can be implemented by the amplifier based ap-proach or switched-capacitor-common mode feedback (SC-CMFB). The SC-CMFB is the most popular method due to
Fig. 5 Circuit diagram of proposed two-stage OPAMP and CMFB circuit.
its simplicity and low power consumption. The SC-CMFB circuit controls the current sources in the output stage of OPAMP. In this design, the feedback signal is lead to the gates of M12 and M10 in the OPAMP. It builds a negative feedback to fix the output DC operating point of OPAMP at the common mode voltage (Vdd/2).
The switch that control operational amplifier ON/OFF is implemented in the bias circuit (Vbias) and the opera-tional amplifier is turned off by dropping its bias reference voltage to Vdd. This switch is used to change the structure of proposedΣ∆ modulator and turn off operational amplifier in single phase CDS integrator.
2.4 Comparator and D/A Feedback Circuit
The comparator is the other essential component ofΣ∆ mod-ulator ADC. Dissimilar to Nyquist ADC, the comparator
Fig. 6 Circuit diagram of regenerative comparator and one bit DAC.
(a)
(b)
Fig. 7 (a) Schematic of clock generator, (b) nonoverlaping clock output.
Fig. 8 The circuit diagrams of D-Flip-Flop and full-adder.
ing circuit’s clock for Boolean operation and delay clock. Figure 7(b) is the waveform of these clocks. The clockΦ 1lat is used to drive the quantizer and it could create delay compared with integrator clock to acquire the correct signal from integrator.
2.6 Digital Canceling Logic and Frequency Divider In MASHΣ∆ modulator, it needs an additional digital can-celing logic to recover the signals. The conventional digital canceling circuit is realized by software or off-chip micro-processor in biomedical applications. However, these dig-ital blocks could be easily designed by simple logics. The basic components of digital canceling logic are adder and delay cell (it is shown in Fig. 3) that could be implemented by D-Flip-Flop and full-adder. Figure 8 shows D-Flip-Flop and full-adder designed by NAND gates which are used in this proposedΣ∆ modulator. The frequency divider with 2’s multiple divisors can be implemented by simple cascade D-Flip-Flop. In this work, the oversampling ratio is switched between 64 and 256 that need two D-Flip-Flops to accom-plish. The digital canceling logic is turned off by setting its clock equal to zero in low-resolution mode.
3. Simulation and Experimental Results
The proposed variable-resolutionΣ∆ modulator chips have been fabricated in a 0.18µm six-metal one poly CMOS tech-nology offered by Taiwan Semiconductor Manufacturing Co. (TSMC). Figure 9 presents the microphotograph of the
Table 1 Simulation results of 2-stage OPAMP of proposed modulator.
Fig. 10 Measurement output spectrum of proposed sigma-delta modulator in high resolution mode.
chip, whose core die area size is around 0.32 mm2. The sim-ulation results are obtained by Hspice simulator. The simu-lation results of proposed two-stage OPAMP are described in Table 1. The OPAMP of first integrator in first stage is designed toward higher specification than others in order to reduce the noise of first stage in high resolutionΣ∆ modu-lator [13]. The simulated SNDR of proposed modumodu-lator is 98.2 dB (ENOB=16 bit) in forth-order MASH Σ∆ modula-tor with 256 oversampling ratio and 68 dB (ENOB=11 bit) in the second-orderΣ∆ modulator with 64 oversampling ra-tio.
The proposed Σ∆ modulator is measured by using a high bandwidth oscilloscope (LECROY 6030A). The recorded pulse density modulated outputs are further ana-lyzed using MATLAB to obtain their power spectrum. Fig-ure 10 demonstrates the 4th order sigma-delta modulator output spectrum with FFT analysis and Fig. 11 demonstrates the 2nd order sigma-delta modulator output spectrum with FFT analysis. They show a SNDR of 96.8 dB and 65.68 dB, where the applied input signal frequency is 500 Hz and the calculation of DR, SNR and SNDR is based on 1 kHz band-width at the 128 kHz and 512 kHz sampling frequency. The measured power consumption is 48µW under normal
con-Fig. 11 Measurement output spectrum of proposed sigma-delta modulator in normal resolution mode.
Fig. 12 Proposed sigma-delta modulator SNDR versus various input signal power in different modes.
Table 2 Comparison of proposed sigma-delta modulator in different modes.
dition and 360µW under high resolution condition. The bandwidth of proposed modulator is suitable for most med-ical signals such as, EOG, EEG, ECG and EMG. The
max-Fig. 13 The EEG signal acquired by the proposed sigma-delta modulator and software digital filter.
Fig. 14 The EOG signal acquired by the proposed sigma-delta modulator and software digital filter.
imum achieved resolution (16-bit) exceeds the requirement (10-bit) of biomedical applications and could be used for high advanced unknown biomedical analysis or acquisition of several biomedical signals with the same biomedical am-plifier. The resolution of proposed modulator could be ad-justed only by switching the stage of modulator in standard sampling rate that is called medium resolution mode in this work. Figure 12 presents the measured SNDR versus vari-ous input signal power under the same testing configuration in three different resolution modes. The experimental re-sults of proposedΣ∆ modulator with previous work [6] are summarized in Table 2.
In order to ensure the proposed modulator practicabil-ity, the real amplified lead I ECG and EEG signals are re-garded as input signals. The voltage range of ECG is am-plified to the 0.4 Vp-p to avoid the circuit saturation and the EEG signal is processed by the same biomedical amplifier. Figure 13 and Fig. 14 are the output ECG and EEG acquired by proposed chip in high resolution mode and software digi-tal filter. It is apparent that the P, Q, R, S waveforms of ECG and EEGβ wave, EOG induced by blink of EEG can be ac-curately acquired and showed by proposedΣ∆ modulator.
ational conditions. The biomedical signals EEG, ECG can be accurately acquired by proposed modulator. It is one of the best solutions for efficient acquisition in medical instru-ments that can be used in monitoring and high resolution analysis applications.
Acknowledgments
Financial support received from the Ministry of Educa-tion (Ex: HH94-A13) and Excellence University project of NCKU, Taiwan and also basic supports from NCKU, Tai-wan, Republic of China is gratefully acknowledged.
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Chen-Ming Hsu was born in Taipei, Tai-wan, in 1979. He received the B.S. and M.S. degrees in Electrical Engineering from National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. He is now pursu-ing the Ph.D. degree in Wireless Mixed Biochip Lab at National Cheng Kung University. His re-search field includes RF IC, biomedical signal processing circuit and biotelemetry chip design.
Tzong-Chee Yo received the B.S. and M.S. degrees in Electrical Engineering from National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. He is now pursu-ing the Ph.D. degree in Wireless Mixed Biochip Lab at National Cheng Kung University. His research fields include wireless power transmis-sion medical devices, rectenna, battery recharg-ing and Labview programmrecharg-ing language.
Ching-Hsing Luo received the B.S. de-gree in electrophysics from the National Chaio Tung University and the M.S. degrees in electri-cal engineering from the National Taiwan Uni-versity in 1982 and in biomedical engineering from the Johns Hopkins University in 1987. He received the Ph.D. degree in biomedical engi-neering from the Case Western Reserve Uni-versity in 1991. He is a full professor in the Department of Electrical Engineering, National Cheng Kung University in Taiwan since 1996. His research interests include biomedical instrumentation-on-a-chip, assis-tive tool implementation, cell modeling, signal processing, home automata, RFIC, gene chip, and quality engineering.
