ISQED 2018: Program
Rev. 1, 12/27/2017
SESSION 1A
Tuesday March 13 Design Verification and Test
Chair: Vinod Viswanath, Real Intent Co-Chair: Sreejit Chakravarty, Intel
10:00AM 1A.1
Concolic Testing of SystemC Designs
Bin Lin1, Kai Cong2, Zhenkun Yang2, Zhigang Liao3, Tao Zhan4, Christopher Havlicek1, Fei Xie1
1Portland State University, 2Intel Corporation, 3Virtual Device Technologies LLC, 4Northwestern Polytechnical University
10:20AM 1A.2
A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators Aydin Dirican, Cagatay Ozmen, Martin Margala
University of Massachusetts Lowell
10:40AM 1A.3
Test Set Identification for Improved Delay Defect Coverage in the Presence of Statistical Delays Pavan Kumar Javvaji1, Basim Shanyour2, Spyros Tragoudas1
1Southern Illinois University Carbondale, 2Southern Illinois University- Carbondale
11:00AM 1A.4
Augmenting ESD and EOS Physical Analysis with Per Pin ESD and Leakage DFT Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono
Intel Corporation
SESSION 1B
Tuesday March 13
System-level Design and Methodologies (SDM)
Chair: Rajesh Berigei, tbd
Co-Chair: Shiyan Hu, Michigan Technological Univ
10:00AM 1B.1
Hybrid-Comp: A Criticality-Aware Compressed Cache Architecture Amin Jadidi1, Mohammad Arjomand2, Mahmut Kandemir1, Chita Das1
1Pennsylvania State University, 2Georgia Institute of technology
10:20AM 1B.2
Energy-Optimal Dynamic Voltage Scaling in Multicore Platforms with Reconfigurable Power Distribution Network
Juyeon Kim1 and Taewhan Kim2
1Samsung Electronics, 2Seoul National University
10:40AM 1B.3
Optimizing Energy in a DRAM based Hybrid Cache Jiacong He1 and Joseph Callenes-Sloan2
1University of Texas at Dallas, 2California Polytechnic State University
11:00AM 1B.4
Program Acceleration Using Nearest Distance Associative Search Mohsen Imani1, Daniel Peroni2, Tajana Rosing3
1University of California San Diego, 2University of California at San Diego, 3UCSD
SESSION 1C
Tuesday March 13
Emerging Logic and Memory Technologies in IoT and Neuromorphic Architectures
Chair: Shih-Hung Chen, IMEC
Co-Chair: Jayita Das, Intel Corporation
10:00AM 1C.1
Synthesis of Normally-Off Boolean Circuits: An Evolutionary Optimization Approach Utilizing Spintronic Devices
Arman Roohi, Ramtin Zand, Ronald F DeMara
Computer Systems and Architecture Laboratory, Department of EECS, University of Central Florida
10:20AM 1C.2
LUPIS : Latch-Up Based Ultra Efficient Processing-in-Memory System Joonseop Sim1, Mohsen Imani1, Woojin Choi1, Yeseong Kim2, Tajana Rosing1
1UCSD, 2University of California San Diego
10:40AM 1C.3
Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminology
Zoha Pajouhi Intel Corporation
11:00AM 1C.4
A Bi-Memristor Synapse with Spike-Timing-Dependent Plasticity for On-Chip Learning in Memristive Neuromorphic Systems
Sagarvarma Sayyaparaju, Sherif Amer, Garrett S. Rose The University of Tennessee, Knoxville
SESSION 2A
Tuesday March 13
Automated Analog and Digital Circuit Optimization Chair: Srini Krishnamoorthy, Advanced Micro Devices (AMD)
Co-Chair: Srinivas Katkoori, University of South Florida (
3:45PM 2A.1
Recognition of Regular Layout Structures Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin Yuan Ze University
4:05PM 2A.2
A Simplified Methodology for Complex Analog Module Layout Generation Pradeep Chawda
Texas Instruments
4:25PM 2A.3
Process Variation Aware D-Flip-Flop Design using Regression Analysis Shinichi Nishizawa1 and Hidetoshi Onodera2
1Saitama University, 2Kyoto University
4:45PM 2A.4
Clock Buffer and Flip-flop Co-optimization for Reducing Peak Current Noise Joohan Kim1 and Taewhan Kim2
1Samsung Electronics, 2Seoul National University
5:05PM 2A.5
Parasitic-Aware gm/ID-Based Many-Objective Analog/RF Circuit Sizing Tuotian Liao1 and Lihong Zhang2
1Memorial University of Newfoundland, 2Memorial University of Newfoundlan
SESSION 2B
Tuesday March 13
System-level Design and Methodologies (SDM) Chair: Rajesh Berigei, tbd
Co-Chair: Shiyan Hu, Michigan Technological Univ
3:45PM 2B.1
A Loop Structure Optimization targeting High-level Synthesis of Fast Number Theoretic Transform
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa Waseda University
4:05PM 2B.2
A 4-PAM Interconnect in Network-on-Chip for High-Throughput and Latency-Sensitive Applications
Ahmad Mansour1, Ahmed El-Naggar1, Bassma Alabassy2, Mostafa Khamis2, Ahmed Shalaby3
1EE Department, Alexandria University, Egypt., 2Mentor Graphics, 3Faculty of Computers and Informatics, Benha University, Egypt
4:25PM 2B.3
Comparative Study and Prediction Modeling of Photonic Ring Network on Chip Architectures Sara Karimi1 and Jelena Trajkovic2
1M.Sc Concordia University, 2Assistant Professor in Concordia University
4:45PM 2B.4
Power and Performance Aware Memory-Controller Voting Mechanism
Milena Vratonjic1, Harmander Singh2, Gautam Kumar3, Roumi Mohamed3, Ashish Bajaj3, Ken Gainey1
1Qualcomm Atheros, Inc., 2Qualcomm Technologies Inc., 3Qualcomm India Private Limited
5:05PM 2B.5
PDA-HyPAR: Path-Diversity-Aware Hybrid Planar Adaptive Routing Algorithm for 3D NoCs Jindun Dai1, Renjie Li2, Xin Jiang3, Takahiro Watanabe4
1Shanghai Jiao Tong University, 2The Graduate School of Information Production and Systems, Waseda University, 3Graduate School of Information Production and Systems, Waseda University, Japan, 4The Graduate School of Information, Production and Systems Of Waseda University, Japan
SESSION P
Tuesday March 13
Posters Chair: Swaroop Ghosh, PSU
5:55PM P1
Network on Interconnect Fabric
Boris Vaisband, Adeel Bajwa, Subramanian Iyer University of California, Los Angeles
5:55PM P2
Machine Learning-based aging compensation to enable safety-critical autonomous driving products
souhir mhira STmicroelectronics
5:55PM P3
Efficient K Nearest Neighbor Algorithm Implementations for Throughput-Oriented Architectures
Jihyun Ryoo1, Meena Arunachalam2, Rahul Khanna2, Mahmut Kandemir1
1Pennsylvania State University, 2Intel
5:55PM P4
Body-Biasing Assisted Vmin Optimization for 5nm-Node Multi-Vt FD-SOI 6T-SRAM Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang
National Cheng Kung University
5:55PM P5
Measuring the effectiveness of ISO26262 compliant Self Test Library Frederico Pratas1, Thomas Dedes2, Andrew Webber3, Itai Yarom4
1Researcher, 2Software engineer, 3Safety Manager, 4Solution Engineer
5:55PM P6
An Online Framework for Diagnosis of Multiple Defects in Scan Chains
Sarmad Tanwir1, Michael Hsiao1, Loganathan Lingappan2
1Virginia Tech, 2Intel Corporation
5:55PM P7
Routing at Compile Time
Chun-Xun Lin, Tsung-Wei Huang, Martin Wong University of Illinois at Urbana-Champaign
5:55PM P8
Uncertainty Aware Mapping of Embedded Systems for Reliability, Performance, and Energy Wenkai Guan, Milad Ghorbani Moghaddam, Cristinel Ababei
Marquette University
5:55PM P9
On the Write Energy of Non-Volatile Resistive Crossbar Arrays With Selectors Albert Ciprut and Eby G. Friedman
University of Rochester
5:55PM P10
A Modified Method of Logical Effort for FinFET Circuits Considering Impact of Fin-Extension Effects
Archana Pandey1, Pitul Garg2, Shobhit Tyagi2, Rajeev Ranjan3, Anand Bulusu2
1Indian Institute of Technology Roorkee, 2IIT Roorkee, 3Samsung Electronics, Republic of Korea
5:55PM P11
Generic System-Level Modeling and Optimization for Beyond CMOS Device Applications Victor Huang, Chenyun Pan, Azad Naeemi
Georgia Institute of Technology
5:55PM P12
Terahertz Travelling Wave Amplifier Design using Ballistic Deflection Transistor Huan Wang1, Jean-François Millithaler1, Ronald Knepper2, Martin Margala1
1University of Massachusetts, 2Boston University
5:55PM P13
Reliable Memory PUF Design for Low-Power Applications
Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Tahoori Karlsruhe Institute of Technology
5:55PM P14
A High Throughput/Area Optimized Elliptic Curve Crypto Processor Implementation on FPGA Malik Imran1, Atif Jafri2, Muhammad Rashid3
1Abasyn University Islamabad, 2Bahria University Islamabad, 3Umm Al-Qura University, Makkah, Saudi Arabia
5:55PM P15
An ESD Transient Clamp with 494 pA Leakage Current in GP 65 nm CMOS Technology Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
University of Waterloo
5:55PM P16
Enhancing Circuit Operation using Analog Floating Gates
Ujas Patel1, Sai Govinda Rao Nimmalapudi1, Harvey Stiegler1, Andrew Marshall1, Keith Jarreau2
1University of Texas at Dallas, 2Texas Instruments Incorporated
5:55PM P17
An Automated Flow for Design Validation of Switched Mode Power Supply Pradeep Chawda1 and Srikrishna Srinivasan2
1Texas Instruments, 2Texas Instruments Inc
5:55PM P18
Dynamic NoC Platform for Varied Application Needs
Sidhartha Sankar Rout1, Hemanta Kumar Mondal2, Rohan Juneja1, Sri Harsha Gade1, Sujay Deb2
1Indraprastha Institute of Information Technology, Delhi, 2IIIT Delhi
5:55PM P19
Multi- Application Mapping and Scheduling Tasks on Network on Chip
NARESH REDDY Intel
SESSION 3A.1
Wednesday March 14 Design Verification and Test
Chair: Vinod Viswanath, Real Intent Co-Chair: Sreejit Chakravarty, Intel
10:00AM 3A.1.1
A Technique to Aggregate Classes of Analog Fault Diagnostic Data Based on Association Rule Mining
Ruslan Dautov1 and Sergey Mosin2
1Shenzhen University, 2Kazan Federal University
10:20AM 3A.1.2
Extracting Hardware Assertions Including Word-Level Relations over Multiple Clock Cycles Mami Miyamoto and Kiyoharu Hamaguchi
Shimane University
SESSION 3A.2
Wednesday March 14
Automated Analog and Digital Circuit Optimization
Chair: Srini Krishnamoorthy, Advanced Micro Devices (AMD) Co-Chair: Srinivas Katkoori, University of South Florida (
10:40AM 3A.2.1
A Study on NBTI-induced Delay Degradation Considering Stress Frequency Dependence
Zuitoku Shin1, Shumpei Morita1, Song Bian1, Michihiro Shintani2, Masayuki Hiromoto1, Takashi Sato1
1Kyoto University, 2Nara Institute of Science and Technology
11:00AM 3A.2.2
Verification Methodology to Guarantee Low Routing Resistance to Well Taps
MOHAMMED FAKHRUDDIN, Kuok-Khian Lo, James Karp, Michael Hart, Min-Hsing Chen Xilinx, Inc.
SESSION 3B
Wednesday March 14
High Performance / Low Power Logic Design
Chair: Kurt Schwartz, Texas Instruments, Inc
Co-Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology
10:00AM 3B.1
Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems Przemyslaw Mroszczyk and Vasilis Pavlidis
The University of Manchester
10:20AM 3B.2
Back-Bias Generator for Post-Fabrication Threshold Voltage Tuning Applications in 22nm FD- SOI Process
Arif Siddiqi, Navneet Jain, Mahbub Rashed Global Foundries
10:40AM 3B.3
Logic Based Row Redundancy Technique Designed in 7nm FINFET Technology for Embedded SRAMs
Vivek Nautiyal, Nishant Nukala, Fakhruddinali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade Kinkade
ARM
11:00AM 3B.4
A 125mV 2ns-Access-Time 16Kb SRAM Design based on a 6T Hybrid TFET-FinFET Cell Hassan Afzali-Kusha1, Alireza Shafaei Bejestan2, Massoud Pedram1
1USC, 2University of Southern California
SESSION 3C
Wednesday March 14 IoT & Smart Sensors
Chair: Pradeep Chawda, Texas Instruments Incorporated Co-Chair: Abishai Daniel, Intel
10:00AM 3C.1
IoT Gateways - Living on the Edge Alfred Gomes
Axiomware
10:20AM 3C.2
New AC Resistance Calculation of Printed Spiral Coils for Wireless Power Transfer Yuhua Cheng, Guoxiong Chen, Gaofeng Wang
Hangzhou Dianzi University
10:40AM 3C.3
An Automated Design Flow for Synthesis of Optimal Multi-layer Multi-shape PCB Coils for Inductive Sensing Applications
Pradeep Chawda Texas Instruments
11:00AM 3C.4
When "things" get older - Exploring Circuit Aging in IoT Applications
Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea Stan University of Virginia
SESSION 4A.1
Wednesday March 14
Design Technology Co-Optimization (DTCO)
Chair: Fedor Pikus, Mentor Graphics, Inc Co-Chair: Rajan Beera, Pall Corporation
11:40AM 4A.1.1
A systematic study of hotspot detection in physical designs using machine learning Piyush Verma1, Robert Pack2, Sriram Madhavan2
1Globalfoundries Inc., 2Globalfoundaries
SESSION 4A.2
Wednesday March 14
Machine Learning on Conventional and Emerging Platforms
Chair: Hai (Helen) Li, Duke University Co-Chair: Yang (Cindy) Yi, Virginia Tech
12:00PM 4A.2.1
A Deep Learning Based Approach for Analog Hardware Implementation of Delayed Feedback Reservoir Computing System
Jialing Li and Yang Yi Virginia Tech
12:20PM 4A.2.2
An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional
Neural Networks using Stochastic Computing
Xiaolong Ma1, Yipeng Zhang1, Geng Yuan1, Ao Ren1, Zhe Li1, Jie Han2, Jingtong Hu3, Yanzhi Wang1
1Syracuse University, 2university of alberta, 3University of Pittsburgh
12:40PM 4A.2.3
A Path to Energy Efficient Spiking Delayed Feedback Reservoir Computing for Brain-inspired Neuromorphic Processors
Kang Jun Bai and Yang Yi
Department of Electrical and Computer Engineering, Virginia Tech
SESSION 4B
Wednesday March 14
High Performance / Low Power Logic Design
Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology Co-Chair: Raviprakash Rao, Texas Instruments, Inc
11:40AM 4B.1
Low Power Latch Based Design with Smart Retiming
Kamlesh Singh1, Hailong Jiao2, Jos Huisken3, Hamed Fatemi4, Josè Pineda de Gyvez4
1Eindhoven University of Technology (TU/e), 2Peking University Shenzhen Graduate School
Shenzhen, China, 3Eindhoven University of Technology, The Netherlands, 4NXP Semiconductors, The Netherlands
12:00PM 4B.2
Parallel implementation of finite state machines for reducing the latency of stochastic computing Cong Ma and David Lilja
University of Minnesota
12:20PM 4B.3
A Post-Silicon Hold Time Closure Technique using Data-Path Tunable-Buffers for Variation- Tolerance in Sub-threshold Designs
Divya Akella Kamakshi1, Xinfei Guo1, Harsh Patel1, Mircea Stan2, Benton Calhoun1
1University of Virginia, 2
12:40PM 4B.4
A Low-Power Configurable Adder for Approximate Applications Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Fukuoka University
SESSION 4C
Wednesday March 14 IoT & Smart Sensors
Chair: Pradeep Chawda, Texas Instruments Incorporated Co-Chair: Abishai Daniel, Intel
11:40AM 4C.1
Mathematical Derivation, Circuits Design and Clinical Experiments of Measuring Blood Flow Volume (BFV) at Arteriovenous Fistula (AVF) of Hemodialysis (HD) Patients Using a Newly- Developed Photoplethysmography (PPG) Sensor
Paul (C.P.) Paul
National Chiao Tung University
12:00PM 4C.2
A Wireless Multifunctional Monitoring System of Tower Body Running State Based on MEMS Acceleration Sensor
Xiaoning Qi
C-SKY Microsystems Corp
12:20PM 4C.3
Power Management Factors and Techniques for IoT Design Devices Anupriya Prasad
Texas instruments
12:40PM 4C.4
Hierarchical Dynamic Goal Management for IoT Systems
Axel Jantsch1, Arman Anzanpour2, Hedyeh Kolerdi1, Iman Azimi2, Lydia Chaido Siafara1, Amir M.
Rahmani3, Nima TaheriNejad1, Pasi Liljeberg2, Nikil Dutt4
1TU Wien, 2University of Turku, 3University of California Irvine & TU Wien, 4UC Irvine
SESSION 5A
Wednesday March 14
Machine Learning on Conventional and Emerging Platforms
Chair: Hai (Helen) Li, Duke University Co-Chair: Yang (Cindy) Yi, Virginia Tech
3:40PM 5A.1
Quantized Neural Networks with New Stochastic Multipliers Bingzhe Li1, MohammadHassan Najafi1, Bo Yuan2, David Lilja1
1University of Minnesota-twin cities, 2City University of New York
4:00PM 5A.2
High Performance Training of Deep Neural Networks Using Pipelined Hardware Acceleration and Distributed Memory
Raghav Mehta1, Yuyang Huang1, Mingxi Cheng2, Shrey Bagga1, Nishant Mathur1, Ji Li1, Jeffrey Draper3, Shahin Nazarian1
1University of Southern California, 2Duke University, 3Information Sciences Institute
4:20PM 5A.3
Deep Neural Network Acceleration Framework Under Hardware Uncertainty Mohsen Imani1, Pushen Wang1, Tajana Rosing2
1University of California San Diego, 2UCSD
4:40PM 5A.4
A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA
Mahdi Nazemi1, Amir Erfan Eshratifar2, Massoud Pedram1
1USC, 2University of Southern California
SESSION 5B
Wednesday March 14
Hardware Security: PUF, Obfuscation, and Trojan Detection
Chair: Arnett Brown, DARPA
Co-Chair: Swaroop Ghosh, Pennsylvania State University
3:40PM 5B.1
Securing FPGA-based Obsolete Component Replacement for Legacy Systems Zhiming Zhang1, Laurent Njilla2, Charles Kamhoua3, Kevin Kwiat2, Qiaoyan Yu1
1University of New Hampshire, 2Cyber Assurance Branch, Air Force Research Laboratory, 3Army Research Laboratory
4:00PM 5B.2
High Level Synthesis of Key Based Obfuscated RTL Datapaths Sheikh Ariful Islam and Srinivas Katkoori
University of South Florida
4:20PM 5B.3
Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design
Anthony Mattar El Raachini1, Hussein Alawieh1, Adam Issa2, Zainab Swaidan1, Rouwaida Kanj1, Ali Chehab1, Mazen Saghir1
1American University of Beirut, 2University of Toronto
4:40PM 5B.4
Design and Evaluation of Physical Unclonable Function for Inorganic Printed Electronics
Ahmet Turan Erozan1, Mohammad Saber Golanbari1, Rajendra Bishnoi1, Jasmin Aghassi- Hagmann2, Mehdi Tahoori1
1Karlsruhe Institute of Technology, 2Karlsruhe Institute of Technology, Offenburg University of Applied Sciences
SESSION 5C
Wednesday March 14 Demystifying self-driving cars Chair: Jayita Das, Intel Corporation
3:40PM 5C.1
Near-Future Traffic Evaluation based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties
Kuen-Wey Lin1, Masanori Hashimoto2, Yih-Lang Li1
1National Chiao Tung University, 2Osaka University
4:05PM 5C.2
Low cost & power CNN/Deep learning solution for Automated Driving Mihir Mody
Texas Instruments, Inc
4:30PM 5C.3
Resource Constrained Cellular Neural Networks for Real-time Pedestrian Segmentation using Embedded FPGAs.
Yiyu Shi
University of Notre Dame
