An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires
Ya-Chi Huang1, Meng-Hsueh Chiang1, Sumeet Kumar Gupta2, and Shui-Jinn Wang1
1Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
2School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
Outline
Introduction
Device Design Methodology
Conceptual Process Flow
Results and Discussion
Conclusion
[M. LaPedus, semiconductor engineering, Feb. 2018]
Technology generation
Introduction
3-D SOI gate-all-around (GAA) MOSFET
multiple doping levels to offer more choices of Vt
Device Design Methodology
Device Design Methodology
6-T SRAM circuit and schematic layout
Low voltage (LV) PU: PG : PD = 1:1:2 Standard high density (HD)
PU: PG : PD = 1:1:1
20 % area saving
Device Design Methodology
Axis Design rule Symbol Size (nm)
x
Contact width CW 8
Equivalent oxide thickness EOT 1 Contact edge to diffusion CD 8
Poly to Poly P 5.25
Poly to Dif. Ext. Tg 3 Channel thickness tSi 4
Fin pitch FP 10
y
Gate length Lg 9.3
Contact length CL 8
Gate to contact Lsp 3.1
Gate pitch GP 26
z Channel height hSi 4
BOX thickness TBOX 50 Substrate thickness TSub 20
Supply voltage V 0.6 V
Parameters of simulated GAA MOSFET and SRAM design.
Conceptual Process Flow
Different stacked channels of GAA MOSFETs
Left and right devices have different channels
Results and Discussion
Simulated I
DS-V
GScharacteristic
0.0 0.1 0.2 0.3 0.4 0.5 0.6
10-8 10-7 10-6 10-5 10-4 10-3
1 channel 1x1015 2x1019
2 stacked nanowires (bottom/top channel)
1x1015/1x1015 2x1019/2x1019 2x1019/1x1019
I DS (A/µm)
VGS (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0 100 200 300 400 500 600
1 channel 1x1015 2x1019
2 stacked nanowires (bottom/top channel)
1x1015/1x1015 2x1019/2x1019 2x1019/1x1019
I DS (A/µm)
VGS (V)
Ion vs. Ioff characteristics
Results and Discussion
0 100 200 300 400 500
10-12 10-11 10-10 10-9 10-8 10-7
1 channel
2 nanowires, bottom/top different doping same doping I off (A/µm)
Ion (µA/µm)
Doping scheme window for 2 stacked NWs
Results and Discussion
Doping
(cm-3) HD and LV Design RSNM (mV) IW
(μA) 1х1015
(undoped)
1 NW (HD area) 87.32 3.02 2 parallel NWs (LV area) 125.24 2.46 2 stacked NWs (HD area) 132.53 2.51 2х1019 1 NW (HD area) 104.62 1.31 2 parallel NWs (LV area) 130.71 0.84 2 stacked NWs (HD area) 155.03 0.77 Bottom/top channel @ 2х1019/1х1019
2 stacked NWs (HD area) 157.44 0.76
IW versus RSNM characteristics
Conclusions
Propose a comprehensive analysis of stacked NW transistor design with multiple doping levels
offer more choices of Vt in SoC application
Present a conceptual fabrication flow
Evaluate the proposed NW transistors in SRAM design
trade-offs between SNM and write current
Achieve low-voltage 6-T SRAM with 20% saving in area
