Design and Simulation of a Low Power Rake Receiver for Indoor Communication

(1)

Design and Simulation of a Low Power

Rake Receiver for Indoor

Communication

Advisor : Tzi-Dar Chiueh

Student : Po-An Chen

Date : Mar 7th , 2005

(2)

2

Outline

• Introduction

– Background of Rake Receiver – Goal • System Architecture – System Specification – Channel Model – Packet Format – Architecture – Operation Flow • System Simulation – Receiver Performance – Fixed-Point Simulation • Conclusion • Reference

(3)

Introduction

(4)

4

Background of Rake Receiver(1)

• Spread Spectrum Basics

– Transmitting signal using wider bandwidth than necessary – A spreading code is used at Tx and Rx to spread signals – Direct Sequence (DSSS) vs Frequency Hop (FHSS)

[1] a a b c d b c d

(5)

Background of Rake Receiver(2)

• Multi-path fading is a severe non-ideality inherent in

typical wireless channel

• For DSSS system, Rake Receiver provides time diversity by combining signal at different timings

(6)

6

Background of Rake Receiver(3)

• In the NSC_BIST 5GHz project, a low power DSSS receiver is required

• A DSSS receiver alone cannot resolve multi-path fading

(7)

Background of Rake Receiver(4)

• Conventional Rake Receiver consumes high power

– 4.1mW @ 20MHz clock rate

• Optimal number of Rake finger decision rule has been proposed in – LOS • Fingers < 4 – NLOS • Fingers < 13 [4] [3]

(8)

8

Background of Rake Receiver(5)

• Minimum sampling timing spacing of fingers cannot be smaller than inverse of the chip rate

• Fractionally-spaced yields advantage over chip-spaced

– Signal bandwidth > chip rate

-> reducing sampling spacing outperforms integer sampling spacing

• Architectures for fractionally-spaced Rake has been proposed in

– Hardware cost increase – Clock rate increase

[6] [5] T1 T2 T1 T2 integer _fractional Chip rate 16MHz T1- T2 = 1/16MHz T1- T2 = 1/16MHz stronger lower

(9)

Goal

• A low power solution for Rake Receiver

• A fractionally-spaced Rake with low hardware cost

• A receiver capable of combating indoor multi-path fading

Finger 1 Finger 1 Finger 2 Finger 2 Channel estimation Channel estimation Finger 3 Finger 3



Rake receiver Combining (MRC) Weighting Weighting i a i  ( )_i

From Jui- Ping Lien

(10)

System Architecture

(11)

System Specification

• Chip rate 16MHz • PN sequence length 32 • Data rate 1Mbps • Modulation QPSK • CFO +/- 20ppm • RF frequency 5GHz • System Clock 16MHz

• 8 chips per partial correlation • ADC output 64MHz

• A 4-phase DLL

• Rake finger number - 3

• Power consumption < 3mW

(12)

12

Channel Model

• 5GHz narrowband channel model based on 802.11a • TDL model with inverse of 256MHz tap spacing

• Delay Spread

– 10ns, 20ns, 60ns considered

• Doppler Spread

– Around 30 Hz

• CFO effect

– Maximum relative CFO is 40ppm • 5GHz * 40ppm = 200 kHz

(13)

Packet Format

• Preamble

– Coarse CFO estimation – PN code acquisition – Path search

– Channel estimation

• Data Start

– Define data start timing

120 Symbols Preamble 8 Symbols Data Start 1024 Symbols Data [8]

(14)

14

Architecture(1)

• Proposed Receiver [8] Analog Digital

(15)

Architecture(2)

• Conventional Rake Receiver                                )} 3 ] 3 [ ( ) 2 ] 2 [ ( ) 1 ] 1 [ {( ) 3 ] 3 [ ( ) 2 ] 2 [ ( ) 1 ] 1 [ ( ) ] 3 [ ( 3 ) ] 2 [ ( 2 ) ] 1 [ ( 1 W n X W n X W n X PN W n X PN W n X PN W n X PN PN n X W PN n X W PN n X W W1 W2 W3 [9]

(16)

16

Architecture(3)

• Proposed Rake Receiver

– correlator move behind mul tipliers – 3 fingers adopted W1 W2 W3                                )} 3 ] 3 [ ( ) 2 ] 2 [ ( ) 1 ] 1 [ {( ) 3 ] 3 [ ( ) 2 ] 2 [ ( ) 1 ] 1 [ ( ) ] 3 [ ( 3 ) ] 2 [ ( 2 ) ] 1 [ ( 1 W n X W n X W n X PN W n X PN W n X PN W n X PN PN n X W PN n X W PN n X W

(17)

Architecture(4)

• Implementation of Rake Receiver

– DLL required

W1

W2

W3

Clock from DLL controlled by digital circuit while consuming additional Signal

DFF

(18)

18

Operation Flow

• DLL start

– Multi-phase clock • Coarse CFO estimation

– Due to large amount of CFO • PN code acquisition

• Path search

– Find combine path timing • Channel estimation

– Determine path gain • Rake start

(19)

Operation Flow(1)

• DLL start

(20)

20

Operation Flow(2)

• Coarse CFO estimation

(21)

Operation Flow(3)

• PN code acquisition

• Path search

(22)

22

Operation Flow(4)

• Rake start & Data recovery

(23)

System Simulation

(24)

24

Receiver Performance(1)

(25)

Receiver Performance(2)

• Performance with/without Rake receiver

(26)

26

Receiver Performance(3)

(27)

Receiver Performance(4)

• QPSK Constellation

10ns

(28)

28

Fixed-Point Simulation(1)

• ADC output bit length ADC output

(29)

Fixed-Point Simulation(2)

• Rake Receiver Output Bit

(30)

30

Fixed-Point Simulation(3)

• CFO Loop

– Not finished yet

• 5-Path Pre-Carrier Recovery Circuit

– Not finished yet

Phase De-Rotator

NCO

Accumulator Phase Error_Detector

Loop Filter

Initial Frequency Offset

Symbol

Sign

Partial Correlation

9 bit

(31)

Conclusion

• A low power DSSS Rake Receiver has been proposed and simulated

• A DLL is used to implement fractionally spaced Rake Receiver effectively

• System ability of resolving multi-path fading justifies the need for fractionally-spaced finger sampling spacing

(32)

32

Reference

• [1] Communication System, Simon Haykin • [2] NSC_BIST 子計畫六

• [3]Ahmed M. Eltawil and Babak Daneshrad, “A Low-Power DS-CDMA RAKE Receiver Utilizing Resource Allocation Techniques”, IEEE JSSC, vol. 39, Aug. 2004. • [4]Chi-Min Li and Hsueh-Jyh Li, “A Novel RAKE Receiver Finger Number Decisio

n Rule”, IEEE Antennas and Wireless Propagation Letters, vol 2., 2003

• [5] K.J. Kim, et al., “Effect of Tap Spacing on the Performance of Direct-Se quence Spread-Spectrum RAKE Receiver”, IEEE Trans. Commun., vol. 48, June 20 00

• [6]P.Sehier and P. Brelivet, “Performance evaluation of an oversampled Rake receiver”, in Proc. IEEE MILCOM, vol. 2, 1994.

• [7] P802-15_SG3a-Channel-Modeling Final accept revision • [8] NSC_BIST 子計畫五