A Study of ESD Immunity Improvement for the Output Driver in Computer Fan ICs 范德安、陳勝利
E-mail: 9019861@mail.dyu.edu.tw
ABSTRACT
In this thesis, we take an output driver which can drive large current in computer fan ICs for HBM ESD stress. We also design protection circuits to improve ESD robustness by various layout parameters and structures. From the ESD testing result, it was found that the PS mode is weakest for the output driver of computer fan ICs during ESD stress. Eventually, the FOD＆SCR protection circuits were used to protect the whole-chip ESD stress, and put those circuits between the output pad vs. VDD pad and output pad vs. ground pad. Obviously, the ESD immunity in PS mode has been improved in an FOD protection circuit of output driver, the device with channel length L = 4um and with gate couple, and L = 2um with large parasitical base resister, were fabricated by the TSMC 0.6um process. In the same token, the ESD immunity level is also improved too, when an LVTSCR with drain-tap space equals to 4um.
Keywords : Output Buffer ; HBM ; ESD ; FOD ; SCR ; LVTSCR
Table of Contents
封面內頁 簽名頁 授權書．．．．．．．．．．．．．．．．．．．．．．．．． iii 中文摘要．．．．．．．．．．．．
．．．．．．．．．．．． iv 英文摘要．．．．．．．．．．．．．．．．．．．．．．．． v 誌謝．．．．．．．．．
．．．．．．．．．．．．．．．．． vi 目錄．．．．．．．．．．．．．．．．．．．．．．．．．． vii 圖目錄．．
．．．．．．．．．．．．．．．．．．．．．．． ix 表目錄．．．．．．．．．．．．．．．．．．．．．．．．．
xii 第一章 緒論．．．．．．．．．．．．．．．．．．．．．． 1 1.1 靜電放電之影響．．．．．．．．．．．．．．
． 1 1.2 輸出緩衝器之靜電問題．．．．．．．．．．．． 2 1.3 本文提要．．．．．．．．．．．．．．．．．． 6 第二 章 靜電放電概述及測試．．．．．．．．．．．．．．． 7 2.1 靜電的產生．．．．．．．．．．．．．．．．． 7 2.2 靜電放電模式．．．．．．．．．．．．．．．． 8 2.2.1 人體放電模式．．．．．．．．．．．．． 9 2.2.2 機器放電模 式．．．．．．．．．．．．． 11 2.2.3 元件充電模式．．．．．．．．．．．．． 12 2.2.4 電場感應模式．．．．．．
．．．．．．． 13 2.3 靜電放電測試組合．．．．．．．．．．．．．． 13 2.3.1 I/O Pin的靜電放電測試 ．．．．．．．
． 14 2.3.2 Pin to Pin的靜電放電測試．．．．．．． 15 2.3.3 VDD to VSS的靜電放電測試．．．．．．． 17 2.3.4 Analog Pin的靜電放電測試．．．．．．． 17 2.4 靜電放電破壞之測試程序．．．．．．．．．．． 18 2.5 靜電放電破壞之失效 判定．．．．．．．．．．． 19 2.6 靜電放電測試結果的判讀．．．．．．．．．．． 20 第三章 ESD保護電路之基本 元件 ．．．．．．．．．．．．． 22 3.1 ESD保護電路之概念 ．．．．．．．．．．．．． 22 3.2 電阻．．．．．．．
．．．．．．．．．．．．． 24 3.3 二極體．．．．．．．．．．．．．．．．．．． 24 3.4 雙載子電晶體．．．．．．
．．．．．．．．．． 26 3.5 MOS電晶體 ．．．．．．．．．．．．．．．．． 29 3.6 厚場氧化元件．．．．．．．．
．．．．．．．． 32 3.7 矽控閘流體．．．．．．．．．．．．．．．．． 34 第四章 輸出埠之ESD保護電路設計 ．．
．．．．．．．．．． 41 4.1 輸出埠之ESD保護電路設計 ．．．．．．．．．． 41 4.2 結果與討論．．．．．．．．．．
．．．．．．． 54 第五章 結論．．．．．．．．．．．．．．．．．．．．．． 62 參考文獻．．．．．．．．．．．
．．．．．．．．．．．．． 63 附錄．．．．．．．．．．．．．．．．．．．．．．．．．． 66 REFERENCES
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