Fundamentals of Computer Systems
Transistors, Gates, and ICs
Stephen A. Edwards
Columbia University
Spring 2012
Semiconductor
sem·i·con·duc·tor noun
1. a substance, such as silicon or germanium, with electrical conductivity intermediate between that of an insulator and a conductor
2. a semiconductor device
Sand into Silicon
Silica a.k.a. SiO2 a.k.a. Quartz SiO2+ 2 C→ Si + 2 CO
Elemental, amorphous silicon
Monocrystalline Silicon Ingot
Doping Silicon Makes It a Better Conductor
Si Si Si Si Si Si Si Si Si Undoped (pure)
silicon crystal Not a good
conductor
Si Si Si Si B− Si Si Si Si
+
p-type (doped) silicon boron atom steals a nearby
electron
Si Si Si Si As+ Si Si Si Si
−
n-type (doped) silicon:
extra electron on arsenic atom
jump loose
A PN Junction aka A Diode
p (holes) n (electrons) Depletion region
0 V +
+
Ammeter 0
A PN Junction aka A Diode
p (holes) n (electrons) Depletion region
2 V +
+
Ammeter 0
Forward biased: current flows
A PN Junction aka A Diode
p (holes) n (electrons) Depletion region
−2 V +
+
Ammeter 0
Reverse biased: no current flow
An N-Channel MOS Transistor
p (holes)
n n
3 V
0 V +
+
+
Ammeter 0
Drain Source
Gate SiO2
Gate at 0V: Off
An N-Channel MOS Transistor
p (holes)
n n
3 V
3 V +
+
+
Ammeter 0
Drain Source
Gate SiO2
+++++++++
− − − − − − −−
Gate positive: On
The CMOS Inverter
Y
0V 3V
A
A Y
p-FET
n-FET
An inverter is built from two MOSFETs:
An n-FET connected to ground
A p-FET connected to the power supply
The CMOS Inverter
Y
0V 3V
A
A Y
3V 1
0V 0
Off
On
When the input is near the power supply voltage (“1”),
the p-FET is turned off;
the n-FET is turned on, connecting the output to ground (“0”).
n-FETs are only good at passing 0’s
The CMOS Inverter
Y
0V 3V
A
A Y
0V 0
3V 1
On
Off
When the input is near ground (“0”), the p-FET is turned on, connecting the output to the power supply (“1”);
the n-FET is turned off.
p-FETs are only good at passing 1’s
The CMOS NAND Gate
Y A
B A
B Y
Two-input NAND gate:
two n-FETs in series;
two p-FETs in parallel
The CMOS NAND Gate
Y A
B A
B Y
0
0 0 0
1 1
Both inputs 0:
Both p-FETs turned on Output pulled high
The CMOS NAND Gate
Y A
B A
B Y
0
1 0 1
1 1
One input 1, the other 0:
One p-FET turned on Output pulled high
One n-FET turned on, but does not control output
The CMOS NAND Gate
Y A
B A
B Y
1
1 1 1
0 0
Both inputs 1:
Both n-FETs turned on Output pulled low Both p-FETs turned off
The CMOS NOR Gate
Y A
B A
B Y
Two-input NOR gate:
two n-FETs in parallel;
two p-FETs in series.
Not as fast as the NAND gate because n-FETs are faster than p-FETs
A CMOS AND-OR-INVERT Gate
Y C
D A
B
A B C D
Y
Static CMOS Gate Structure
p-FET pull-up network
n-FET pull-down
network Inputs Y
Pull-up and Pull-down networks must be
complementary; exactly one should be connected for each input combination.
Series connection in one should be parallel in the other
CMOS Inverter Layout
Y
Vss
Vdd
A
Cross Section Through N-channel FET
A Vss
Vdd
Y
Top View
Full Adder Layouts
Fromhttp://book.huihoo.com/design-of-vlsi-systems/
Intel 4004: The First Single-Chip Microprocessor
4001: 256-byte ROM + 4-bit IO port 4002: 40-byte RAM
4003: 10-bit shift register
4004: 740 kHz 4-bit CPU w/ 45 instructions (2300 transistors)
