行政院國家科學委員會專題研究計畫 成果報告
低耗能多核心資源管理機制 研究成果報告(精簡版)
計 畫 類 別 ： 個別型
計 畫 編 號 ： NSC 97-2218-E-011-002-
執 行 期 間 ： 97 年 01 月 01 日至 97 年 10 月 31 日 執 行 單 位 ： 國立臺灣科技大學電機工程系
計 畫 主 持 人 ： 陳雅淑
計畫參與人員： 碩士班研究生-兼任助理人員：何書瑋 碩士班研究生-兼任助理人員：廖容章
報 告 附 件 ： 出席國際會議研究心得報告及發表論文
處 理 方 式 ： 本計畫涉及專利或其他智慧財產權，1 年後可公開查詢
中 華 民 國 97 年 11 月 10 日
行政院國家科學委員會補助專題研究計畫 ■ 成 果 報 告
□期中進度報告 低耗能多核心資源管理機制
計畫類別：■個別型計畫 □ 整合型計畫 計畫編號：NSC 97-2218-E-011-002
執行期間： 97 年 1 月 1 日至 97 年 10 月 31 日
計畫主持人：陳雅淑 共同主持人：
計畫參與人員：何書瑋，廖容章
成果報告類型(依經費核定清單規定繳交)：■精簡報告 □完整報告
本成果報告包括以下應繳交之附件：
□赴國外出差或研習心得報告一份
□赴大陸地區出差或研習心得報告一份
■出席國際學術會議心得報告及發表之論文各一份
□國際合作研究計畫國外研究報告書一份
處理方式：除產學合作研究計畫、提升產業技術及人才培育研究計畫、列管計 畫及下列情形者外，得立即公開查詢
□涉及專利或其他智慧財產權，■一年□二年後可公開查詢
執行單位：國立台灣科技大學
中 華 民 國 97 年 11 月 10 日
行政院國家科學委員會補助專題研究計畫期中報告
計畫名稱：低耗能多核心資源管理機制 計畫編號：NSC97-2218-E-011-002
執行期限：計畫自民國 97 年 01 月 01 日至民國 97 年 10 月 31 日止 主持人：陳雅淑 國立台灣科技大學電機工程系
計畫參與人員：何書瑋 國立台灣科技大學電機工程所 廖容章 國立台灣大學資訊工程研究所
中文摘要
多核心嵌入式系統為接下來的多媒體設備 的普遍解決方案，如何在多核心間以最有效的 方式提供使用者對多媒體影音與品質要求、降 低裝置能源消耗並延長設備可使用時間是目 前的重要課題。為降低能源消耗，大部分的處 理器都提供動態電壓與頻率調整的功能。然 而，瞬間降低電壓將造成系統不穩定，不僅可 能降低系統效能，更可能造成電晶體的損壞。
除此之外，在多核心嵌入式系統內多利用記憶 體作為資料共享元件，如何保證資料正確性，
也是一大課題。本研究探討如何設計低耗能多 核心資源管理機制，並考慮電壓改變造成的系 統問題。有別於以往，此計畫提出``頻率上鎖”
觀念，避免頻繁調變電壓，以降低整體耗能並 保證系統穩定性。為確保影音品質要求，本計 畫還提出低耗能管理機制之排程分析，用以分 析資源共享與降低頻率造成的反應時間延 遲。經過一連串實驗，顯示本方法大幅勝出，
相較於之前已提出的研究，本方法最高可降低 30％的能源消耗，有效降低系統能源消耗。
關鍵詞:動態電壓頻率調整，即時同步機 制，即時系統排程，節能
Abstract
The designs of multi-core embedded systems are complicated by various limitations on resource supports, such as computing power, even though their potential application domains grow
exponentially. With energy consumption considerations, modern microprocessors are usually deployed with dynamic-voltage
-frequency-scaling (DVFS) supports. It provides a strong driving force in energy-efficient real-time task scheduling. However, with supply voltages approaching one volt, further large reductions in voltage are unlikely. A significant reduction in power supply voltage variation may cause transient timing faults or performance loss, and it is called voltage emergence. Such emergencies may be addressed by larger design margins at the cost of higher power consumption. We are interested in minimizing the energy consumption of a given task set, provided that the schedulability of tasks and voltage emergency prevention.
This project proposes an energy-efficient real-time synchronization protocol with voltage emergency prevention. The protocol locks the processor frequency in a proper way to avoid voltage emergency, and assigns tasks frequencies to minimize the energy consumption under real-time constraint. Extensive simulations were performed to provide insights. The energy consumption could be reduced up to 30% in the experiments, compared to the previous works.
Keywords:
DVFS, real-timesynchronization protocol, energy-efficiency, real-time scheduling
Voltage Emergence Prevention for Energy-Efficient Real-Time Task Synchronization
Abstract
This paper proposes an energy-efficient real-time synchronization protocol with voltage emergency prevention. The protocol locks the processor frequency in a proper way to avoid voltage emergency, and assigns tasks frequencies to minimize the energy consumption under real-time constraint. Extensive simulations were performed to provide insights. The energy consumption could be reduced up to 30% in the experiments, compared to the previous works.
1 Introduction
With energy consumption considerations, modern microprocessors are usually deployed with dynamic- voltage-frequency-scaling (DVFS) supports. It provides a strong driving force in energy-efficient real-time task scheduling. However, with supply voltages approaching one volt, further large re- ductions in voltage are unlikely. A significant reduction in power supply voltage variation may cause transient timing faults or performance loss [7, 8], and it is called voltage emergence. Such emergencies may be addressed by larger design margins at the cost of higher power consump- tion [11]. To resolve the problem, each processor usually is designed by a given current swing constraint [7], because large swings in current over small time intervals cause large swings in voltages.
While energy-efficient real-time task scheduling is often modeled and resolved in terms of optimization problems, various excellent scheduling algorithms and approximate solutions were proposed in the past decade, e.g.[1, 3, 5, 6]. Beside excellent results reported in the energy-efficient optimization problems, researchers also explore overhead in frequency switching for independent task sets, e.g., [4, 13].
The energy efficiency problem becomes more difficult when there are non-preemptive re- sources shared among tasks, where anomalies or even deadlines are possible. However, there are relatively few results in providing real-time task synchronization protocols. The closest related work is an extension of the Priority Ceiling Protocol [16] in frequency inheritance [10]. Another related work is the concept of two alternative frequencies for task executions [20]. Considering frequency switching overhead, Chen, et al extend the Priority Ceiling Protocol to schedule the task set with static priority assignment by locking the processor frequency in a restricted way [19].
Different from the past work, this research work is motivated by the voltage emergency prob- lem, and the needs in task synchronization protocols. In this paper, we are interested to minimize the energy consumption of a given task set, provided that the schedulability of tasks and voltage emergency prevention. We revise the idea of frequency locking proposed on [19] with current
swing constraint, and extend the concept to schedule the task set with dynamic priority assign- ment. We also propose the methodology to assign tasks frequencies in the minimization of the energy consumption, and with the consideration of schedulability tests and voltage emergency prevention.
The rest of this paper is organized as follows: Section 2 presents the system model and the problem definition. Section 3 proposes the concept of frequency locking with voltage emergence prevention. Algorithm in frequency assignment and schedulability tests is presented. Section 4 reports the performance evaluation of the proposed approach. Section 5 is the conclusion.
2 Problem Definition
The dynamic power consumption P (f ), due to gate switching at processor frequency f , could be modeled as a convex function of the processor speed [14] : P (f ) = CefVdd2f, where f = κ(VddV−Vt)2
dd , and Cef, Vt, Vdd, and κ denote the effective switch capacitance, the threshold voltage, the supply voltage, and a hardware-design-specific constant, respectively. Moreover, to avoid volt- age emergency, the processor will be designed by a given current swing constraint. The current swing constraint (di/dt) can be modeled as the frequency swing constraint by V = L ∗ di/dt, where V is the voltage across an inductor of value L. In this paper, we assume that each processor has a frequency swing constraint fc. In other words, each frequency switching of the processor can only switch current frequency fnowto a frequency which is in the range [fnow− fc, fnow+ fc].
In this paper, we will focus our discussions on the cases in which the processor can operate at any frequency f in a given range [fmin, fmax]. Further extensions of this work for processors with discrete available frequency can be done by approaches similar to those reported in [6].
Each periodic task τi in the system is associated with an initial arrival time ai, a worst-case execution CPU cycles ci, and a period pi. The relative deadline di of τi is equal to its period pi. A task is a template of its jobs, where a job is instantiated for each request of the task. Let the number of CPU cycles executed in a time interval be proportional of the processor frequency. In other words, the number of CPU cycles completed for a task running at a processor frequency f for t time units is f ∗t. The energy consumed for a processor in the execution of a task at the processor frequency f for t time units is t ∗ P (f ). In order to meet the deadline constraint of each task, every task is assigned a base frequency based on off-line analysis. Therefore, the base frequency of a task τi is the lowest frequency to execute τiso that no deadline violation is possible for τi.
Suppose that each resource in the system is guarded by a unique semaphore. Before a task accesses any resource, the corresponding semaphore must be locked. In this paper, we consider exclusive locks with an objective in the focusing of the concept for energy-efficient real-time task synchronization. Only binary semaphores are adopted for the simplicity of discussion. When the lock request is blocked, the job is said being blocked. Depending on the adopted resource synchronization protocol and the run-time situation, each job might suffer from a different amount of blocking time from some lower-priority tasks, due to access conflict. In this paper, the energy consumption of a task set T is defined as the energy consumption of tasks in the hyper-period of T, denoted by L, where L is the LCM of the task period in T.
In this paper, we shall propose an energy-efficient real-time synchronization protocol to prevent voltage emergency and schedule the task set with dynamic priority assignment. The goal is to adjust the processor frequency in a proper pattern to avoid voltage swing, and limit the occasions in frequency switchings to minimize total energy consumption.
τ ττ
τ
τ τ
(a) FLV-SRP
τ ττ
τ
τ τ
(b) SRP with USFI
Figure 1: FLV-SRP v.s. SRP with USFI
3 Proposed Approach
3.1 Protocol: FLV
When earliest deadline first (EDF) [12] is adopted for scheduling a set of dynamic-priority in- dependent task, it is shown that the frequencies of all task executions should be the same in the minimization of the energy consumption [1]. However, when there are shared resources among tasks, to minimize energy consumption, each task will be executed in different frequency [20]. In this section, to guard resource shared between dynamic-priority tasks, we extend SRP [2] with volt- age emergence prevention rules by revising frequency locking idea, referred to as FLV-SRP. The task model under discussions follows directly from that of SRP, where a set of dynamic-priority tasks is considered in a uniprocessor environment, and binary semaphores are adopted for task synchronization. The protocol is revised as follows:
Algorithm 1 FLV-SRP
I Task Scheduling, Resource Allocation and Priority Inheritance: Rules are as the same as those of SRP.
II Frequency Switching:
• The processor frequency is switched to a proper one when a task is dispatched and scheduled for the first time, or when all of the executing tasks just finish their executions at this time point.
• The new processor frequency is set based on the following three conditions:
– If no task is dispatched and scheduled for the first time, and all of the exe- cuting tasks just finish their executions at this time point, then the frequency is set as the one for the idle mode.
– If a task is dispatched and scheduled for the first time, and all of the exe- cuting tasks just finish their executions at this time point, then the processor frequency is set as the base frequency of the task by switching frequency no more than fcin each step to meet the frequency swing constraint.
– Otherwise, the processor frequency remains.
As shown in Algorithm 1, the rules of task scheduling, resource allocation and priority inheri- tance are exactly as the same as those of SRP [2], except the rule is on frequency switching. The
time moment for frequency switching is determined when a task is dispatched and scheduled for the first time, or when all of the executing tasks just finish their executions at this time point. The idea is to lock up the processor frequency for a longer time at a proper level [19] for saving energy consumption. However, to prevent voltage emergency, each frequency switching shall be not more than the frequency swing constraint fc as shown in the second condition of frequency switching rule in FLV-SRP. As a result, in FLV-SRP, processor frequency is set as the base frequency of the task by switching frequency no more than fcin each step.
FLV-SRP could be better illustrated by the following example: Consider three tasks τL, τM and τH, which are ready to execute at time 0, 3 and 5, respectively. Let τH and τL have the highest priority and the lowest priority in the task set, respectively. The priority ceilings of R1 and R2 are both the priority of τH, according to the definitions of SRP. Let the periods of τH, τM, and τL be 15, 20 and 25 time units, respectively. The worst-case execution times of τH, τM, and τLare 5, 3, and 6 CPU cycles at the maximum processor frequency fmax, respectively.
By the frequency assignment algorithm which will be presented in the later section, the base frequencies of τH, τM and τL are set as 1/2 ∗ fmax, 2/3 ∗ fmax and 2/3 ∗ fmax, respectively. As shown in Figure 1.(a), there are only two frequency switchings in this case (when τL starts and finishes its execution, respectively), and two priority inversions occurs. In FLV-SRP, we assign a lower priority task to a higher base frequency in execution because of more task preemption cost from higher priority tasks. Therefore, each task will be executed at a frequency which is not lower than its base frequency under FLV-SRP, such that no task will violate the real time constraint.
A counter example is shown in Figure 1.(b), we schedule tasks by SRP with the Uniform Slowdown with Frequency Inheritance algorithm (USFI) [10] to minimize the energy consumption.
In this way, the base frequencies of τH, τM and τLare set as 1 ∗ fmax, 2/3 ∗ fmax and 1/2 ∗ fmax, respectively. In SRP with USFI, a higher priority task to a higher base frequency in execution.
Moreover, the lower priority task τLwill inherit the frequency of the blocked higher priority task τH (τM), when τH (τM) is blocked by τL. In this example, there will be totally 4 frequency switchings when all of the tasks finish their executions. As astute readers might point out, the overhead in frequency switching might be overwhelming, especially there is a frequency swing constraint of the processor. The rational is that one frequency switching might cause more than one switching cost when the frequency swing constraint is considered.
Lemma 3.1 There is no frequency switching under FLV-SRP when task preemption occurs, or when a task is blocked.
Proof. The correctness of this lemma follows directly from the frequency switching rules of FLV- SRP. ¤
Lemma 3.2 No task executes at a frequency less than its base frequencies under FLV-SRP.
Proof. The correctness of this lemma follows directly from the frequency switching rules of FLV- SRP.¤
Lemma 3.3 There is no frequency swing violation under FLV-SRP.
Proof. The correctness of this lemma follows directly from the frequency switching rules of FLV- SRP.¤
Theorem 3.4 [12] Task τiis schedulable by EDF if and only if 1 ≥P
1≤j<i(CDj
j) + (CDi
i), where Ci and Di denote the worst-case CPU time and the deadline of task τi, respectively.
Theorem 3.5 [2] Task τi is schedulable by SRP if 1 ≥ P
1≤j<i(DCjj) + (BiD+Ci i), where Ci, Di, and Bidenote the worst-case CPU time, the deadline, and the worst-case blocking time of task τi, respectively.
3.2 Frequency Assignment
The task frequency assignment under FLV-SRP problem can be formulated as an optimization problem: The objective is to assign each task τiin a task set T = {τ1, · · · , τn} a base frequency fi so as to minimize the worst-case energy consumption of task executions in the hyper-period, i.e., P (fn) ∗P
1≤i≤n((fci
n+ 2β) ∗pL
i) + P (fn) ∗α∗(fnf−fmin)
c ∗P
1≤i≤(k−1) L
pi+ Pidle∗ (L − (P
1≤i≤n(fci
n+
2β) ∗ pL
i)), where Pidle is the energy consumption per time unit during the idle time, and k is the smallest task index such that fk = fn, subject to the following constraints (Please see Theorem 3.6 for the worst-case energy consumption estimation):
1 ≥ i−1X j=1
(cj fj ∗ 1
pj) + (ci fi∗ 1
pi+2β pi) +
Xi j=1
(α ∗ (fn− fmin)
fc ∗ 1
pi)
i = 1, 2..., n (1)
1 ≥ i−1X j=1
(cj fj ∗ 1
pj) + (Bi+ ci fk ∗ 1
pi) + i−1X j=1
(α ∗ (fn− fmin)
fc ∗ 1
pi)
i = 1, 2..., n, k = i + 1, i + 2..., n (2)
P (fn)ci
fn ≥P (fi)(ci+ α)
fi i = 1, 2.., n (3)
fmin≤ fi≤ fmax, i = 1, 2.., n (4)
fi−1≤ fi i = 2.., n (5)
To meet the real-time constraint, Equation 1 and Equation 2 make sure that execution cost, blocking cost and frequency switching cost are both satisfied in schedulability tests. To reducing the energy consumption, Equation 3 is to make sure that the energy consumption to run a task at its base frequency plus the energy consumption in frequency switching is no larger than the energy consumption to run the task at the maximum base frequency of tasks. Equation 4 lets the base frequencies of tasks stay in a legal range [fmin, fmax]. Equation 5 requires that lower priority tasks are assigned higher base frequencies because of more task preemption cost from higher priority tasks.
By definition, the worst case CPU time Ciof a task τi is the ratio of the worst case CPU cycles of the task to the base frequency of the task (i.e., cfi
i). Therefore, according to theorem 3.4, the first and second terms in the right hand side of the Equation 1 make sure that execution cost is satisfied in schedulability tests (plus the worst-case cost in switching between operating and idle modes). Let β denote the delay time to switch from the operating mode to the idle mode (and vice versa). In the worst case, there are 2β in the second term: One happens when τi arrives at the time moment when the processor is switched from the operating mode to the idle mode. The other happens when the processor is switched from the idle mode back to the operating mode to run a task with a priority no less than that of τi. Note that the relative deadline di of τi is equal to its period pi in this paper.
In a dynamic-voltage-frequency-scaling processor, we shall also consider the frequency switch- ing overhead to make sure that each task is satisfied the schedulability test. The third term of Equation 1 denote the frequency switching cost of the i-th task, and it comes from to switch the processor frequency of a higher priority task to that of another higher priority task (including τi) because the former task finishes its execution, and the later then starts its execution at the same time. However, to avoid voltage emergency, each frequency switching of the processor can only switch current frequency fnow to a frequency which is in the range [fnow − fc, fnow+ fc]. As a result, the total frequency switching overhead for changing the processor frequency to the base frequency of task τiis boundedPi
j=1
α∗(fn−fmin)
fc , where α is the worst-case CPU cycles for each frequency switching [17]. Note that there is no frequency switching due to task preemption based
on corollary 3.1. The third term is the ratio of the cost and the period of τi because the cost is charged to τi as a part of its utilization.
By considering the effect on blocking time, Equation 2 adds the blocking time effect on the schedulability test, according to Theorem 3.5. Let Bi denote the worst-case blocking CPU cycles of a task τi under SRP (i.e., the corresponding worst-case blocking time of a task under SRP with CPU cycles as units). The derivation of Bi follows directly from the corresponding way in blocking time derivation under SRP [2]. However, τi will be executed at a frequency no less than τk’s base frequency under FLV-SRP until τi completes its execution, when a task τi is blocked by a low priority task τk. The rationale is that τi is blocked by a low priority task τk, only when τk is not finished. Because τi is blocked only when the processor is not idle, in Equation 2, the second term in the right hand side of the inequality of Equation 1 is revised to Bif+ci
k ∗ p1
i, due to additional blocking CPU cycles Bi, where fkis the lowest frequency among based frequencies of tasks with priority lower than τi. Reader might note that a task might be executed by a frequency which is higher than its base frequency, when the task is blocked. As a result, to guarantee the timing constraints of tasks, Equation 1 and Equation 2 are both needed.
Theorem 3.6 Given a set of n periodic schedulable tasks, the total energy consumption under FLV-SRP in a hyper-period is no more than P (fn) ∗P
1≤i≤n((fcni + 2β) ∗pLi) + P (fn) ∗α∗(fnf−fc min)∗ P
1≤i≤(k−1) L
pi + Pidle∗ (L − (P
1≤i≤n(fci
n + 2β) ∗pL
i)), where Pidleis the energy consumption per time unit during the idle time, and k is the smallest task index such that fk= fn.
Proof. The correctness of the energy consumption bound follows directly from the following three facts: (1) The first part serves as an upper bound on the energy consumption of task executions and the frequency switching to their corresponding base frequency, and the worst-case delay time in switching between operating and idle modes per task execution is at most 2β. (2) The second part is the energy consumption in the processor frequency switching to execute tasks with the base frequency as fn. Since a frequency switching for the execution of a task with the base frequency as fnoccurs only when the current processor frequency is not fn, the number of frequency switchings to execute all of tasks with the base frequency as fnis at least bounded byP
1≤i≤k−1 L
pi. Moreover, to avoid voltage emergency, each frequency switching can change the processor frequency no more than fc. As a result, it needs at least (fn−ffcmin) steps to change the current frequency of processor to fn. Note that when a task with the base frequency as fnis dispatched, the processor frequency will be locked at fnuntil the task completes according to corollary 3.1. (3) The third part is an upper bound on the energy consumption of task executions at the idle mode. ¤
4 Performance Evaluation
4.1 Data Sets and Performance Metrics
In this section, the proposed FLV-SRP was evaluated for energy consumption in task executions.
SRP without voltage scaling (i.e., SRP) [16], SRP with a minimal constant frequency (SRPC), the Uniform Slowdown with Frequency Inheritance algorithm (USFI) [10], and the Dual Speed algorithm (DS) [20] were adopted for comparisons. Under SRPC, all of the tasks executed at the maximum of the minimal required frequency of each task based on the schedulability test of SRP as Theorem 3.5.
0 20 40 60 80 100
0.03 0.025 0.02
0.015 0.01
Average Normalized Energy Consumption (%)
Frequency Swing Contraint SRPC
DS USFI FLV-SRP
(a) α=0.05
0 20 40 60 80 100
0.03 0.025 0.02
0.015 0.01
Average Normalized Energy Consumption (%)
Frequency Swing Contraint SRPC
DS USFI FLV-SRP
(b) α=0.1
Figure 2: Normalized energy consumption with different values of the frequency swing constraint
In the experiments, the number of tasks per task set ranged from 10 to 20. Each task was periodic, and the period was randomly picked up in the range [20ms, 8000ms]. The blocking factor of a task was defined as the maximum percentage of time in the execution time of a task in blocking, and it ranged from 10% to 30%. In other words, the maximum blocking duration of a task τi was ci∗ blocking f actori [10]. The initial arrival time of each task was generated by a random distribution function.
To perform the dynamic-voltage-frequency scaling, the CPU utilization of each task ranged from 5% to 10%, and the total CPU utilization of each task set ranged from 40% to 70% based on the maximum processor frequency. The maximum and minimum available frequencies were nor- malized to 1 and 0.1, respectively. To estimate the system energy consumption, the specifications of Intel XScale was adopted in the experiments, where the power consumption function was ap- proximated by P (f ) = (0.08 + 1.52f3) Watt [15]. The frequency switching overhead ranged from 0.05ms to 0.1ms. The frequency swing constraint fcranged from 0.01 to 0.03 when the maximum processor frequency is 1 [9, 21]. The delay time in switching from the operating mode to the idle mode (and vice versa) was defined as 1 µs [18]. The power consumption in the idle mode was set as 0.01 times of that in the operating mode.
The primary metric in performance evaluation was the normalized energy consumption. Let X and Y denote the energy consumption amount of the algorithm under performance evaluation and that of SRP, respectively. The normalized energy consumption of the algorithm was defined as X/Y . In the experiments, 1000 task sets were generated for each system configuration, and their results were averaged for comparison. Each simulation run was conducted for the duration of the hyperperiod of the task set. When the number of available processor frequencies was finite, the available frequencies were derived by picking up real numbers between 0.1 to 1 with an equal consecutive distance. For example, 0.1, 0.55, and 1 were the available frequencies of a processor with three available frequencies.
4.2 Experiment Results
Figure 2.(a) and (b) showed the normalized energy consumption of FLV-SRP, SRP, SRPC, USFI, and DS, when there were 10 tasks with the total CPU utilization U = 0.6, the available frequencies could be any number between 0.1 and 1.0, and the frequency switch overhead is 0.05ms and 0.1ms, respectively. The horizontal axis is the frequency swing constraint fc, and the vertical axis is the normalized energy consumption.
0 20 40 60 80 100
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Average Normalized Energy Consumption (%)
Frequency Levels
SRPCDS FLV-SRPUSFI
(a) Frequency Levels=20
0 20 40 60 80 100
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Average Normalized Energy Consumption (%)
Frequency Levels
SRPC DS USFI FLV-SRP
(b) Frequency Levels=100
Figure 3: Normalized energy consumption with different numbers of processor frequencies
It was shown that FLV-SRP outperformed than other algorithms, such as the energy consump- tion only 30% of that of SRP, where the energy consumption of SRP was 100% in comparison.
FLV-SRP was also good in terms of energy consumption with voltage emergency prevention, be- cause the variation of energy consumption of FLV-SRP is small when the frequency swing or over- head of frequency switching is varied. The main difference from FLV-SRP and other algorithms is that the overhead of frequency switching and the cost of voltage emergency prevention were con- sidered in task frequency assignment of FLV-SRP in Section 3.2. Note that all tasks under SRPC will be executed at the same frequency. As a result, the variation of energy consumption of SRPC is also small. Experiments were also conducted to evaluate the energy consumption of FLV-SRP with different task numbers and different total CPU utilization. The results showed that the energy consumption increased, and the performance gap between FLV-SRP and USFI/DS increased, when the number of tasks increased or total CPU utilization increased.
Figure 3.(a) and (b) showed the normalized energy consumption of FLV-SRP, SRP, SRPC, USFI, and DS, when there were 10 tasks with the total CPU utilization U = 0.6, the frequency switch overhead is 0.1ms, and frequency swing constraint fc is 0.01. The horizontal axis is the number of frequency levels of a processor, and the vertical axis is the normalized energy consump- tion. The energy consumption of task executions, when there were 5 and 20 available processor frequencies, was 10% and 3% more than that when there was an infinite number of the processor frequency, respectively. The experiments of those with different values in the frequency swing constraint had similar results, and they were not included in the paper. The results also show that the cost in voltage emergency prevention had little impacts on the number of needed processor frequencies.
5 Conclusion
This paper is one of the pioneering exploring real-time task synchronization with the minimization of energy consumption and voltage emergency prevention. To manage the frequency switching overhead and avoid voltage emergency, we revise the concept of frequency locking proposed on [19] with current swing constraint. Moreover, we also propose the frequency assignment method to provide the schedulability of the task set with dynamic priority assignment. Performance eval- uations show that our proposed algorithms can significantly reduce the energy consumption even with voltage emergency prevention.
References
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可供推廣之研發成果資料表
■ 可申請專利 □ 可技術移轉 日期：97 年 11 月 10 日
國科會補助計畫
計畫名稱：低耗能多核心資源管理機制 計畫主持人：陳雅淑
計畫編號：NSC97-2218-E-011-002 學門領域：資訊工程
技術/創作名稱 使用於嵌入式作業系統的低耗能資源管理機制 發明人/創作人 陳雅淑
技術說明
中文：
本機制適用於嵌入式作業系統，協助降低嵌入式系統的整體耗能。
其特點是不需更動硬體設定，並具有完整分析機制協助系統開發者 發展新系統。
英文：
This project proposes an energy-efficient real-time synchronization protocol with voltage emergency prevention. The protocol locks the processor frequency in a proper way to avoid voltage emergency, and assigns tasks frequencies to minimize the energy consumption under real-time constraint.
可利用之產業 及 可開發之產品
嵌入式相關設備
技術特點
實做簡易 提供完整分析
推廣及運用的價值
在多媒體手持式電子裝置上，能源消耗一直是主要課題，該技術能 有效協助降低能源消耗，並且不需要多餘的硬體支援。
※ 1.每項研發成果請填寫一式二份，一份隨成果報告送繳本會，一份送 貴單位研 發成果推廣單位（如技術移轉中心）。
※ 2.本項研發成果若尚未申請專利，請勿揭露可申請專利之主要內容。
※ 3.本表若不敷使用，請自行影印使用。
出席國際學術會議心得報告
計畫編號 NSC97-2218-E-011-002
計畫名稱 低耗能多核心資源管理機制 出國人員姓名
服務機關及職稱
陳雅淑
國立台灣科技大學電機工程系 助理教授 會議時間地點 Sydney, Austria, 7/8-7/11
會議名稱 IEEE 8th International Conference on Computer and Information Technology 發表論文題目 Voltage Emergence Prevention for Energy-Efficient Real-Time Task
Synchronization
一、參加會議經過 目的:
本次參加的國際學術會議是 IEEE CIT 2008 研討會，此技術會議主要討論資訊相關技術，
囊括多媒體技術，軟體發展，積體電路設計等等，會議地點在澳洲雪梨舉行。本人於此
次會議發表低耗能多核心資源管理機制，透過動態調動頻率與電壓，並同時考慮電壓調
動的實作問題，其實驗結果大幅勝出現存的相關機制。
過程:
本次會議發表的論文是在 VLSI and Computer Systems 的場次發表，會場位於雪梨科技大
學。在此場次中，發表的論文著重於嵌入式系統的處理器與記憶體架構的討論，由於系
統晶片的蓬勃發展，有許多業者持續關心於如何發展更適於消費性電子產品上的低價
格、低耗能、高效能的處理器，於是學者仍在努力研發新技術中。具體而言，我們討論
如何設計 Sigma-Delta Modulated Processor，作者著重於加法器的改進；針對嵌入式系統
的記憶體保護問題，作者提出簡易方法避免增加過多系統負擔；16 位元指令集處理器架
援動態調動頻率和電壓的處理器，通常都不能忍受短時間大幅度的電壓調動，此舉將會
造成處理器不可預期之錯誤。針對這樣的問題，本人提出不同於以往的低耗能資源管理
機制，協助多核心系統共享資源的正確性，並在電壓調動的限制下，盡可能的降低整體
耗能。為保證應用程式執行的正確性，本論文還提出相關排程分析機制，可用於系統發
展前期的分析與動態執行的行為預測。
二、與會心得
會議過程中，與外國學者交換許多有益的意見，過程中本人發現，關於作業系統在
多核心上的實際應用，是大家相當關心的問題，主因為硬體的全面加速，可是作業系統
尚未全面性解決此問題，而仍維持在單一處理器上執行，使得系統內只能應用協同合作
機制，而非平行執行機制。
這次會議的主辦單位為雪梨科技大學，該校為澳洲的重點科技大學，與本人任教的
台灣科技大學，擁有類似的教育理念與地位。我與該校的教授也交換了許多關於科技大
學面臨的競爭問題，與學生未來主要發展的方向，讓本人吸收了不同國家對科技大學的
不同規劃與執行方式，受益良多。讓本人較為在意的是，相較於以往，本次參加會議較
多人知道台灣的存在，不再有人誤認我為泰國人，可是卻有泰國人詢問我，為何我們的
立法院總是不停的上演全武行，讓本人只能委婉地回答，台灣人問政的方式比較熱情一
點。針對這樣的事情，我一則喜於台灣在國際間逐漸被大家得知，一則憂於國際形象的
維持。本人僅能在國際會議舉行期間，不僅交換專業學術意見，也嘗試讓與會者認識台
灣學者與台灣其他沒有被媒體報導的進步面。
Voltage Emergence Prevention for Energy-Efficient Real-Time Task Synchronization
Ya-Shu Chen1 and Tay-Jyi Lin2
1Department of Electrical Engineering, National Taiwan University of Science and Technology
2SoC Technology Center, Industrial Technology Research Institute
Abstract
This paper proposes an energy-efficient real-time syn- chronization protocol with voltage emergency prevention.
The protocol locks the processor frequency in a proper way to avoid voltage emergency, and assigns tasks fre- quencies to minimize the energy consumption under real- time constraint. Extensive simulations were performed to provide insights. The energy consumption could be re- duced up to 30% in the experiments, compared to the pre- vious works.
1 Introduction
With energy consumption considerations, modern micro- processors are usually deployed with dynamic-voltage- frequency-scaling (DVFS) supports. It provides a strong driving force in energy-efficient real-time task scheduling.
However, with supply voltages approaching one volt, fur- ther large reductions in voltage are unlikely. A significant reduction in power supply voltage variation may cause transient timing faults or performance loss [7, 8], and it is called voltage emergence. Such emergencies may be addressed by larger design margins at the cost of higher power consumption [11]. To resolve the problem, each processor usually is designed by a given current swing constraint [7], because large swings in current over small time intervals cause large swings in voltages.
While energy-efficient real-time task scheduling is of- ten modeled and resolved in terms of optimization prob- lems, various excellent scheduling algorithms and ap- proximate solutions were proposed in the past decade, e.g.[1, 3, 5, 6]. Beside excellent results reported in the energy-efficient optimization problems, researchers also explore overhead in frequency switching for independent task sets, e.g., [4, 13].
The energy efficiency problem becomes more difficult when there are non-preemptive resources shared among tasks, where anomalies or even deadlines are possible.
However, there are relatively few results in providing real- time task synchronization protocols. The closest related work is an extension of the Priority Ceiling Protocol [16]
in frequency inheritance [10]. Another related work is the
concept of two alternative frequencies for task executions [20]. Considering frequency switching overhead, Chen, et al extend the Priority Ceiling Protocol to schedule the task set with static priority assignment by locking the pro- cessor frequency in a restricted way [19].
Different from the past work, this research work is mo- tivated by the voltage emergency problem, and the needs in task synchronization protocols. In this paper, we are interested to minimize the energy consumption of a given task set, provided that the schedulability of tasks and volt- age emergency prevention. We revise the idea of fre- quency locking proposed on [19] with current swing con- straint, and extend the concept to schedule the task set with dynamic priority assignment. We also propose the methodology to assign tasks frequencies in the minimiza- tion of the energy consumption, and with the consider- ation of schedulability tests and voltage emergency pre- vention.
The rest of this paper is organized as follows: Section 2 presents the system model and the problem definition.
Section 3 proposes the concept of frequency locking with voltage emergence prevention. Algorithm in frequency assignment and schedulability tests is presented. Section 4 reports the performance evaluation of the proposed ap- proach. Section 5 is the conclusion.
2 Problem Definition
The dynamic power consumption P (f ), due to gate switching at processor frequency f , could be modeled as a convex function of the processor speed [14] : P (f ) = CefVdd2f, where f = κ(VddV−Vt)2
dd , and Cef, Vt, Vdd, and κ denote the effective switch capacitance, the thresh- old voltage, the supply voltage, and a hardware-design- specific constant, respectively. Moreover, to avoid volt- age emergency, the processor will be designed by a given current swing constraint. The current swing constraint (di/dt) can be modeled as the frequency swing constraint by V = L ∗ di/dt, where V is the voltage across an in- ductor of value L. In this paper, we assume that each processor has a frequency swing constraint fc. In other words, each frequency switching of the processor can only
switch current frequency fnow to a frequency which is in the range [fnow − fc, fnow+ fc]. In this paper, we will focus our discussions on the cases in which the pro- cessor can operate at any frequency f in a given range [fmin, fmax]. Further extensions of this work for proces- sors with discrete available frequency can be done by ap- proaches similar to those reported in [6].
Each periodic task τiin the system is associated with an initial arrival time ai, a worst-case execution CPU cycles ci, and a period pi. The relative deadline diof τiis equal to its period pi. A task is a template of its jobs, where a job is instantiated for each request of the task. Let the number of CPU cycles executed in a time interval be proportional of the processor frequency. In other words, the number of CPU cycles completed for a task running at a processor frequency f for t time units is f ∗ t. The energy consumed for a processor in the execution of a task at the processor frequency f for t time units is t ∗ P (f ). In order to meet the deadline constraint of each task, every task is assigned a base frequency based on off-line analysis. Therefore, the base frequency of a task τi is the lowest frequency to execute τiso that no deadline violation is possible for τi.
Suppose that each resource in the system is guarded by a unique semaphore. Before a task accesses any re- source, the corresponding semaphore must be locked. In this paper, we consider exclusive locks with an objective in the focusing of the concept for energy-efficient real- time task synchronization. Only binary semaphores are adopted for the simplicity of discussion. When the lock request is blocked, the job is said being blocked. Depend- ing on the adopted resource synchronization protocol and the run-time situation, each job might suffer from a dif- ferent amount of blocking time from some lower-priority tasks, due to access conflict. In this paper, the energy con- sumption of a task set T is defined as the energy con- sumption of tasks in the hyper-period of T, denoted by L, where L is the LCM of the task period in T.
In this paper, we shall propose an energy-efficient real- time synchronization protocol to prevent voltage emer- gency and schedule the task set with dynamic priority as- signment. The goal is to adjust the processor frequency in a proper pattern to avoid voltage swing, and limit the oc- casions in frequency switchings to minimize total energy consumption.
3 Proposed Approach
3.1 Protocol: FLV
When earliest deadline first (EDF) [12] is adopted for scheduling a set of dynamic-priority independent task, it is shown that the frequencies of all task executions should be the same in the minimization of the energy consump- tion [1]. However, when there are shared resources among tasks, to minimize energy consumption, each task will be
executed in different frequency [20]. In this section, to guard resource shared between dynamic-priority tasks, we extend SRP [2] with voltage emergence prevention rules by revising frequency locking idea, referred to as FLV- SRP. The task model under discussions follows directly from that of SRP, where a set of dynamic-priority tasks is considered in a uniprocessor environment, and binary semaphores are adopted for task synchronization. The protocol is revised as follows:
Algorithm 1 FLV-SRP
I Task Scheduling, Resource Allocation and Pri- ority Inheritance: Rules are as the same as those of SRP.
II Frequency Switching:
• The processor frequency is switched to a proper one when a task is dispatched and scheduled for the first time, or when all of the executing tasks just finish their execu- tions at this time point.
• The new processor frequency is set based on the following three conditions:
– If no task is dispatched and scheduled for the first time, and all of the execut- ing tasks just finish their executions at this time point, then the frequency is set as the one for the idle mode.
– If a task is dispatched and scheduled for the first time, and all of the execut- ing tasks just finish their executions at this time point, then the processor frequency is set as the base frequency of the task by switching frequency no more than fcin each step to meet the frequency swing constraint.
– Otherwise, the processor frequency remains.
As shown in Algorithm 1, the rules of task schedul- ing, resource allocation and priority inheritance are ex- actly as the same as those of SRP [2], except the rule is on frequency switching. The time moment for frequency switching is determined when a task is dispatched and scheduled for the first time, or when all of the executing tasks just finish their executions at this time point. The idea is to lock up the processor frequency for a longer time at a proper level [19] for saving energy consumption.
However, to prevent voltage emergency, each frequency switching shall be not more than the frequency swing con- straint fc as shown in the second condition of frequency switching rule in FLV-SRP. As a result, in FLV-SRP, pro- cessor frequency is set as the base frequency of the task by switching frequency no more than fcin each step.
