Room Temperature Fabrication of High Quality ZrO 2 Dielectric Films for High Performance

(1)

280 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 2, FEBRUARY 2018

Room Temperature Fabrication of High Quality ZrO ₂ Dielectric Films for High Performance

Flexible Organic Transistor Applications

Yanfen Gong, Kai Zhao, Longsen Yan, Weiyao Wei, Cheng Yang, Honglong Ning , Sujuan Wu, Jinwei Gao, Guofu Zhou, Xubing Lu, and J.-M. Liu

Abstract —By using low-cost solution process and ultraviolet (UV) irradiation, we successfully fabricated high- quality ZrO₂ films at room temperature. The ZrO₂ films obtained with 1-h UV curing showed a very low leakage current (1.7 × 10^-6 A/cm² at −3 V), a high breakdown electric field 7.9 MV/cm, a high bandgap (6.13 eV), and a high dielectric constant (17.8). The organic thin-film tran- sistor made by solution-processed ZrO₂ gate dielectric shows a greatly reduced operation voltage of 4 V, and a high drain current on/off ratio of 3.1×10⁶. Furthermore, we also clarified the electronic structures of ZrO₂films with UV cured or thermal annealing. This letter demonstrated that solution-processable ZrO₂film is promising for applications in future low power consumption electronic devices.

Index Terms—OTFT, room temperature fabrication, UV treatment, ZrO₂films.

I. INTRODUCTION

I

N THE last decades considerable efforts have been made to develop high-k dielectrics to replace traditional SiO2

Manuscript received December 3, 2017; accepted December 12, 2017. Date of publication December 15, 2017; date of current version January 25, 2018. This work was supported in part by the National Natural Science Foundation of China under Contract 51472093 and Contract 51431006, in part by the Science and Technology Planning Project of Guangdong Province under Grant 2016B090907001, in part by the Guangdong Innovative Research Team Program under Grant 2013C102, in part by the Guangdong Provincial Key Laboratory of Optical Information Materials and Technology under Grant 2017B030301007, and in part by the 111 Project. The work of X. Lu was supported by the Project for Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme under Grant 2016. The review of this letter was arranged by Editor D. Akinwande.(Corresponding authors: Xubing Lu;

J.-M. Liu.)

Y. Gong, K. Zhao, L. Yan, W. Wei, C. Yang, S. Wu, J. Gao, and X. Lu are with the Institute for Advanced Materials, South China Academy of Advanced Optoelectronics, and the Guangdong Provin- cial Laboratory of Quantum Engineering and Quantum Materials, South China Normal University, Guangzhou 510006, China (e-mail:

[email protected]).

H. Ning is with the State Key Laboratory of Luminescent Materials and Devices, Institute of Polymer Optoelectronic Materials and Devices, South China University of Technology, Guangzhou 510640, China.

G. Zhou is with the Electronic Paper Displays Institute and the Guang- dong Provincial Key Laboratory of Optical Information Materials and Technology, South China Academy of Advanced Optoelectronics, South China Normal University, Guangzhou 510006, China.

J.-M. Liu is with the Laboratory of Solid State Microstructures, Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China (e-mail: [email protected]).

Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2017.2783945

to lower the operating voltage and enhance on/off ratio of the drain current in OTFTs [1], [2]. Among the methods of fabricating the high-k dielectric films, the solution-processing has attracted wide attentions, since it has the advantages of low-cost, easy chemical composition control and compatibility for large-scale roll-to-roll production [3], [4]. Most recently, solution processed high-k dielectrics have been fabricated at low temperature [5], [6]. However, the insulating property of the low temperature processed dielectric films are far from satisfactory [7]. Although the photo-assisted low temperature annealing is reported to produce high insulating dielectric films, the additional thermal annealing process adds com- plexity to the process may limit the scalable production [8].

In addition, the low temperature process is still not compatible with special flexible substrate like paper and may induce thermal deformations in flexible substrate like PET. The fabrication of high performance flexible devices at room temperature is thus challenging, as a tradeoff must be found between the processing temperature and the device performance [9].

Among high-k materials, zirconium oxide is an obvious ideal candidate for OTFT because it uniquely combines excellent thermal, chemical and mechanical stability as well as a theoretical high-k value (25) [10], [11]. In this work, we successfully fabricated high quality ZrO2films by low cost solution process at room temperature. We carried out a systematic study on the impact of UV curing time on the microstructure and electrical performance of solution processed ZrO2 films.

Pentacene OTFTs with low operation voltage were finally fabricated at room temperature.

II. EXPERIMENTALSECTION

The 0.15 mol/L ZrO2solution was prepared by dissolving

∼0.7 g zirconium (IV) acetylacetonate powder into 10 mL N, N-dimethylformamide solvent in a glove box. Then, the solution was stirred at 90 °C for 32 h. The ZrO2 film was deposited by spin-coating at 500 rpm for 5 s and 2000 rpm for 40 s on a p-type silicon or polyethylene terephthalate (PET) substrates. After several coating cycles with a pre-curing under a Hg UV lamp (185 and 245 nm) at room temperature for 20 min, the ZrO2 film was finally UV irradiated for 30, 60, and 120 min, hereafter named U30, U60, and U120 samples, respectively. Another process, after several coating cycles with a pre-annealing on a hot plate at 160 °C for 10 min, the films were finally annealed at 160 °C for 1h (hereafter named T160).

Transistors were fabricated by firstly thermally evaporating on PET substrate a 40 nm thick gold (Au) electrode acting as the bottom gate. Then ZrO2 film was fabricated and annealed

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

(2)

GONGet al.: ROOM TEMPERATURE FABRICATION OF HIGH QUALITY ZrO₂DIELECTRIC FILMS 281

Fig. 1. Cross sectional HRTEM images of ZrO₂ films with various annealing conditions:(a)and(d)T160;(b)and(e)U60;(c)and(f)U120.

by using the above mentioned methods. Then, poly-α-methyl styrene (PαMS) with ∼10 nm thickness was spin coated, which is aim to reduce the surface energy of ZrO2surface and improve the grain size of the pentacene film [7]. Furthermore, the PαMS layer will also passivate the OH group on ZrO2

surface, and eliminate the hysteresis in the drain current- gate voltage (IDS-VGS) curve. Pentacene film with 40 nm thicknesses was thermally evaporated to form the organic semiconductor layer. Finally, a 40 nm thick Cu source/drain electrode was thermally evaporated on the pentacene layer with a shadow mask, which finally defined a bottom-gate and top-contact OTFT device with channel width/length of 750 μm/50μm.

III. RESULTS ANDDISCUSSION

Although the solution processing conditions were identical, high resolution transmission electron microscopy (HRTEM) images show that the ZrO2 film thickness was considerably influenced by the post-deposition annealing. As shown in Fig. 1a-c, T160 has a thickness of ∼60.8 nm, while U60 and U120 have thicknesses of 50.2 nm and 35.1 nm, respectively.

We conclude that the UV-curing results in a more efficient densification of ZrO2film with respect to the thermal annealing. HRTEM images shown in Fig. 1d-f clearly indicate the presence of an interface layer between the ZrO2 and the Si substrate. Assuming the initial existence of a native SiO2

layer (∼2 nm), a clear formation of the thicker interface layer occurs in U120 (corresponding to 3.7 nm), which suggests that the oxidization of Si substrate occurs due to reactive oxygen species generated by the UV irradiation or by the photolysis of Zr-based sol-gel layer [12], [13]. However, there is no obvious increase in the interface layer thickness for T160 (2.4 nm) or U60 (2.1 nm) samples, suggesting that the oxidization of the Si substrate cannot easily occur for low thermal annealing temperature or for short (up to 1 h) UV treatments.

Fig. 2a shows a comparison of the leakage current density for the different Cu/ZrO2/Si capacitors. T160 sample exhibits a leakage current density of ∼3.6×10⁻⁵ A/cm² at −3 V, while U60 sample shows nearly one order of magnitude lower leakage current density of 1.8×10⁻⁶ A/cm². The inset of Fig. 2ashows a high breakdown electric field of∼7.9 MV/cm for U60. Fig. 2b shows the frequency dependence of the areal capacitance. The frequency dependence of the areal capacitance is assumed to be mostly induced by the series resistance of the Si substrate [14]. The areal capacitance of UV-cured ZrO2films is higher than that of thermally annealed films and it increases with the curing time. The capacitance

Fig. 2. The electrical properties of ZrO₂films with different annealing conditions: (a) Leakage current characteristics; The inset of Fig. 2a shows the breakdown electrical field characteristics; (b) Frequency dependent areal capacitance.

at 1 k Hz is ∼116 nF/cm² for T160 and ∼261 nF/cm² for U60. According to the thicknesses of ZrO2 films and SiO2determined from HRTEM (Fig. 1), the relative dielectric constants (k) of ZrO2 are 17.8 for U60 and 8.7 for T160.

The theoretical dielectric constant (k) value for ZrO2 is different with different crystal structures. It is∼20 (monoclinic),

∼37 (cubic), and∼47 (tetragonal) [15]. While the theoretical k value is∼22 for the amorphous phase [16]. The k value of 17.

8 for amorphous U60 sample is close to that of the reported results [16], [17]. The relatively low k value of T160 was ascribed to the presence of more organic residuals in the film [18], which have lower atomic density and hence smaller electronic and ionic polarizations.

To further understand the different electrical properties of ZrO2 films by UV curing and thermal annealing, their electronic structures were investigated by XPS.Fig. 3ashows the O1s spectra of ZrO2films, from which their band gap can be extracted by using the methods reported by Xu et al. [19].

The band-gaps of ZrO2 films are 5.45 eV (T160), 5.76 eV (U30), 6.13 eV (U60) and 5.89 eV (U120), respectively. The band gap of U60 is larger than that of ZrO2 films deposited by sputtering [20], electron beam evaporation [21], and even atomic layer deposition [22]. The band structure is more dominated by its crystal structure for crystalline ZrO2, while it is often dominated by oxygen vacancies for amorphous ZrO2 films [23]. The high band gap value observed in the U60 sample can be attributed to a relatively small quantity of oxygen vacancies in UV curved films, in which the excess O³ and O^∗ absorbed in the ZrO2 thin films can effectively fill the oxygen vacancies [12], [23]. The valence band spectra of Au and ZrO2 thin films were also measured (results not shown here), in which the valence band structure of Au was used as the reference for calculating the electronic structure of

(3)

282 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 2, FEBRUARY 2018

Fig. 3. (a)O 1s electron energy loss spectroscopy,(b)a schematic diagram of electron band structure of ZrO₂ films with different post- deposition treatments.

ZrO2 films. By using the same method proposed by Liao et al. [24], the electronic structure of ZrO2 films was calculated. Fig. 3b summarizes the corresponding detailed band offset values for these thermal annealed and UV-cured ZrO2films. The above results suggest that UV irradiation will significantly affect the electronic structures of the ZrO2films.

Based on the above results, it looks that a longer UV annealing time will degrade the film quality. We ascribed this effect to the following reaction mechanism occurring in the ZrO2

films under UV irradiation. The first process is a relatively fast photolysis of the precursor by the UV irradiation. The second process is a slower densification of the thin film due to the oxidation by reactive oxygen species (O^∗) [12]. UV irradiation is beneficial to promote the polycondensation and to remove impurities, resulting in the densification of the sol-gel-derived metal-oxide films [25]. However, an excessive illumination time will promote additional decomposition reactions in the film, inducing the cracking of the membranes and introducing new impurities leading to the reduction of the Zr-O-Zr con- tent, thus changing the electronic structure and degrading the electrical performance of ZrO2 films.

Fig. 4a shows the schematic diagram of the ZrO2-OTFT device structure used in our work. The inset of Fig. 4b shows the photograph of the OTFT device on PET substrate.

Fig. 4b shows the typical transfer curve of the ZrO2-OTFTs with 1 hour UV irradiated. The room temperature fabricated ZrO2-OTFT exhibited excellent device performance including a field-effected mobilityμ of 0.88 cm²/V·s, threshold voltage of−1.16 V, and a high on/off ratio of 3.1×10⁶. The negligible hysteresis between forward and backward scans indicates that the interface between the dielectric and the channel layer has

Fig. 4. (a)A schematic diagram of the bottom-gate with top-contact ZrO₂-OTFT;(b)The typical I_DS-V_GScharacteristics and(c)the typical I_DS-V_DScharacteristics of the room temperature fabricated ZrO2-OTFT device. The inset of Fig. 4b shows the photograph of the actual ZrO₂-OTFT device.

a high quality with a low density of traps [26]. A compara- tively high subthreshold swing of 0.2 V/decade was observed, which may be related to the trivial charge trapping in the polymer electret PαMS layer. We found that room temperature fabrication can effectively prevent the thermal deformation of the PET substrate and improve the interfacial adhesion, which significantly enhances the viability for future flexible electronic devices. It should be noticed that the increase of off state current near VGSof 0 V is assumed to be due to the overlap between the drain and gate [27]. We can also see a clear difference of the IDS-VGScharacteristics around VGSof

−0.5 V, which is mostly due to the difference of the depletion width in the pentacene channel under two different sweeping directions. It is interesting that a smaller drain current value was observed in the IDS-VDScurve when compared with that in the IDS-VGS curve at the same gate voltage and drain voltage. The reason is still not clear now. It may be related to the varied charge transport in the organic semiconductor or its interface with insulator during the different voltage scanning cycles.

The low operation voltage of ZrO2-OTFT shown inFig. 4is ascribed to the high dielectric constant and low leakage current of the solution processed ZrO2films [28]. It should be noticed that, for OTFTs, other factors such as channel carrier mobility, metal/semiconductor contact resistance, and insulator/semiconductor interface may also play important roles on the performance of OTFTs including operation voltages [29]. In our work, we specially focus on the effect from the dielectric layer. For OTFTs with same device configurations except for dielectric layer materials, the SiO2-OTFT shows much higher operation voltage, which is usually larger than 10 V in most of the reported devices [30], [31]. In our work (results not shown here), the 50 nm ZrO2-OTFT shows drain current saturation at a small gate voltage of −5 V, while it needs a high gate voltage of−30 V to reach drain current saturation for a 50 nm SiO2-OTFT device with the same device configuration.

(4)

GONGet al.: ROOM TEMPERATURE FABRICATION OF HIGH QUALITY ZrO₂DIELECTRIC FILMS 283

REFERENCES

[1] G. Liu, A. Liu, F. Shan, Y. Meng, B. Shin, E. Fortunato, and R. Martins,

“High-performance fully amorphous bilayer metal-oxide thin film transistors using ultra-thin solution-processed ZrOxdielectric,” Appl. Phys.

Lett., vol. 15, no. 11, p. 113509, Sep. 2014, doi:10.1063/.1.4895782.

[2] M. R. Beaulieu, J. K. Baral, N. R. Hendricks, Y. Tang, A. L. Briseno, and J. J. Watkins, “Solution processable high dielectric constant nanocom- posites based on ZrO2 nanoparticles for flexible organic transistors,”

ACS Appl. Mater. Interfaces, vol. 5, no. 24, pp. 13096–13103, Dec. 2013, doi:10.1021/am404129u.

[3] X. Xu, Q. Cui, Y. Jin, and X. Guo, “Low-voltage zinc oxide thin-film transistors with solution-processed channel and dielectric layers below 150° C,” Appl. Phys. Lett., vol. 101, no. 22, p. 222114, Nov. 2012, doi:10.1063/1.4769091.

[4] Y. Meng, C. Ling, R. Xin, P. Wang, Y. Song, H. Bu, S. Gao, X. Wang, F. Song, J. Wang, X. Wang, B. Wang, and G. Wang, “Repairing atomic vacancies in single-layer MoSe2 field-effect transistor and its defect dynamics,” NPJ Quantum. Mater., vol. 2, no. 16, pp. 1–5, Mar. 2017, doi:10.1038/s41535-017-0018-7.

[5] Y. S. Rim, H. Chen, X. Kou, H.-S. Duan, H. Zhou, M. Cai, H. J. Kim, and Y. Yang, “Boost up mobility of solution-processed metal oxide thin-film transistors via confining structure on electron pathways,” Adv. Mater., vol. 26, no. 25, pp. 4273–4278, Jul. 2014, doi:10.1002/adma.201400529.

[6] W. Xu, H. Wang, L. Ye, and J. Xu, “The role of solution-processed high-k gate dielectrics in electrical performance of oxide thin-film transistors,” J. Mater. Chem. C, vol. 2, no. 27, pp. 5389–5396, Jul. 2014, doi:10.1039/c4tc00334a.

[7] W. He, W. Xu, Q. Peng, C. Liu, G. Zhou, S. Wu, M. Zeng, Z. Zhang, J. Gao, X. Gao, X. Lu, and J. M. Liu, “Surface modification on solution processable ZrO₂high-k dielectrics for low voltage operations of organic thin film transistors,” J. Phys. Chem. C, vol. 120, no. 18, pp. 9949–9957, May 2016, doi:10.1021/acs.jpcc.6b03638.

[8] J. Hwang, K. Lee, Y. Jeong, Y. U. Lee, C. Pearson, M. C. Petty, and H. Kim, “UV-assisted low temperature oxide dielectric films for TFT applications,” Adv. Mater. Interfaces, vol. 1, no. 8, p. 1400206, Nov. 2014, doi:10.1002/admi.201400206.

[9] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono,

“Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, no. 4016, pp. 488–492, Nov. 2004, doi:10.1038/nature03090.

[10] S. Dutta, A. Pandey, I. Yadav, O. P. Thakur, A. Kumar, R. Pal, and R. Chatterjee, “Growth and electrical properties of spin coated ultrathin ZrO2 films on silicon,” J. Appl. Phys., vol. 114, no. 1, p. 014105, Jul. 2013, doi:10.1063/1.4812733.

[11] X. Li, E. Xin, and J. Zhang, “Low-temperature solution-processed zirconium oxide gate insulators for thin-film transistors,” IEEE Trans.

Electron. Devices, vol. 60, no. 10, pp. 3413–3416, Oct. 2013, doi:10.1109/TED.2013.2278206.

[12] Y. M. Park, A. Desai, A. Salleo, and L. Jimison, “Solution-processable zirconium oxide gate dielectrics for flexible organic field effect transistors operated at low voltages,” Chem. Mater., vol. 25, no. 13, pp. 2571–2579, Jul. 2013, doi:10.1021/cm303547a.

[13] Y. M. Park, J. Daniel, M. Heeney, and A. Salleo, “Room-temperature fabrication of ultrathin oxide gate dielectrics for low-voltage operation of organic field-effect transistors,” Adv. Mater, vol. 23, no. 8, pp. 971–974, Feb. 2011, doi:10.1002/adma.201003641.

[14] K. J. Yang and C. Hu, “MOS capacitance measurements for high- leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500–1501, Jul. 1999, doi:10.1109/16.772500.

[15] X. Zhao and D. Vanderbilt, “Phonons and lattice dielectric properties of zirconia,” Phys. Rev. B, Condens. Matter, vol. 65, no. 7, p. 075105, Feb. 2002, doi:10.1103/PhysRevB.65.075105.

[16] X. Zhao, D. Ceresoli, and D. Vanderbilt, “Structural, electronic, and dielectric properties of amorphous ZrO₂ from ab initio molecular dynamics,” Phys. Rev. B, Condens. Matter, vol. 71, no. 8, p. 085107, Feb. 2005, doi:10.1103/PhysRevB.71.085107.

[17] W. Xu, H. Wang, L. Ye, and J. Xu, “The role of solution-processed high-k gate dielectrics in electrical performance of oxide thin-film transistors,” J. Mater. Chem. C, vol. 2, no. 27, pp. 5389–5396, Jul. 2014, doi:10.1039/c4tc00334a.

[18] G. Liu, A. Liu, Y. Meng, F. Shan, B. Shin, W. Lee, and C. Cho,

“Annealing dependence of solution-processed ultra-thin ZrOxfilms for gate dielectric applications,” J. Nanosci. Nano. Techno., vol. 15, no. 3, pp. 2185–2191, Mar. 2015, doi:10.1166/jnn.2015.10228.

[19] W. Xu, Y. Zhang, Z. Tang, Z. Shao, G. Zhou, M. Qin, M. Zeng, S. Wu, Z. Zhang, J. Gao, X. Lu, and J. Liu, “Electronic structure and charge-trapping characteristics of the Al₂O₃-TiAlO-SiO₂gate stack for nonvolatile memory applications,” Nanoscale Res. Lett., vol. 12, p. 270, Apr. 2017, doi:10.1186/s11671-017-2040-x.

[20] C. V. Ramana, R. S. Vemuri, I. Fernandez, and A. L. Campbell, “Size-effects on the optical properties of zirconium oxide thin films,” Appl. Phys. Lett., vol. 95, no. 23, p. 231905, Dec. 2009, doi:10.1063/.1.3271697.

[21] C. C. Fulton, G. Lucovsky, and R. J. Nemanich, “Electronic properties of the Zr–ZrO2–SiO2–Si(100) gate stack structure,” J. Appl. Phys., vol. 99, no. 6, p. 063708, Mar. 2006, doi:10.1063/1.2181282.

[22] E. Bersch, S. Rangan, and R. A. Bartynski, “Band offsets of ultrathin high-k oxide films with Si,” Phys. Rev. B, Condens. Matter, vol. 78, no. 8, p. 085114, Aug. 2008, doi:10.1103/PhysRevB.78.085114.

[23] S. Chang and R. Doong, “Interband transitions in sol–gel-derived ZrO₂ films under different calcination conditions,” Chem. Mater., vol. 19, no. 19, pp. 4804–4810, Sep. 2007, doi:10.1021/cm070606n.

[24] L. S. Liao, M. K. Fung, C. S. Lee, S. T. Lee, M. Inbasekaran, E. P. Woo, and W. W. Wu, “Electronic structure and energy band gap of poly (9,9-dioctylfluorene) investigated by photoelectron spectroscopy,” Appl. Phys. Lett., vol. 76, no. 24, pp. 3582–3584, Jun. 2000, doi:10.1063/.1.126713.

[25] S. Park, Y. J. Jeong, Y. Baek, L. H. Kim, J. H. Jang, Y. Kim, T. K. An, S. Nam, S. H. Kim, J. Jang, and C. E. Park, “Reduced water vapor transmission rates of low-temperature solution-processed metal oxide barrier films via vltraviolet annealing,” Appl. Surf. Sci., vol. 414, pp. 262–269, Apr. 2017, doi:10.1016/j.apsusc.2017.04.100.

[26] J. Y. Na, B. Kang, D. H. Sin, K. Cho, and Y. D. Park, “Understanding solidification of polythiophene thin films during spin-coating: Effects of spin-coating time and processing additives,” Sci. Rep., vol. 5, p. 13288, Aug. 2015, doi:10.1038/srep13288.

[27] Q. H. Li and S. Sakai, “Characterization of Pt/SrBi2Ta2O9/ Hf-Al-O/Si field-effect transistors at elevated temperatures,” Appl. Phys.

Lett., vol. 89, no. 22, p. 222910, doi:10.1063/1.2399351.

[28] F. Liu, Y. Zhou, Y. Wang, X. Liu, J. Wang, and H. Guo,

“Negative capacitance transistors with monolayer black phosphorus,”

NPJ Quantum. Mater., vol. 1, p. 16004, Jul. 2016, doi: 10.1038/

npjquantmats.2016.4.

[29] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” J.

Appl. Phys., vol. 89, no. 10, pp. 5243–5275, May 2001, doi:10.1063/

1.1361065.

[30] Y.-Y. Lin, D. J. Gundlach, S. F. Nelson, and T. N. Jackson, “Stacked pentacene layer organic thin-film transistors with improved characteristics,”

IEEE Electron Device Lett., vol. 18, no. 12, pp. 606–608, Dec. 1997, doi:10.1109/55.644085.

[31] H.-C. Wu and C.-H. Chien, “Improving electrical properties of bottom- gate poly (3-Hexylthiophene) thin-film transistor using CF4 plasma treatment,” IEEE. Electron. Device. Lett., vol. 34, no. 4, pp. 538–540, Apr. 2013, doi:10.1109/LED.2013.2244840.