第五章 總結與未來展望
5.2 未來展望
實驗結果證實吾人所設計出的結構除了能夠保持穿隧電晶體原有的特 性之外，在提升開電流的這個項目中，也成功的讓 n 型與 p 型穿隧電晶體的 開電流值達到 10-5 安培等級，與其他研究文獻的結果相較，我們的研究成果 擁有較理想的開電流值，因此算是成功達到初步的研究目標。基於本研究主 要著重於二維元件特性分析，因此未來希望往三維結構的方向進行研究。由 於 Trigate 的三維閘極包覆通道的結構特性，可增強閘極對通道的控制能力，
能夠進一步的增強其電場，另外 Trigate 結構特有的方形尖角形狀更能讓電 場有集中的特性，如此亦能進一步增強 Trigate 穿隧電晶體的電流穿隧效率，
且由於 Trigate 結構本質上是三維立體的通道，能夠三面導通，所以有益於 增加公式
(2.4)中的穿隧有效面積，並結合前面所提的異質接面造成的能隙
下降帶來的好處，因此未來發展重點便是可利用 Trigate 結構來進一步增強 穿隧電晶體的能帶至能帶的穿隧機率，使得本研究的元件能更進一步的性能 提升。並嘗試結合現有的金氧半場效電晶體技術，設計出具有理想特性的穿 隧型場效電晶體，使穿隧型場效電晶體能夠應用的領域更加廣闊。參考文獻
[1] S.Y. Wu, C. Y. Lin and M. C. Chiang, “A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications,” Electron Devices Meeting, pp. 224-227, 2013.
[2] C. Auth, “22 nm Fully-depleted Tri-gate CMOS Transistors,” CICC, pp. 1-6, 2012.
[3] K. Henson, H. Bu, M. H. Na and Y. Liang, “Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology Using High-κ/Metal Gate,” Electron Devices Meeting, pp. 645-648, 2008.
[4] T. Y. Hsieh, “Self-Aligned Patterning with Implantation,” U.S. Patent, pp. 65nm Technology,” IEEE International Electron Devices Meeting, pp.
1070-1071, 2005.
[7] C. Auth, A. Cappellani, J. S. H. Chun and A. Dalis, “45 nm high-κ/metal Gate Strain-enhanced Transistors,” VLSI Technology, pp. 128-129, 2008.
[8] P. Packan, S. Akbar, M. Amstrong and D. Bergstrom, “High Performance 32nm Logic Technology Featuring 2nd Generation High-κ/Metal Gate Transistors,” Electron Devices Meeting, pp. 659-663, 2009.
[9] C. H. Jan, U. Bhattacharya, R. Brain and R. Choi, “A 22 nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate Optimized for
Electron Devices Meeting, pp. 1-3, 2012.
[10] S. Natarajan, M. Agostinelli, S. Akbar and A. Bowonder, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Air-Gapped Interconnects Self-aligned Double Patterning and a 0.0588 µm2 SRAM Cell Size,”
Electron Devices Meeting, pp. 3-7, 2014.
[11] 劉傳璽，陳進來，第三版，半導體物理元件與製程-理論與實務，五南文 化出版社，2006。
[12] M. Bhohr and K. Mistry, intel.com, http://goo.gl/jWz3fO, 2011.
[13] N. Patel, A. Ramesh and S. Mahapatra, “Drive Current Boosting of n-type Tunnel FET with Strained SiGe Layer at Source,” Microelectronics Journal, vol. 39, pp. 1671-1677, 2008.
[14] S. M. Sze, “Physics of Semiconductor Devices,” Wiley, 1969.
[15] Q. Huang, R. Huang and Z. Zhan, “Performance Improvement of Si Pocket-Tunnel FET with Steep Subthreshold Slope and High Ion/Ioff Ratio,”
Solid-State and Integrated Circuit Technology, pp. 1-3, 2012.
[16] F. Mayer, R. Le and J. F. Damlencourt, “Impact of SOI, Si1-xGexOI and GeOI Substrates on CMOS Compatible Tunnel FET Performance,” Electron Devices Meeting, pp. 1-5, 2008.
[17] N. Dang, and C. H. Shih, “Short-Channel Effect and Device Design of Extremely Scaled Tunnel Field-effect Transistors,” Microelectronics Reliability, pp. 31-37, 2015.
[18] M. S. Kim, H. Liu and V. Narayanan, “A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter,” Electron Devices, IEEE Transactions, pp. 3661-3667, 2014.
Low-Power Heterojunction Tunnel FET SRAM Design,” IEEE Computer Society, pp. 45-52, 2011.
[20] S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect,” Electron Device Letters, IEEE, pp. 791-794, 2014.
[21] S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Tunnel Field Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes,” Japanese Journal of Applied Physics, 04CC25, 2013.
[22] S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Synthetic Electric Field Tunnel FETs: Drain Current Multiplication Demonstrated by Wrapped Gate Electrode around Ultrathin Epitaxial Channel,” International Symposium on VLSI Technology, Systems and Applications, pp. 236-237, 2013.
[23] J. H. Seo, Y. J. Yoon, S. Lee and J. H. Lee “Design and Analysis of Si-based Arch-shaped Gate-all-around Tunneling Field Effect Transistor,” Current Applied Physics, pp. 208-212, 2015.
[24] J. D. Jackson, “Classical Electrodynamics Semiconductor,” Wiley, 1975.
[25] 韓雁，第一版，半導體器件TCAD設計與應用，電子工業出版社，2013。
[26] Synopsys, TCAD Sentaurus Device Manual, H-2013.03, 2013.
[27] M. D. Martino, J. A. Martino and P. G. Agopian, “Drain Induced Barrier Thinning on TFETs with Different Source/Drain Engineering,”
Microelectronics Technology and Devices, pp. 1-4, 2014.