本研究計畫內容主要分為兩部分,第一部份著重於探討氮化鎢閘極中,含氮量的多寡 對於閘極電極之影響,其中研究的方向為改變氮化鎢閘極的含氮量,觀察其對於閘極功函 數值之改變,閘極的熱穩定性及閘極電極與氧化層界面之影響。此研究成果提供以氮化鎢 薄膜應用於閘極電極時,其氮與鎢的最佳成分比及其特性表現。
而計畫的第二部分主要為研究氮化鎢閘極與 Ta2O5 氧化層之界面,於不同溫度與氣氛 下熱處理後,其界面反應及電性的變化。研究成果提供氮化鎢薄膜應用於閘極電極及高介 電常數材料應用於閘極氧化層之特性表現,並可瞭解閘極電極與高介電常數氧化層其界面 之基本材料科學。
本計畫研究成果,已撰寫論文為”Effects of post-metal annealing on the electrical characteristics and thermal stability of W2N/Ta2O5/Si MOS capacitors”,發表於 Journal of the Electrochemical Society 151, G751 (2004),另一篇為 “Influence of nitrogen content in WNx on its thermal stability and electrical property as a gate electrode”, 亦已投稿於 Journal of the Electrochemical Society,已經過 first review,目前狀態為 after revision。
9. 附錄: 已發表論文
(Submitted to JES, after revision)
Influence of nitrogen content in WN
xon its thermal stability and electrical property as a gate electrode
Pei-Chuen Jiang and J. S. Chena)
Department of Materials Science and Engineering, National Cheng Kung University Tainan, Taiwan
a) Electronic mail: [email protected]
Abstract
The effects of nitrogen concentration on the thermal stability and electric property of the WNx film as the gate electrode is investigated. WNx is deposited by using reactive rf sputtering and films with composition of WN0.6, WN0.8 and WN1.5 are obtained at 10%, 25% and 40% of N2
partial flow ratio, respectively. The crystal structure of the WN0.6 film indicates that this film is a mixture of W+W2N, while WN0.8 and WN1.5 films both show the W2N phase. After annealing in N2+H2 (N2:H2=9:1) ambient at 500oC, the surface of the WN0.6 film reveals only the W-O bonding, but no W-N bonding. In addition, oxygen diffused from SiO2 into WN0.6 and leads to the formation of a mixing layer. Subsequently, flatband voltage (VFB) of the MOS capacitor shifts positively after annealing at 500oC. After annealing at 500oC, WN0.8 and WN1.5 films exhibit better resistance to oxidation than the WN0.6 film, regardless of the surface of the WNx film or the interface between WNx and SiO2. Sheet resistance of all WNx films increases after annealing and that also increases with increasing nitrogen content in the WNx films. However, neither the nitrogen content in the WNx nor the post-metal annealing affect the leakage current of WNx/SiO2/Si capacitors at both positive and negative biases.
I. Introduction
The dimension of complementary metal oxide semiconductor (CMOS) devices shrinks continuously in order to improve the electrical performance. At the same time, the choice of the gate electrode materials becomes an important issue. The conventional poly-silicon gate electrode of CMOS devices suffers several problems, such as gate depletion and boron penetration into the channel region [1-4]. Gate depletion decreases the capacitance of the device and degrades the driving capability of channel current [1,2]. Boron penetration in p-channel metal oxide semiconductor field effect transistor (PMOSFET) reduces the control of threshold voltage and gate oxide reliability [3,4]. Therefore, metals or metal nitrides will be interesting materials for gate electrode application.
As a gate electrode, its work function, resistivity, and compatibility with CMOS technology
On the other hand, the thermal stability of TiN [10-13], WNx [13, 14], TaN [15], Ta [16], TaSixNy
[17], and WSix [18] have been discussed to see their compatibility with gate electrode process.
Unfortunately, metal nitrides generally exhibit high resistivity. However, resistivity of gate electrode can be reduced by the stacking structure, such as W/TiN [19-21], W/WNx [20], Ta/TaNx
[22].
Therefore, the literature suggests that metal nitrides are approved materials as gate electrodes. Nevertheless, nitrogen concentration and structure of metal nitride gate electrodes are not fully explored in previous studies. In this study, WNx and SiO2 are chosen as the gate electrode and gate dielectric of MOS capacitors, respectively. The WNx represents three W-nitride films of different nitrogen contents. Thermal stability and electrical property of WNx/SiO2/Si MOS capacitors are investigated after prolonged (30 min) post-metal annealing at 400-600oC in N2+H2 ambient. The phase and microstructure, compositional depth profiles and chemical bonding states of the WNx electrode, as well as the WNx/SiO2 interface after post-metal annealing are investigated. The connection between material characteristics and the electrical performance of WNx/SiO2/Si MOS capacitors is also discussed.
II. Experimental procedures
The substrate used in this study is n-type Si (100) wafer with a resistivity of 1-10 Ω-cm. The silicon wafer was cleaned in organic baths and chemically etched with diluted HF solution, followed by thermal oxidation in a quartz tube furnace at 1050oC. Thickness of resulting SiO2
films was determined by a spectroscopic ellipsometer and the value is 25nm.
The WNx film was then deposited on the SiO2 layer by reactive magnetron sputtering using a W target (2 inches diameter, 99.9% purity). The base pressure of the chamber was 3×10-6 Torr and the working pressure was 7 mTorr. The total gas (Ar+N2) flow rate was kept at 100 sccm and the N2 partial flow rate (the ratio of N2 flow rate to the total flow rate) was set at 10, 25 and 40%
to fabricate WNx films of three different compositions. The rf power supplied to the target was 150 W and the substrate holder was neither cooled nor heated externally, but applied with a negative 100V DC bias. Depending on the N2 partial flow rate, the resulting WNx film thickness varies from 160 nm to 180 nm, as examined by scanning electron microscope (SEM) on the sample cross section.
After the WNx/SiO2/Si structure was completed, post-metal annealing was carried out in a quartz tube furnace at 400-600oC in N2+H2 ambient (N2 flow rate=135 sccm and H2 flow rate=15 sccm) for 30 min, to investigate the thermal stability. Atomic ratio of N/W in the films was determined by Rutherford back scattering spectrometry (RBS) with 2 MeV He+ ion beams. The phase transformation after post-metal annealing was investigated by glancing incident angle X-ray diffraction (GIAXRD) with the Cu
Κα
radiation (λ=0.1542 nm) and an incident angle of 2o. The microstructure of WNx and WNx/SiO2 interface was examined by high resolution transmission electron microscopy (HRTEM). Auger electron spectrometry (AES) was used to characterize the distribution of elements after the post-metal annealing. Chemical bonding states of the samples were investigated using x-ray photoelectron spectroscopy (XPS) with MgΚα
radiation (1253.6eV). Sheet resistance of WNx was measured by a four-point probe. The MOS capacitors were characterized electrically using a computer-controlled HP 4284 LCR meter forhysteresis loops, at a frequency of 100 kHz with a small ac signal of 25 mV. The current densities were measured by an HP 4140B pA meter/DC voltage source.
III. Results and Discussion
A. Material characteristics of WN
xfilm on SiO
2, as deposited and after annealing
The W:N ratios of WNx films is analyzed by using RBS and the details was reported in our previous work [23]. With 10%, 25% and 40% of N2 partial flow ratio during sputtering, the W:N ratio of WNx film are 1:0.6, 1:0.8 and 1:1.5, respectively. Accordingly, WNx films sputtered at 10%, 25% and 40% N2 partial flow ratio are referred to as WN0.6, WN0.8 and WN1.5 films, respectively.
Figures 1(a), (b) and (c) show the GIAXRD spectra of WN0.6, WN0.8 and WN1.5 films after annealing at various temperatures, respectively. The diffraction peaks of as-deposited WN0.6 film are associated with (111), (200), (220), and (311) diffractions of W2N (ICDD PDF 25-1257) and a broaden (110) diffraction of bcc-W at 2θ≒40o (ICDD PDF 04-0806) (Fig. 1(a)), indicating that the WN0.6 film is a W+W2N mix phase. The diffraction peaks nearby 2θ=40o of as-deposited, 400oC and 500oC annealed WN0.6 films are deconvoluted and shown in Fig. 2(a), (b) and (c), respectively. The deconvolution indicates that the crystal structure of 400oC and 500oC annealed samples are still a mixture of W+W2N. Neither W nor W2N exhibits sharp crystallization. After annealing at 600oC (Fig. 1(a)), the WN0.6 film shows improved crystallinity and the diffraction peaks are associated with W2N, bcc-W and WO3 (ICDD PDF 83-0947) phases. In Fig. 1(b), the diffraction peaks of as-deposited and 400-500oC annealed WN0.8 films are pertaining to (111), (200), (220), and (311) planes of W2N and these peaks are significant and sharp, indicating that the WN0.8 film exhibits good crystallinity. After annealing at 600oC, additional diffraction peaks pertaining WO3 structure are observed, but they are not as significant as those seen in the 600oC-annaled WN0.6. As for the XRD patterns of WN1.5 films (Fig. 1(c)), they are similar to the patterns of WN0.8; however, all peaks shift a little to the lower angle because the W2N lattices expand slightly due to the high concentration of nitrogen in the WN1.5 film. Peaks of WO3 are also observed in the WN1.5 film after annealing at 600oC. Oxidation of WNx after annealing at 600oC was caused by residual oxygen in the annealing furnace. As a consequence, the WN0.6 film will be oxidized more easily because it partly contains the metallic W phase.
Both WN0.8 and WN1.5 films exhibit the W2N phase according to their XRD patterns (Fig.
1(b) and (c)). However, the difference in sharpness of diffraction peaks suggests that the microstructure of the two films should not be the same. Figures 3(a) and (b) present the bright-field TEM micrographs of the WN0.8 and WN1.5 films after annealing at 500oC, respectively. The micrographs clearly indicate that the grain size of the WN0.8 film (~22nm) is greater than that of the WN1.5 film (~9nm). The reduction in grain size for the WN1.5 film is also expressed in the broadening of the corresponding X-ray diffraction peaks.
Although the stoichiometry of W2N phase is W:N=1:0.5, the near-stoichiometric sputtered WNx film (WN0.6 in this study) still contains metallic W and does not show apparent W2N
nitrogen atoms may exist interstitially in the lattices, or locate along the grain boundaries.
Surface chemical bonding states of 500oC annealed WNx films are examined by XPS and the W 4f spectra are shown in Fig. 4. The low-energy side doublet is associated with the W 4f7/2
and W 4f5/2 peaks of nitrogen-bonded W and high-energy side doublet is associated with the W 4f7/2 and W 4f5/2 peaks of oxygen-bonded W. The intensity of the W 4f7/2 and W 4f5/2 peaks of nitrogen-bonded W increases with increasing N2 flow ratio, and oxygen-bonded W peaks of 500oC annealed WN0.6 film are the most significant among the three. It is clear that the WNx film with high nitrogen content has the better ability to prevent the oxidation after annealing than the WNx film with low nitrogen content. The heats of formation for W2N and WO3 are -17 and -200 kcal/mol, respectively [24]. Although the oxidation of W2N is thermodynamically favored, W atoms in a N-rich environment are more resistant to oxidation.
To further understand whether the oxidation of WNx occurs only on the surface or across the whole film, we have carrier out the elemental depth profiling on the 500oC annealed WNx
films by using AES. Figures 5(a), (b) and (c) show the AES depth profiles of the WN0.6/SiO2/Si, WN0.8/SiO2/Si and WN1.5/SiO2/Si samples after annealing at 500oC, respectively. It is clear that the oxidation of WNx is limited on the surface and it is most significant for the WN0.6 film (Fig.
5(a)). In addition, Fig. 5(a) also indicates that oxygen diffuses from SiO2 to WN0.6 film after annealing at 500oC. In contrast, the interfaces of WN0.8/SiO2 and WN1.5/SiO2 remain sharp after annealing at 500oC (Fig. 5(b) and (c)). When comparing the AES profiles of as-deposited (not shown) and 500oC annealed WNx films, we have found that the intensities of W and N signals in the bulk of WNx films (not including the oxidized regions) remain unchanged before and after annealing. Although the surface of WNx films is oxidized, the composition inside WNx films is stable after annealing at 500oC.
Diffusion of oxygen at the interface between WN0.6 and SiO2 is further investigated by using HRTEM. Figure 6 shows the high resolution TEM micrograph on the WN0.6/SiO2 interface after annealing at 500oC. The micrograph indicates that a layer of different contrast and non-uniform thickness lies between WN0.6 and SiO2. This interlayer should correspond to the oxygen diffusing layer observed in the AES depth profiles (Fig. 5(a)).
B. Electric properties of WN
x/SiO
2/Si MOS capacitor
To determine whether the nitrogen content in WNx affects its electrical properties, we have carried out sheet resistance, hysteresis C-V and I-V measurements on the WNx/SiO2/Si structure.
Because the WNx films are oxidized after annealing at 600oC, the electrical properties are measured on the samples which were annealed at the temperature of 500oC or lower. sheet resistance (Rs) values of WNx films of various compositions, as deposited and after annealing, are listed in Table 1. Thickness of the WNx films are also listed in Table 1. Thickness of the WN0.6
film increases slightly with increasing annealing temperature, which is attributed to the oxidation of the WN0.6 film. However, the thickness of the WN0.8 and WN1.5 films is independent of the annealing temperature. Rs of all WNx films increases after annealing, suggesting that oxidation of the WNx surface would increase the Rs of WNx films. Rs of WNx films also increases with increasing nitrogen content in the WNx films. With increasing nitrogen content in WNx, N atoms convert W atoms from the metallic state (more conductive) to the nitrided state (less conductive)
and the N atoms may also serve as incorporated impurities to increase the electron scattering;
therefore, the Rs increases with increasing nitrogen content in the WNx films.
Dielectric characteristics of the WNx/SiO2/Si structure are investigated by measuring the hysteresis C-V curves and I-V curves. Figures 7(a), (b) and (c) show the high frequency (100 kHz) hysteresis C-V curves of the as-fabricated and annealed WN0.6/SiO2/Si, WN0.8/SiO2/Si and WN1.5/SiO2/Si capacitors, respectively. The hysteresis offset is attributed to the charges within the dielectric layer (SiO2). The density of charges, Nh, can be calculated by the following equation [25]:
qA V
Nh CoxΔ fb,hysteresis
= (Eq. 1)
where Cox is the capacitance of the oxide layer, ΔVfb,hysteresis is the hysteresis offset of the flatband voltage, q is the electron charge, and A is the capacitor area. The values of Nh for all MOS capacitors are listed in the Table 2. Nh of all MOS capacitors decreases after annealing at 400oC, and slightly increases (as compared to the 400oC annealed one) after annealing at 500oC.
Hickmott [26] demonstrated that the surface states at the Si-SiO2 interface is created when annealing in H2 ambient above 450oC. Because the annealing ambient in this studying also contains H2 (N2:H2=9:1), the increase of Nh in the 500oC annealed samples, as compared to their corresponding 400oC annealed ones, can thus be attributed to the increase of surface states. To further understand whether the Nh affects the flat band voltage of the MOS capacitor, the relative shift of flat band voltage, ΔVFB, [ΔVFB = (VFB of the MOS after annealing) – (VFB of the as-fabricated MOS)] of samples after annealing is also listed in Table 2. The positive ΔVFB for all MOS capacitors after annealing can be attributed to the reduction of Nh for samples after annealing. Nh of all 500oC-annealed MOS capacitors is greater than that of their corresponding 400oC-annealed ones, indicating that ΔVFB of the 500oC-annealed samples shall be less positive.
This is true for the WN0.8 and WN1.5 capacitors; however, it is not in such a way for the WN0.6
capacitor. In the AES depth profiles, one can see that oxygen diffuses from SiO2 to WN0.6 film after annealing at 500oC (Fig. 5(a)), and the cross-sectional TEM micrograph indicates a mixing layer lying between SiO2 and WN0.6. The VFB of 500oC annealed WN0.6/SiO2/Si MOS capacitor shifts more positively, as compared to the 400oC annealed one, is therefore attributed to the increase of defects at the SiO2/WN0.6 interface.
With regard to the leakage current behavior, current density for all MOS capacitors at +1 and -1 MV/cm are listed in the Table 3. At +1 MV/cm electrical field, the leakage current density for all MOS capacitors is lower than 10-9 A/cm2. Under -1 MV/cm electrical field, the leakage current density of all MOS capacitors varies from 1×10-8 to 9×10-8, before and after annealing at 400oC and 500oC. Therefore, the post-metal annealing does not affect the leakage current of WNx/SiO2/Si capacitors at both positive and negative biases. Nevertheless, the leakage current at negative bias is generally higher than that at positive bias. Joo et. al. [27] reported that oxygen vacancy at the interface between the top electrode and the oxide layer resulted in the higher reverse current (applying negative bias to the electrode) than the forward current (applying
measured at +1 MV/cm, which can be attributed to the defects induced at the interface between SiO2 and WNx during the deposition of WNx by sputtering.
IV. Conclusion
Dependence of the material and electrical properties of sputtered WNx gate electrode on its nitrogen content is investigated. For three WNx films of different compositions (WN0.6, WN0.8
and WN1.5), the nitrogen concentration determines their phases, crystallinity, resistance to surface oxidation and interdiffusion at the WNx/SiO2 interface. Sheet resistance of WNx increases with increasing nitrogen content while C-V and I-V characteristics of WNx/SiO2/Si MOS capacitors are generally not sensitive to the nitrogen concentration of WNx. WN0.6 possesses a rather low sheet resistance but it has poor oxidization resistance and the interdiffusion at WN0.6/SiO2
interface upon post-metal annealing at 500oC will lead to the increase of defects in the MOS structure. On the other hand, WN1.5 is thermally stable but exhibits a high sheet resistance. As a consequence, the WN0.8 film shall be the optimum W-nitride gate electrode for practical application in MOS devices.
Acknowledgements
The authors gratefully appreciate the financial support from the National Science Council of Taiwan, R.O.C. (grant no. NSC 93-2216-E-006-015).
References
1. C. Leveugle, P. K. Hurley, A. Mathewson, S. Moran, E. Sheehan, A. Kalnitsky, A. Lepert, I.
Beinglass, M. Venkatesan, Microelectronic Engineering 36, 215 (1997).
2. W. –J. Cho, J. –E. Hong, W. –H. Jin, K. –S. Lee, S. –K. Rha, H. –S. Kim, Solid-State Electronics 44, 393 (2000).
3. K. S. Krisch, M. L. Green, F. H. Baumann, D. Brasen, L. C. Feldman, L. Manchanda, IEEE Trans. on Electron Devices 43, 982 (1996).
4. Z. J. Ma, J. C. Chen, Z. H. Liu, J. T. Krick, Y. C. Cheng, C. Hu, P. K. Ko, IEEE Electron Device Lett. 15, 109 (1994).
5. International Technology Roadmap for Semiconductors, 2001 editon, Semiconductor Industry Association.
6. R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, , IEEE Electron Device Lett. 23, 49 (2002).
7. T.-H. Cha, D.-G. Park, T.-K. Kim, S.-A. Jang, I.-S. Yeo, J.-S. Roh, and J. W. Park, Appl. Phys.
Lett. 81, 4182 (2002).
8. B.-Y. Tsui and C.-F. Huang, IEEE Electron Device Lett. 24, 153 (2003).
9. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, Mat. Res. Soc. Symp. Proc., 670, K5.1.1 (2001).
10. M. Wittmer, J. R. Noser, and H. Melchior, J. Appl. Phys. 54, 1423 (1983).
11. B. Claflin and G. Lucovsky, J. Vac. Sci. Technol. B 16, 2154 (1998).
12. E. K. Evangelou, N. Konofaos, X. A. Aslanoglou, C. A. Dimitriadis, P. Patsalas, S.
Logothetidis, M. Kokkoris, E. Kossionides, R. Vlastou, and R. Groetschel, J. Appl. Phys. 88,
7192 (2000).
13. B. Claflin, M. Binger, and G. Lucovsky, J. Vac. Sci. Technol. A 16, 1757 (1998).
14. P.-C. Jiang and J. S. Chen, J. Electrochem. Soc. 151, G751 (2004).
15. B. H. Lee, R. Choi, L. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. Jeon, W.-J. Qi, C. Kang, and J. C. Lee, Tech. Dig. of IEDM, p. 39 (2000).
16. T. Ushiki, K. Kawai, I. Ohshima, and T. Ohmi, IEEE Trans. Electron Devices, 47, 2201 (2000).
17. Y.-S. Suh, G. Heuss, H. Zhong, S.-N. Hong, and V. Misra, Symp. on VLSI Tech. Dig., p.47 (2001).
18. B. Sell, J. Willer, K. Pomplun, A. Sänger, D. Schumann, and W. Krautschneider, Microelectronic Eng. 55, 197 (2001).
19. D. H. Lee, K. H. Yeom, M. H. Cho, N. S. Kang, and T. E. Shim, Symp. on VLSI Tech. Dig., p.208 (1996).
20. I. H. Cho, J.-S. Park, D. K. Sohn, and J. H. Ha, Jpn. J. Appl. Phys. 40, 4854 (2001).
21. S. Youn, K. Roh, S. Yang, Y. Roh, K.-S. Kim, Y.-C. Jang, and N.-E. Lee, J. Vac. Sci. Technol.
A 19, 1591 (2001).
22. H. Shimada, I. Ohshima, S.-I. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, and T. Ohmi, Symp. on VLSI Tech. Dig., p.67 (2001).
23. P.–C. Jiang, J. S. Chen, and Y. K. Lin, J. Vac. Sci. Technol. A 21, 616 (2003).
24. Q. T. Vu, P. J. Pokela, C. L. Garden, E. Kolawa, S. Raud, and M.-A. Nicolet, J. Appl. Phys. 68,
24. Q. T. Vu, P. J. Pokela, C. L. Garden, E. Kolawa, S. Raud, and M.-A. Nicolet, J. Appl. Phys. 68,