函數(work function)在微波退火後有較小的變化且偏移的量較介電層為 SiO2的偏 移量小。在 RTA 退火與微波退火後等效氧化厚度(EOT)變化小於 3nm，說明電容 結構在退火後介面沒有很嚴重的化學反應；而且微波退火後的電容電性的均勻性 比 RTA 退火後的電容電性的均勻性有很好的改善。
XRD 分析結果，TiN 的局部晶體取向(localized crystalline orientation) 在 RTA 退火與微波退火後沒有什麼變化，可以知道 TiN 金屬閘極與下面的介電層材料 沒有什麼變化，TiN 的功函數(work function)變化與 TiN 的局部晶體取向(localized crystalline orientation)無關。
TiN 金屬閘極的 MOS 元件，在微波退火後電容特性的均勻度是非常出色，
TiN 的功函數(work function) 微波退火 shift 的值和 RTA 700℃差不多且活化完全
。
然而微波退火後功函數(work function)的下降是我們未來改善的目標，微波 退火低溫活化的特性搭配電漿處理(plasma treatment)，覆蓋層(capping layer)，介 電層摻雜(dielectric doping)這幾個方法調變功函數(effective work function)是我們 未來研究的方向。
參 參 考文 考 文獻 獻
[1] Wong H-S P. H.-S. P. Wong, "Beyond the Conventional Transistor " ---IBM J. Res.
& Dev. 46(2/3), 133- (2002)
[2]S. M. Sze, ―Physics of Semiconductor Devices‖, Second printing July,p.469-486.
[3] Yuan Taur, Tak H. Ning, ―Fundamentals of Modem VLSI Devices‖, First published 1998, Reprinted 1999, p.161, 187.
[4] D. A. Buchanna and S. H. Lo, ―Reliability and Integration of ultra-thin gate dielectrics for advanced CMOS‖, Microelectron. Eng., 36, p. 13, 1997
[5] Saito, and H. Iwai, ―1.5 nm direct-tunneling gate oxide Si MOSFET's‖, IEEE Trans. Electron Devices, vol. 43, pp. 1233–1241, Aug. 1996
[6] International Technology Roadmap for Semiconductors, (2005 Update),SIA,2005.
[7] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Y.
Zhiping, P. M. Zeitzoff, and J. C. S. Woo, IEEE Trans. Electron Devices, 46, no. 7, pp. 1537–1544, Jul. 1999.
[8] J. A. Floro and E. Chason. ―Measuring Ge segregation by real-time stress monitoring during Si 1-xGe x molecular beam epitaxy‖ Appl. Phys. Lett 69, 1996 (p. 3830)
[9] HR Huff, A Hou, C Lim, Y Kim, J Barnett, G Bersuker, “High-k gate stacks for planar, scaled CMOS integrated circuits.‖, Source, Microelectronic Engineering archive. Volume 69 , Issue 2-4 (September 2003).
[10] A Buchanan, ―Scaling the Gate Dielectric: Materials, integration and reliability", IBM J. Res. Develop., vol. 43, pp. 245-264, 1999.
[11] Steven M. Martin, Fadi H. Gebara, Brian J. Larivee, Richard B. Brown, ―A CMOS-Integrated Microinstrument for Trace Detection of Heavy Metals,‖ IEEE Journal of Solid-State Circuits, vol. 40, issue, 12, pp. 2777-2786, Dec. 2005.
[12] NR Mohapatra, MP Desai, SG Narendra, and VR Rao, ―The effect of high- gate dielectrics on deep submicrometer CMOS device and circuit performance,‖IEEE Trans. Electron Devices, vol. 49, pp. 826–831, May 2002 [13] I. De, et al., Solid-State-Electronics, vol.44, no.6, p.1077-80, 2000.
[13] GB Alers, DJ Werder, Y. Chabal, HC Lu, EP Gusev,E. Garfunkel, T. Gustafsson, and RS Urdahl,―Intermixing at the tantalum oxide/silicon interface in gate dielectric structures,‖ Appl. Phys. Lett., vol. 73, no. 11, p. 1517, 1998.
[14] P. Church, A. Leduc, R. A. Beique, and J. R. Derome, ―A numerical solution of cylindrical coordinate Laplace‘s equation with mixed boundary conditions along the axis of symmetry: Application to intracerebral stimulating electrodes‖, J. of Appl. Phys., vol.56, p.1, 1984.
[15] Ohguro, T. Naruse, H. Sugaya, H. Morifuji, E. Nakamura, S. Yoshitomi, T. Morimoto, T. Momose, H.S. Katsumata, Y. Iwai, H. , ―0.18 μm low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique‖Tech. Dig. Int. Electron Devices Meet., p. 873,1997 [16] Hu, J.C. Yang, H. Kraft, R. Rotondaro, A.L.P. Hattangady, S. Lee,
W.W. Chapman, R.A. Chao, C.-P. Chatterjee, A. Hanratty, M. Rodder, M. Chen, I.-C.., Tech. Dig.,‖ Feasibility of using W/TiN as metal gate for conventional 0.13 μm CMOS technology and beyond ―, Int. Electron Devices Meet., p.825, 1997.
[17] Nakajima, K. Akasaka, Y. Kaneko, M. Tamaoki, M. Yamada, Y. Shimizu, T. Ozawa, Y. Suguro, K. ―Work function controlled metal gate electrode on ultrathin gate insulators‖, Symp. On VLSI Tech. Dig., p.95, 1999.
[18] C.W. Yang, Y. K. Fang,C. H. Chen, S. F. Chen, C. Y. Lin, and C.S. Lin, et al.,
―Effectof polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal–oxide–semiconductor field-effect transistors for high-k-HfO2 dielectric‖Appl. Phys. Lett., vol.83 (2), pp.308, 2003.
[19] C. C. Hobbs, L. R. C. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R.
Garcia, D. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, H.-H. Tseng, S. G. H.
Anderson, B. E. White, and P. J. Tobin, ―Fermi-level pinning at the polysilicon/metal oxide interface-Part I,‖ IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 971–977, Jun. 2004.
[20] C.C. Hobbs, L.R.C. Fonseca, A. Knizhnik, V. Dhandapani.,‖ Fermi-level pinning at the polysilicon/metal–oxide interface—Part II‖ Trans. Elec. Dev. Lett., vol.51(6), pp.978, 2004.
[21] Hobbs, C. Fonseca, L. Dhandapani, V. Samavedam, S. Taylor, B. Grant, J. Dip, L.
Triyoso, D. Hegde, R. Gilmer, D. Garcia, R. Roan, D. Lovejoy, L. Rai, R. Hebert, L. Tseng, H. White, B. Tobin, P.‖ Fermi level pinning at the polySi/metal oxide interface―, Symp. VLSI Tech. Dig., pp.9, 2003
[22] IEDM Short Course 2004, Mark Rodder, Texas Instrument.
[23] Yu, H.Y. Ren, C. Yee-Chia Yeo Kang, J.F. Wang, X.P. Ma, H.H.H. Ming-Fu Li Chan, D.S.H. Kwong, D.-L, ―Fermi pinning-induced thermal instability of metal-gate work functions‖, IEEE Elec. Dev. Lett., vol.25 , NO.5 pp.337, 2004.
[24] D.-G. Park, T.-H. Cha, K.-Y. Lim, H.-J. Cho, T.-K. Kim, S.-A. Jang, Y.-S. Suh, V.
Misra, I.-S. Yeo, J.-S. Roh, J. W. Park, and H.-K. Yoon, ―Metal Gate Electrodes for Dual Gate CMOS Devices‖ ,IEDM Tech. Dig. 2001, p. 671..
[25] Y.-H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris, ―Strong quantum- confined Stark effect in germanium quantum-we
ll structures on silicon‖, Nature, vol. 437, pp. 1334-1336, 2005
[26]Tejada, F. Andreou, A.G. Wickenden, D.K. Francomacaro, A.S., ―Surface micromachining in Silicon on Sapphire CMOS technology‖, in Proceedings of the 2004 IEEE international symposium on Circuits and Systems, (ISCAS 2004),vol.4.
IEEE, May 2004, pp.920-923.
[27] Shih, Y.H. Lai, E.K. Hsieh, J.Y. Hsu, T.H. Wu, M.D. Lu, C.P. Ni, K.P. Chou, T.Y.
Yang, L.W. Hsieh, K.Y. Liaw, M.H. Lu, W.P. Chen, K.C. Ku, J. Ni, F.L. Liu, R.
Chih-Yuan Lu, ―Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface‖, IEDM, p.1, 2006.
[28] T. L. Alford, D. C. Thompson, J. W. Mayer,and N. David Theodore, ‖Dopant activation in ion implanted silicon by microwave annealing ‖Journal of applied physics 106, 114902 2009
[29] Nakajima, K. Akasaka, Y. Kaneko, M. Tamaoki, M. Yamada, Y. Shimizu, T. Ozawa, Y. Suguro, K., ‗‘ Work function controlled metal gate electrode on ultrathin gate insulators‘‘. Symp. VLSI Technology, p96, 1999.
[30] D.-G. Park, T.-H. Cha, K.-Y. Lim, H.-J. Cho, ―Robust Ternary Metal Gate Electrodes for Dual Gate CMOS Devices,‖ IEDM Tech. Dig., pp.671-674, 2001 [31] Fujioka H, Kamohara S, King YC and Yang K., ―QMCV simulator,‖ online
available http://www-device.eecs.berkeley.edu/qmcv/index.shtml
[32] N. V. Nguyen, C. A. Richter, Yong Jai Cho, G. B. Alers, and L. A. Stirling,‖
Effects of high-temperature annealing on the dielectric function of Ta2O5 films observed by spectroscopic ellipsometry‖ Appl. Phys. Lett., 77, 3012 (2000).
[33] Pengtao Gao, L. J. Meng, M. P. dos Santos, V. Teixeira and M. Andritschky,‖
Influence of sputtering power and the substrate–target distance on the properties of ZrO2 films prepared by RF reactive sputtering ‖, Thin Solid Films, 377, 557 ,2000.
[34] Kaupo Kukli, Jaan Aarik, Aleks Aidla, Oksana Kohan, Teet Uustare and Väino
Sammelselg,‖ Properties of tantalum oxide thin films grown by atomic layer deposition‖., Thin Solid Films, 260, 135 (1995).
[35] M. Cassir, F. Goubin, C. Bernay, P. Vernoux, and D. Lincot, ―Synthesis of ZrO2 thin films by atomic layer deposition: growth kinetics, structural and electrical properties‖, Applied Surface Science 193 (2002) 120–128
[36] Charles M. Perkins, Baylor B. Triplett, Paul C. McIntyre, Krishna C. Saraswat, Suvi Haukka, and Marko Tuominen,‖ Electrical and materials properties of ZrO2
gate dielectrics grown by atomic layer chemical vapor deposition‖, Appl. Phys.
Lett., 78, 2357 (2001).
[37] C. Chaneliere, S. Four, J. L. Autran, and R. A. B. Devine, ―Comparison between the Properties of amorphous and crystalline Ta2O5 thin films deposited on Si‖, Microelectronics Reliability. 39, 261, (1999).
[38] D. D. L. Chung, et al., X-Ray Diffraction at Elevated Temperatures: A Method for In-Situ Process Analysis, Chap.1, VCH Publishers, New York (1993).
[39] Powder Diffraction File: Inorganic and Organic Data Book, PDF#19-1299, 25-0922, 25-1257, 25-1366, 27-1402, 34-1084, 42-0060, 42-1120, and 72-1088, JCPDS – International Center for Diffraction Data, American Society for Testing and Materials, Swarthmore, PA (1950-2003).
[40] W. L. Bragg, W. H. and W. L. Bragg, ―The Reflection of X-rays by Crystals‖,Proc. Roy. Soc. 88, 428 (1913)
[41] ENMA465 Dr. Gary Rubloff,―An Overview of Atomic Layer Deposition and its role in Transistor Gate Dielectrics‖, May 14, 2003
[42] W. M. Warner, ―The work function difference of the MOS-System with aluminum field plates and polycrystalline silicon field plates‖, Solid-State Electronics 17, 769 (1974)
[43] R. R. Razouk and B. E. Deal, ―Hydrogen anneal effects on metal-semiconductor