5.1 結論
近年來對於電晶體的發展上，從傳統的平面型(planar)電晶體到發展出三 閘極(trigate)電晶體，也就是三維的結構，為的是解決平面型電晶體所面臨到 的問題，但在決問題的同時，卻又衍生出許多更困難的技術性問題，像是閘 極微影的繞射(gate-litho diffraction)、蝕刻製程(etchant process)，由這些製程 所產生之粗糙度的問題也逐漸被大家所討論。
本論文有系統地去完成了氧化層面積之變動率A 與厚度之變動率Tox
的幾何變異之實驗，它們分別是由邊粗糙度(line roughness)與面粗糙度 (surface roughness)所組成，並且我們成功的於三閘極電晶體中，閘極電流之 變動率Ig與閘極電容之變動率Cg中萃取而得。結果顯示出，氧化層厚度之 變動率是由面粗糙度之變動率SR 所估計，它將使得介面缺陷密度增加以及 電子遷移率(mobility)的下降。另外，由於三閘極電晶體的鰭之側壁較粗糙的 原因，使得氧化層厚度之變動率也將影響著臨界電壓之變動率Vth。而在短 通道(short channel)的情況下，由於邊線粗糙度(line edge roughness)所引起的 氧化層面積之變動率則是受高電場的影響，在此進行更深入的探討發現由於 閘極微影時的繞射問題，使得源極(source)與汲極(drain)端之邊緣擁有很高的 相似性。另一方面，與平面型電晶體比較之下，氧化層面積之變動率於三閘 極電晶體中，更是造成汲極飽和電流之變動率Isat 產生的重要因素。然而，
隨著三閘極電晶體之鰭的高度不斷的往上提升時，氧化層厚度所產生之變動 率也將變得更為重要。最後，我們利用三閘極電晶體與平面型電晶體所組成 之反向器，利用其延遲時間(delay rime,)為標準進行受幾何變異所影響比較，
結果顯示，三閘極電晶體確實擁有比平面型電晶體還要大的延遲時間之變動 率，這無疑是由於氧化層之幾何變異所造成，因此我們所提出對於三閘極
69
電晶體的各種變化量之幾何變動量的理論與研究方法，對於未來發展下個世 代的三閘極電晶體來說是非常有用的。
5.2 未來展望
由實驗得知，量測閘電流與閘極電壓，便可得知氧化層面積之變動率與 氧化層厚度之變動率，另外，對於臨界電壓之變動率(Vth)可進行更深入的 探討，例如三閘極電晶體中由於隨機摻雜擾動(RDF)所造成的變動率，是否 會由於鰭的高度(Hfin height)而造成不同的影響，以及探討不同鰭的數目所對 應的變動率。至於三閘極電晶體於電子遷移率的部分，由於實驗中其典型的 三個不同階段中，第二階段(phonon scattering)的部分並不明顯，因此必須更 深入的 去了 解其 原 因，才 能確 保實 驗 結果中 顯示 的確 實 就是第 三階段 (surface scattering)的部分。對於不同鰭(fin)的數目，要如何得知單根鰭所造 成的變動率，這是非常重要的，如果可以進行此探討，論文將更為完整。最 後，於各種不同電晶體之結構上，還有著許多由於種種不同製程所引起的變 動量，或是不同型態的電晶體，像是穿隧式電晶體等等新穎的元件，將會是 未來可以被深入探討的部分。
70
參考文獻
[2-1] G. Moore, “Cramming more Components onto Integrated Circuits,” in IEEE Electronics, p. 114, 1965.
[2-2] 劉傳璽，陳進來，第三版，半導體物理元件與製程-理論與實務，五 南文化出版社，2006。
[2-3] E. R. Hsieh, S. S. Chung, C. H. Tsai, R. M. Huang, C. T. Tsai, et al., “A Novel and Direct Experimental Observation of the Discrete Dopant Effect in Ultra-Scaled CMOS Devices,” in IEEE Very Large Scale Integration Technology Digest, pp. 194-195, 2011.
[2-4] E. R. Hsieh, E. D. Wang, S. S. Chung, “A New Variation Plot to Examine the Interfacial-Dipole Induced Workfunction Variation in Advanced High-k Metal-Gate CMOS Devices,” in IEEE Very Large Scale Integration Technology Digest, p. 204, 2016.
[2-5] E. R. Hsieh, Y. L. Tsai, S. S. Chung, C. H. Tsai, R. M. Huang, et al., “The Understanding of Multi-Level RTN in Tri-gate MOSFETs through the 2D Profiling of Traps and Its Impact on SRAM Performance: A New Failure Mechanism Found,” in IEEE International Electron Devices Meeting, pp.
19.2.1-19.2.4, 2012.
[2-6] H. M. Tsai, E. R. Hsieh, S. S. Chung, C. H. Tsai, R. M. Huang, et al.,
“The Understanding of the Trap Induced Variation in Bulk Tri-gate Devices by a Novel Random Trap Profiling (RTP) Technique,” in IEEE Very Large Scale Integration Technology Digest, pp. 189-190, 2012.
[2-7] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness,”
IEEE Transactions on Electron Devices, Vol. 50, pp. 1254-1260, 2003.
71
[2-8] E. R. Hsieh, S. T. Lin, S. S. Chung, R. M. Huang, C. T Tsai, et al., “Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Tri-gate MOSFETs and the Power Dissipation of SRAM,” in IEEE International Electron Devices Meeting, pp. 31.2.1-31.2.4, 2013.
[2-9] D. Reid, C. Millar, S. Roy, and A. Asenov, “Understanding LER-Induced MOSFET VT Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples,” IEEE Transactions on Electron Devices, Vol.
57, pp. 2801-2807, 2010.
[2-10] S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, P. Rao, H. Wang, and B. En, “Is Gate Line Edge Roughness a First-Order Issue in Affecting the Performance of Deep Sub-Micro Bulk MOSFET Devices?,” IEEE Transactions on Semiconductor Manufacturing, Vol. 17, 2004.
[2-11] S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, and P. Rao, “Study of Gate Line Edge Roughness Effects in 50 nm Bulk MOSFET Devices,” in Proceedings of SPIE, Vol. 4689, pp. 733-741, 2002.
[2-12] S. Xiong, J. Bokor, “A Simulation Study of Gate Line Edge Roughness Effects on Doping Profiles of Short-Channel MOSFET Devices,” IEEE Transactions on Electron Devices, Vol. 51, 2004.
[2-13] Y. Ye, F. Liu, and M. Chen, “Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness,” IEEE Transactions on Very Large Scale Integration
System, Vol. 19, 2011.
[2-14] F. Zhao, Q. Wang, L. Zhang, and Z. Jiang, “Impact of Line Edge Roughness and Line Width Roughness on Critical Dimension Variation,”
72
IEEE International Conference, Vol. 3, pp. 475-479, 2012.
[2-15] X. Jiang, R. Wang, T. Yu, J. Chen, and R. Huang, “Investigations on Line Edge Roughness (LER) and Line Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method,” IEEE Transactions on Electron Devices, pp. 3669-3675, 2013.
[2-16] R. Wang, X. Jiang, T. Yu, J. Fan, J. Chen, D. Z. Pan, and R. Huang,
“Investigations on Line Edge Roughness (LER) and Line Width Roughness (LWR) in Nanoscale CMOS Technology: Part II-Experimental Results and Impacts on Device Variability,” IEEE Transactions on Electron Devices, pp. 3676-3682, 2013.
[3-1] M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, “Limit of Gate Oxide Thickness Scaling in MOSFETs due to Apparent Threshold Voltage Fluctuation Induced by Tunnel Leakage Current,” IEEE Transactions on Electron Devices, Vol. 48, pp. 259-264, 2001.
[3-2] M. Depas, B. Vermeire, P. W. Mertens, R. L. V. Meirhaeghe, and M. M.
Heyns, “Determination of Tunnelling Parameters in Ultra-Thin Oxide Layer Poly-Si/SiO2/Si Structures,” Solid-State Electronics, Vol. 38, pp.
1465-1471, 1995.
[3-3] M. Cassé, X. Garros, O. Weber, F. Andrieu, G. Reimbold, and F.
Boulanger, “Study of N-induced Traps due to Nitrided Metal Gate in HK/MG nMOSFETs,” Proceedings of the European Solid-State Device Research Conference, pp. 325-328, 2010.