於本篇論文所談到的關於 CT ΣΔ modulator 設計的過程中，從一開始係數 上的決定，已將 CT excess loop delay 的影響計算在其內而做了修正。接著在 MATLAB 的模擬環境中，我們建立了有關有限增益頻寬，jitter，RC 時間常數和 各路徑係數的變動，以及考慮到電阻電容匹配性影響的 behavioral model。另 外 也 對 於 MATLAB single-ended 的 模 擬 環 境 ， 對 應 到 電 路 上 以 fully- differential 的方式來實現所得到的模擬結果(主要在於 mismatch 上的模擬)做 了分析。最後根據 MATLAB 模擬所訂定的規格，在 HSPICE 上設計的電路，對於探 討到的各項非理想效應所得到的模擬結果，也有良好的對應性。
除了非理想效應的探討，針對不同的架構也做了比較。在我們所使用的 half-delay 架構上來看，無論是二階或是三階的系統，除了所需要的元件規格 較 unit-delay 的架構來得低之外。在對於 RC variation 的容忍度也有較大的範 圍。而係數上的 variation，我們則使用電容式的加法電路，利用其製程上的優 勢，即可做到在比例上的精準度，將其影響減到最低。省去了在電阻加法電路的 做法中所需要的運算放大器，同時也減低了功率的消耗。
而所討論到的 feed-forward 以及 feed-back 的差異性，即 CRFF 和 CRFB。
而無論兩者之間選擇何架構在設計上，都可以達到所預期的規格。但是由於抗 variation 以及消耗功率上，較偏好使用 CRFF 的架構。
最後本篇論文中在 HSPICE 上模擬得到的 CT SDM 為:
(1)250 kHz, 4mW, 83dB SNDR 3rd-order in CRFF form (2)250 kHz, 6mW, 76dB SNDR 3rd-order in CRFB form
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