第三章 實驗結果與討論
3.2 綜述
第四章 結論與未來發展
4.1 結論
本實驗中我們藉由雷射退火(laser annealing)及高介電材料(La2O3)加上鍺基材的 使用，達到成果如下：
(1) 有效提高電子遷移率(mobility)：
因為電子遷移率的提高即代表電晶體的速度變快，而電晶體的速度變快就 代表低功耗與高遷移率的性能越趨重要。
而本實驗樣品即擁有較高電子遷移率(mobility =304 cm2/V @0.75 MV/cm 及peak mobility=603 cm2/Vs)。
(2) 較大的導通/截止電流比：
因為較大的導通/截止電流比即代表電晶體不但擁有大驅動電流，還克服 了穿隧效應及短通道效應擁有很小的漏電流，此為電晶體性能重要的指標。
而本實驗的樣品即擁有很大導通/截止電流比(ratio=105)。
(3) 降低了活化(annealing)時的溫度：
因為使用Laser annealing製程則可針對小區域執行快速且低溫的退火過 程，除去了RTA的高溫退火製程在電晶體微小化的現況下，IC可能會因溫度 過高而損壞。
而本實驗的樣品在雷射能量160 mJ/cm2時即可達到退火效果，若使用RTA 製程則需將溫度拉高至550℃才能達到相同效果。
(4) 降低了片電阻值(sheet resistance)：
因為降低片電阻值就等於降低電流的阻抗，提高電晶體的工作效率，這 也是電晶體性能的重要指標之一。
而本實驗的樣品在在雷射能量220 mJ/cm2時Rs值等於68 Ω/sq，遠低於使 用RTA 550℃時Rs值(Rs等於112 Ω/sq)，這兩者Rs值相差達40 %。
4.2 未來發展
根據本實驗的結果提出未來能夠持續改善及發展的方向如下：
(1) 材料的使用：
(a) 鍺基材的改善：
由於鍺具有比矽還小的能階(bandgap)，對於其可能會造成的接面漏電 問題，可採用在鍺基板上利用熱成長的二氧化矽層(深處植入的氧與矽鍵結 成 SiO2)的 Ge-on-insulator (GOI or GeOI)技術改善漏電問題 [14]，或是在矽 基板上成長一層薄鍺膜的 ultrathin body Ge-on-Si 技術，而此技術也可改善 鍺價格昂貴的問題。
(b) 遷移率的改善：
可使用 III-V 族的材料來改善遷移率問題，由於 III-V 族擁有極高的 電子遷移率，如砷化鎵(GaAs)其電子遷移率為 8500 cm2/Vs，為鍺的 2.17 倍、矽的 6.29 倍(鍺=3900 cm2/Vs，矽=1350 cm2/Vs) [33]。
(c) 使用 p-MOSFET：
鍺的低電場電子遷移率比矽大二倍以上(3900 V.S. 1500cm2/V-sec)，而 電洞遷移率更比矽大了四倍(1900 V.S. 450cm2/V-sec)之多，雖然本實驗是使 用 n-MOSFET，但也可以朝 p-MOSFET 方向發展實驗[3]、[4]。
(2) 雷射退火的相關應用：
就退火的效率及退火所需的溫度而言，由本實驗可得知 laser annealing 製程確實比傳統的 RTA 製程具有優勢，在 IC 製程不斷微縮的未來，相信挾 其優勢必定會是未來的主流。然而在其他需要執行退火製程的半導體相關產 業，例如；太陽能電池(Solar cells)、液晶面板(LCD)等，雖然目前還是採用 處理速度慢、效率低的紅外線燈爐管退火製程，但相信日後在成本及良率考 量下，也有可能採用雷射退火製程技術，以確保產品的競爭力。
參考文獻
[1] 宋健民，先進半導體製程與材料選擇，”半導體科技雜誌”，2008。
[2] Matthias Passlack, III-V 族與鍺期望能幫助 CMOS 發展，“半導體科 技雜誌”， 2010。
[3] Jungwoo Oh, Prashant Majhil, Hideok Lee, Ooksang yoo, Sehoon Lee, Sanjay Banerjee,Hsing-Huang Tseng, and Raj Jammy, “Controlled threshold voltage of high-mobility Ge pMOSFETs with high-k/metal gate on epitaxial Ge films on Si substrates,” in VLSI Symp. Tech. Dig., pp. 40–41. 2008.
[4] M. Yang, M. leong, L. Shi, K. Chan, V. Chant, A. Chout, E. Gusev, K.
Jenkins,D. Boyd,Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb,P. Mooney, B. To, N. Rovedo, J. Benedict, R. MO and H. Ng, “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations,” in IEDM Tech. Dig., pp. 18.7.1–18.7.4.
2003.
[5] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi,G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D.
Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford,
L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C.
Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” in
IEDM Tech. Dig., pp. 247–250. 2007.
[6] Donald A. Neamen，半導體物理與元件，初版，滄海書局，2008。
[7] 吳良志， Laser Basic Course Training，”Gigaphoton 公司”， 2008。
[8] 張鼎章， 半導體製程概論講義，”第一章 半導體製程概論”，2000。
[9] 莊達人，VLSI 製造技術（修訂版），六版，滄海書局，2000。
[10] 趙臨軒，基礎物理透析，初版，全華圖書，2010。
[11] 孫允武，中興大學物理系，
網址”
http://ezphysics.nchu.edu.tw/prophys/electron/lecturenote/ ”。
[12] 艾司摩爾，ASML XT1950i Training Reprot，”ASML 股份有限公司”，
2007。
[13] 蕭宏，半導體製程技術導論（修訂版），二版，學銘圖書股份有限公司，
1994。
[14] C. H. Huang, M. Y. Yang, A. Chin, W. J. Chen, C. X. Zhu, B. J. Cho, M.-F. Li, and D. L. Kwong, “Very low defects and high performance Geon- insulator p-MOSFETs with Al2O3 gate dielectrics,” in VLSI Symp. Tech. Dig., , pp. 119–120. 2003.
[15] C. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400℃ Ge MOSFET technology with high-κ dielectric and metal gate,” in IEDM Tech. Dig., pp. 437–440. 2002.
[16] W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L. Kwong, D. Wristers, A. Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD HfO2 gate dielectrics and TaN gate electrode,” in VLSI Symp. Tech. Dig., pp. 121–
122. 2003.
[17] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M. F.
Li, A. Chin, J. K. O. Sin, and D. L. Kwong, “A TaN-HfO2-Ge pMOSFETs with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, no.
9, pp. 631–633, Sep. 2004.
[18] S. Zhu, R. Li, S. J. Lee, M. F. Li, A. Du, J. Singh, C. Zhu, A. Chin, and D. L.
Kwong, “Germanium pMOSFETs with Schottky-barrier germanide S/D, high-κ gate dielectric and metal gate,” IEEE Electron Device Lett., vol. 26, no.
2,pp. 81–83, Feb. 2005.
[19] W. P. Bai, N. Lu, and D.-L. Kwong, “Si interlayer passivation on germanium
MOS capacitors with high-κ dielectric and metal gate,” IEEE Electron Device
Lett., vol. 26, no. 6, pp. 378–380, Jun. 2005.
[20] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L. K. Bera, and C. Zhu, “Drive-current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation,” IEEE Electron Device Lett., vol. 27, no. 9, pp.
728–730, Sep. 2006.
[21] M. Kobayashi, T. Irisawa, B. M. Kope, Y. Sun, K. Saraswat, H.-S. P. Wong, P. Pianetta, and Y. Nishi, “High quality GeO2
/Ge interface formed by SPA
radical oxidation and uniaxial stress engineering for high performance Ge NMOSFETs,” in VLSI Symp. Tech. Dig., pp. 76–77. 2009.[22] K. Kita, S. K. Wang, M. Yoshida, C. H. Lee, K. Nagashio, T. Nishimura, and A. Toriumi, “Comprehensive study of GeO2 oxidation, GeO desorption and GeO2-metal interaction—Understanding of Ge processing kinetics for perfect interface control,” in IEDM Tech. Dig., pp. 693–696. 2009.
[23] K. Morii, T. Iwasaki, R. Nakane, M. Takenaka, and S. Takagi, “High performance GeO2
/Ge nMOSFETs with source/drain junctions formed
by gas phase doping,” in IEDM Tech. Dig., pp. 681–684. 2009.[24] D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta,
H.-S. P. Wong, and K. C. Saraswat, “Experimental demonstration of high mobility Ge NMOS,” in IEDM Tech. Dig., pp. 453–456. 2009.
[25] C. H. Lee, T. Nishimura, N. Saido, K. Nagashio, K. Kita, and A. Toriumi, “Record-high electron mobility in Ge n-MOSFETs exceeding Si universality,” in IEDM Tech. Dig., pp. 457–460. 2009.
[26] H.-Y. Yu, M. Kobayashi, W. S. Jung, A. K. Okyay, Y. Nishi, and K. C.
Saraswat, “High performance n-MOSFETs with novel source/drain on selectively grown Ge on Si for monolithic integration,” in IEDM Tech.
Dig., pp. 685–688. 2009.
[27] T. Yamamoto, T. Kubo, T. Sukegawa, E. Takii, Y. Shimamune, N. Tamura, T. Sakoda, M. Nakamura, H. Ohta, T. Miyashita, H. Kurata, S. Satoh, M. Kase, and T. Sugii, “Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology,” in IEDM Tech. Dig., pp. 143–146. 2007.
[28] C. C. Liao, A. Chin, N. C. Su, M.-F. Li, and S. J. Wang, “Low Vt gate-first Al/TaN/[Ir3Si-HfSi2−x]/HfLaON CMOS using simple laser
annealing/reflection,” in VLSI Symp. Tech. Dig., pp. 190–191. 2008.
[29] F. Liu, H. S. Wong, K. W. Ang, M. Zhu, X. Wang, D. M. Y. Lai, P. C. Lim, and Y. C. Yeo, “Laser annealing of amorphous germanium on silicon—
Germanium source/drain for strain and performance enhancement in pMOSFETs,” IEEE EDL., vol. 29, no. 8, pp. 885–888, Aug. 2008.
[30] W. B. Chen and Albert Chin, “High Performance of Ge nMOSFETs Using
SiO2 Interfacial Layer and TiLaO Gate Dielectric, ” IEEE Electron Device
Lett., vol. 31, no. 1 pp. 80–82, Jan. 2010.
[31] C. Ortolland, L.-A. Ragnarsson, P. Favia, O. Richard, C. Kerner, T.
Chiarella, E. Rosseel, Y. Okuno, A. Akheyar, J. Tseng, J.-L. Everaert,
T. Schram, S. Kubicek, M. Aoulaiche, M. J. Cho, P. P. Absil, S. Biesemans, and T. Hoffmann, “Optimized ultra-low thermal budget process flow for advanced high-k/metal gate first CMOS using laser annealing technology,”
in VLSI Symp. Tech. Dig., pp. 38–39. 2009.
[32] C. Y. Ong, K. L. Pey, K. K. Ong, D. X. M. Tan, X. C. Wang, H. Y. Zheng, C. M. Ng, and L. Chan, “A low-cost method of forming epitaxy SiGe on Si substrate by laser annealing,” Appl. Phys. Lett., vol. 94, no. 8,
pp. 082 104-1–082 104-3, Feb. 2009.
[33] M. F. Chang, P. T. Lee, S. P. McAlister, and A. Chin, “Low subthreshold swing HfLaO/pentacene organic thin-film transistors,” IEEE Electron
Device Lett., vol. 29, no. 3, pp. 215–217, Mar. 2008.
[34] Grace Huiqi Wang, Eng-Huat Toh, Xincai Wang, “Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs,” IEEE
Electron Device Lett., pp. 131-134, . 2007.
[35] Q.C. Zhang, J. D. Huang, N. Wu, G. X. Chen1, M. H. Hong1, L.K. Bera,