在本實驗中，我們使用矽鍺/鍺堆疊結構與一次活化的製程步驟降 低漏電流，漏電流受到相當大的改善。當晶格不匹配的兩種材料接觸 時並定會產生差排，目前改善鍺與矽差排的製程技術有(1)漸層堆疊 法，(2)循環回火法。漸層堆疊法所沈積的薄膜非常厚，製程時間極長，
技術複雜，但是薄膜品質非常優異，幾乎無差排的存在。而循環回火 法必須做很多次的回火步驟，所使用的熱預算十分龐大，鍺矽介面依 然會有差排，但其優點是製程方便。本實驗所使用的方式比上述兩種 方式更為簡單，漏電流範圍也控制在一定的等級下。本實驗也提供一 種新穎且簡單的製程方式製作淺接面，對未來製作提升鍺源極/汲極 提供另一個方向。
在這些製作專題過程中，讓我們對半導體元件有更多的認識與學 習並用於實驗測量驗證結果。讓我學到其他的相關知識運用其方法去 獲得參數值最佳化的結果。
感謝指導老師 楊文祿老師的教導與實驗室的學長姊們的指導與 照顧，我將以主動積極、努力認真之學習態度，凡是盡心盡力、全力 參數之萃取精準度，以赴的研究精神來面對任何研究領域，並將專題 中所學，應用於日後的研究上。
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