As mentioned above, SiC has superior electrical properties and can produce low on resistance and high blocking voltage power devices. SiC is the only one compound semiconductor that can be thermally oxidized directly, which is similar to the Si
technology. The power MOSFET is an important device for two reasons. First, it has higher switch speed and low power loss than BJT because MOSFET has no minority carrier storage effect. Second, it also has large safe operation area (SOA) for automotive application. The early SiC power MOSFET was reported in 1995 with UMOSFET structure [15]. The trench corner is easily to breakdown, so the breakdown voltage is only 260 V. In order to eliminate the corner breakdown, the DMOSFET structure was reported in 1997 [16]. The breakdown voltage was improved to 760 V. The LDMOSFET with a long lateral drift region can achieve a breakdown voltage of 2.6 kV [17]. Moreover, a RESURF technology combined with LDMOSFET structure to reduce surface field has been reported in literature [18]. In the present, there are several commercialized SiC devices such as Schottky Barrier Diode (SBD), Junction Barrier Schottky Diode (JBSD), and MOSFET. A 1200 V power MOSFET has been commercialized recently [19]. Unfortunately, the low channel mobility in the range of 5–40 cm/V-s occurs on the 4H-SiC MOSFET due to the higher SiO2/SiC interface states density [20]. The large amount trapped charges at the SiO2/SiC interface results in Coulomb scattering and degrades channel mobility.
The usually measured SiO2/SiC interface states density exceeds 1012 1/cm2/eV, which is 100 times higher than the SiO2/ Si interface.
The SiC oxidation mechanism obeys the following chemical reaction [21].
SiC + 1.5 O2 → SiO2 + CO
There are several steps for SiC oxidation. First, molecular oxygen transports to the SiO2 surface and then diffuses toward SiO2/SiC interface. Second, molecular oxygen reacts with SiC forming SiO2 and the product (CO) diffuses out of the SiO2. The unreacted carbon and undiffused CO residue at the SiO2/SiC interface that cause the high interface state density (Dit). How to reduce Dit is a critical issue for SiC MOS
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(POA) in NO or N2O ambient at high temperature for a long time. During the POA process, N atoms incorporate to the SiO2/SiC interface and form the Si-N and C-N bonds to passivate the interface states. NO annealing can be more effective in improving Dit than N2O annealing. Because NO is a toxic gas, it is impractical to use NO [22-23]. Some researchers used high dielectric constant (high-κ) dielectrics to replace SiO2 [24]. The electric field in high-κ dielectrics is lower than that in the low-κSiO2 at the same effective thickness. However, the conduction band offset between high-κand SiC is lower than that between SiO2 and SiC because of the higher dielectric constant the lower energy band-gap. The carrier tunneling barrier reduces and leakage current increases [25].
POCl3 [26], NH3 [27] and H2 [28] annealing have also been reported in literature.
Although POCl3 annealing can achieve lower Dit than NO annealing, the increase of positive charges in oxide after annealing causes apparent flat-band voltage shift. H2 annealing exhibits little improvement on Dit and the best result occurs at 800 ℃.
Above 800 ℃, H2 annealing does not further reduce Dit. NH3 and N2O annealing do not reduce Dit to acceptable level [29]. In addition to these POA methods, the oxidation in sodium (Na) environment can reduce Dit and achieved channel mobility to above 150 cm2/Vs. Unfortunately, there are many Na mobile ions in oxide [30].
High doping concentration (>>1015 cm-3) n-type SiC substrate has been used to enhance oxidation rate [21]. This enhancement is due to the doping-induced lattice mismatch. However, the oxide quality degrades due to this mismatch. To enhance oxidation rate, preamorphization by ion implantation has been proposed [31]. The oxidation rate of amorphous SiC is comparable to that of Si so that the low temperature oxidation can be achieved. However, the wide carbon transition region occurs between the crystal SiC and SiO2, as the temperature is not high enough to diffuse CO out and consume the amorphous region totally.
1-5 Motivation
The post-oxidation treatment methods in recently literatures are discussed in the previous section. Most of the methods need high temperature and very long annealing process. In this thesis we try to compare different types of low thermal budget processes (<1100 ℃) and the best process for the lowest interface state density is identified. The sample set of low temperature wet oxidation is the high bound reference of interface state density in this thesis since lots of carbon clusters during long time oxidation do not have enough time to diffuse out [32]. The current transport mechanisms of the wet oxide samples are also investigated The 1300 ℃ N2O oxidation sample provides the lowest bound reference of interface states density in this thesis.
Three sets of samples are used to compare with reference samples. First, post-oxidation annealing (N) is performed. We want to understand if NH3 and N2O annealing have superposition effect or not. Second, the post-oxidation ammonia plasma treatment method has the lowest thermal budget but a few literatures used this method on SiC MIS capacitor [33]. We want to investigate the interface passivation effect with various times and powers of plasma. We also want to know the limitation of plasma treatment with high power and long treatment time. The optimum treatment condition would be found. Third, in order to avoid C transition layer at the SiO2/SiC interface during thermal oxidation, we try to deposit plasma enhanced chemical vapor deposition (PECVD) oxide and High-κ material on SiC. We obtain large effective oxide thickness (EOT) with dielectric stacks.
High temperature measurement is performed because we want to extract deep level interface state density. We describe the details reasons for high temperature measurement in the next chapter. Mobile ion measurement is also performed in this
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thesis.