In this study, some important results have been summarized in previous section.
However, many works are worthy for further investigation. They are listed here.
1. The source of the negative charges after plasma treatment is not clear at this moment. Further material analysis will be performed in the future. Those negative charges may degrade the channel mobility due to Coulomb scattering. How to reduce negative charges is an important issue.
2. The sample HT has low breakdown field due to thick oxide. We try to repeat the process of 1300 ℃ N2O-grown oxide and reduce oxide thickness to improve breakdown characteristic in the future.
3. Except the samples W0.5 and W1, the current transport mechanisms for other samples are still unclear. The further investigation at various temperatures would help on clarifing the transport mechanism.
4. The thinner (10 nm) PECVD oxide deposition on SiC has large leakage current and poor interface quality. The reason is not clear in this stage. We doubt the stoichiometric ratio of PECVD oxide is not theoretical at initial deposition stage.
The stoichiometric ratio of PECVD oxide will be detected by SIMS and XPS analysis.
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5. In order to operate at high voltage and high temperature for a long time, the reliability of the gate dielectric must be investigated. Poor SiC MOS lifetimes below 1000 s at 6 MV/cm and 350 ◦C has been reported in literature [43].
Bias-stress-induced threshold-voltage instability due to electron tunneling from the oxide traps is observed [44]. Therefore, reliability of the MIS structure fabricated by the low thermal budget processes proposed in this thesis should be evaluated carefully. Time dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) will be measured in the future.
6. The hydrogen and nitrogen can passivate C-cluster–like defects during NH3 plasma treatment but the thermal stability is an issue for high temperature MISFET processes application. Hydrogen may escape from interface during high temperature processes. If NH3 plasma treatment will want to be embedded in MISFET processes, the thermal stability of NH3 plasma treatment–MIS-capacitor will be further investigated.
7. The deep level (Ec-E > 1 eV) Dit is not passivated for all samples as mentioned in previous cheaper. How to reduce deep level Dit is worthy to investigate.
8. In addition to nitrogen passivation, it has been reported that fluorine passivation can reduce interface state density at the SiO2/Si interface [45]. It is worthy to evaluate the effect of fluorine passivation on SiC substrate. Several processes can be considered. They are CF4 plasma treatment, NF3 annealing, fluorine ion implantation, and so on.
9. If we want obtain lowest Dit, the high temperature N2O is needed in recently stage.
We will try to fabricate planar SiC MISFET in next year. NH3–plasma-treatment and 1300℃ N2O will be embedded in SiC MISFET. The source and drain dopant activation issues need further investigation.
References
[1]. B.Jayant Baliga, “Power Semiconductor Devices”, PWS Publishing Company, 1996, pp.7-8.
[2]. B.Jayant Baliga, “Power Semiconductor Devices”, PWS Publishing Company, 1996, pp.199-255.
[3]. AMES A. COOPER, JR AND ANANT AGARWAL, “SiC Power-Switching Devices—The Second Electronics Revolution” Proceedings of the IEEE, vol. 90, no. 6, pp.956-968, 2002.
[4]. Baoxing Duan and Yintang Yang, “A Development Summarization of the Power Semiconductor Devices” IETE Technical Review, vol. 28, no. 6, pp.503-511, 2011.
[5]. B.Jayant Baliga, “Trends in Power Semiconductor Devices” IEEE Trans. Electron Devices, vol. 43, no. 10, pp.1717-1731, 1996.
[6]. Jong Mun Park, “Novel Power Devices for Smart Power Applications”
Marburgerstrasse 9/5 St. Peter 8042 Graz, Wien, 2004.
[7]. A. Porst Siemens, “Ultimate Limits of an IGBT (MCT) for High Voltage Applications in Conjunction with a Diode” Proc, of the 6th Internat. Power Semiconductor Devices & IC's, Davos, Switzerland, 1994, pp163-170.
[8]. S. M. Sze, “Physics of Semiconductor Devices” New York: Willey- Interscience, 1985.
[9]. J. Milla´n, “Wide band-gap power semiconductor devices”IET Circuits Devices Syst., vol. 1, no. 5, pp. 372 –379, 2007.
[10].MAGNUS WILLANDER1 et al., “Silicon carbide and diamond for high temperature device applications” Journal of Material Science: Materials in Electrions, vol.17, pp.1-25, 2006.
[11].Masakazu Kanechika et al., “Advanced SiC and GaN Power Electronics for Automotive Systems’’ IEDM Tech. Dig., 2010, pp. 324-327.
[12].Yoon Soo Park, ’’SiC Materials and Devices” Academic Press, pp.1-20, 1998.
[13].Volker Presser et.al “Silica on Silicon Carbide,” Critical Reviews on Solid State
& Material Sciences, vol.33, pp.1-99, Taylor and Francis, 2008.
[14].G. L. Harris, ’’Properties of Silicon Carbide”, vol. 13, Weiss, B.L. Ed. INSPEC, the Institution of Electrical Engineers, London, 1995.
[15].J. W. Palmour, S. T. Allen, R. Singh, L. A. Lipkin, and D. F. Waltz,“4H-silicon carbide power switching devices,” in Silicon Carbide and Related Materials 1995, ser. Inst. Phys. Conf. Series no. 142, 1996, p.813.
73
[16].J. N. Shenoy, J. A. Cooper, Jr., and M. R. Melloch, “High-voltage double-implanted power MOSFETs in 6H-SiC,” IEEE Electron Device Lett., vol.
18, no.3, pp. 93-95, 1997.
[17].J. Spitz, M. R. Melloch et al., “2.6 kV 4H-SiC Lateral DMOSFET” IEEE Electron Device Lett., vol. 19, no. 4, pp.100-102, 1998.
[18].J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF devices),” IEDM Tech. Dig., 1979, pp. 238-241.
[19].Cree Launches Industry’s First Commercial Silicon Carbide Power MOSFET;
Destined to Replace Silicon Devices in High-Voltage (≥ 1200-V) Power Electronics,” Cree News, 2011.
[20].GUDJÓNSSON et al., “High Field-Effect Mobility in n-Channel Si Face 4H-SiC MOSFETs With Gate Oxide Grown on Aluminum Ion-Implanted Material”
IEEE Electron Device Lett., vol. 26, no. 2, pp.96-98, 2005.
[21].B. K. Daas et al., “Doping Dependence of Thermal Oxidation on n-Type 4H-SiC”
IEEE Trans. Electron Devices, vol. 58, no. 1, pp.115-121, 2011.
[22].G. Y. Chung, C. C. Tin et al., ‘Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide’ Appl.
Phys. Lett., vol. 76, no. 13, pp.1713-1715, 2000.
[23].Kuan Yew Cheong et al.,“ Electrical and physical characterization of gate oxides on 4H-SiC grown in diluted N2O” J. Appl. Phys., vol. 93, no. 9, pp.5682-5686, 2003.
[24].Kuan Yew Cheong et al., ”Improved Electronic Performance of HfO2/SiO2
Stacking Gate Dielectric on 4H SiC” IEEE Trans. Electron Devices , vol. 54, no.
12, pp. 3409-3413, 2007.
[25].A. K. Agarwal, S. Seshadri, and L. B. Rowland, “Temperature dependence of Fowler–Nordheim current in 6H- and 4H-SiC MOS capacitors,” IEEE Electron Device Lett., vol. 18, no. 12, pp. 592–594, Dec. 1997.
[26].D. Okamoto, H. Yano, K. Hirata, T. Hatayama, and T. Fuyuki, “Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide,” IEEE Electron Device Lett., vol.31, no.7, pp.710-712, 2010.
[27].G. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. Di Ventra, R. K. Chanana, S. T. Pantelides, L. C. Feldman, and R. A. Weller, “Effects of anneals in ammonia on the interface trap density near the band edges in 4H–silicon carbide metal-oxide-semiconductor capacitors,” Appl. Phy. Lett., vol.77, no.22, pp.3601-3603, 2000.
[28].K. Fukuda et al., “Reduction of interface-state density in 4H–SiC n-type metal oxide semiconductor structures using high-temperature hydrogen annealing”
Appl. Phys. Lett., vol. 76, no. 12, pp.1585-1587, 2000.
[29].S.Chakraborty et al., “Interface properties of N2O annealed SiC metal oxide semiconductor devices” Solid state Electronics 45, pp.471-474, 2001.
[30].F. Allerstam et al., “A strong reduction in the density of near-interface traps at the SiO2/4H-SiC interface by sodium enhanced oxidation” J. Appl. Phys., vol.101, pp.124502-1-124502-5, 2007.
[31].Antonella Poggi et al., “Low temperature oxidation of SiC preamorphized by ion implantation” J. Appl. Phys., vol. 95, no., pp.6119-6121, 2004.
[32].M. Schürmann et al., “Investigation of carbon contaminations in SiO2 films on 4H-SiC (0 0 0 1),” J. Appl. Phys., vol. 100, no. 11, pp.113510-1-113510-6, Dec.
2006.
[33].Y. Iwasaki et al., “NH3 Plasma Pretreatment of 4H-SiC (0 0 0_1) Surface for Reduction of Interface States in Metal–Oxide–Semiconductor Devices” Appl.
Phys. Express 3, pp.026201-1-026201-5, 2010.
[34].Chang et al., “High-carbon concentrations at the silicon dioxide–silicon carbide interface identified by electron energy loss spectroscopy” Appl. Phys. Lett., vol.
77, no. 14, pp.2186-2188, 2000.
[35].R. Esteve et al., “Toward 4H-SiC MISFETs Devices Based on ONO (SiO2-Si3N4-SiO2) Structures” Journal of The Electrochemical Society, vol. 158, no 5, pp.H496-H501, 2011.
[36].R. Castagne and A. Vapaille , Surface Sci., vol.28, no. 873, 1970.
[37].J. A. Cooper, Jr., “Advances in SiC MOS Technology,” phys. stat. sol. (a), vol.
162, no. 1, pp. 305-320, 1997.
[38].Kuan Yew Cheong et al., “Current conduction mechanisms in atomic-layer-deposited HfO2 /nitrided SiO2 stacked gate on 4H silicon carbide” J.
Appl. Phys. vol 103, pp.084113-1-084113-8, 2008.
[39].P. Friedrichs et al., “Interface properties of metal-oxide-semiconductor structures on n-type 6H and 4H-SiC” J. Appl. Phys. vol.79, no 10, pp.7814-7819, 1996.
[40].Sanjeev K Gupta, A Azam and J Akhtar., “Variation of interface trap level charge density within the bandgap of 4H-SiC with varying oxide thickness”
Pramana – J. Phys., vol. 76, no. 1, pp.165-172, 2011
[41].T. KIMOTO et al., “Interface Properties of Metal–Oxide–Semiconductor Structures on 4H-SiC{0 0 0 1} and (1 1-2 0) Formed by N2O Oxidation” Jpn. J.
Appl. Phys., vol. 44, no. 3, pp. 1213–1218, 2005.
[42].Anri Nakajima et al., “Soft Breakdown Free Atomic-Layer-Deposited Silicon Nitride/SiO2 Stack Gate Dielectrics” IEDM Tech. Dig., 2001, pp.133-136.
[43].L. A. Lipkin and J. W. Palmour, “Insulator investigation on SiC for improved reliability,” IEEE Trans. Electron Devices, vol. 46, no. 3, pp. 525–532, 1999
75
[44].Aivars J. Lelis et al., “Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements” IEEE Trans. Electron Devices, vol.
55, no. 8, pp. 1835–1840, 2008.
[45].P. J. Wright and K. C. Saraswat, ”The Effect of Fluorine in Silicon Dioxide Gate Dielectrics,” IEEE Trans. Electron Devices, vol.36, no.5, pp.879-889, 1989.