There are seven chapters in this dissertation. In chapter 1, a brief review of the scaling down issues of metal silicide and S/D junctions is given. The motivation for the thesis is also described.
In chapter 2, the thermal stability of NiSi with Ge ion implantation (Ge I/I) is investigated. The energies and dosages of Ge I/I before and after silicide formation are examined to test the efficiency improvement. Applications on differential substrates for poly-Si and bulk-Si are also carried out. The sheet resistance, SEM, TEM, AFM, SIMS, and XRD are employed to examine the thermal stability of NiSi.
In chapter 3, we show how the best Ge I/I condition in chapter 2 is applied to
junction fabrication. The electrical characteristics of p+-n and n+-p junctions with Ge I/I are investigated in detail. We also discuss the temperature and time effects for the junction leakage. The contact resistance between the NiSi and p+ Ge I/I layer is measured by the CBKR structure.
In chapter 4, the ITS technology is utilized in the fabrication of MSB p+-n and n+-p lateral junctions on SOI. The electrical characteristics of MSB p+-n and n+-p junctions are discussed. Different temperatures and durations are used to examine the dopant segregation efficiency. The interface trap density between the Si and SiO2 of the MSB p+-n and n+-p junctions is also measured. Charge pumping and gated-diode methods are used to measure the interface trap density. Here, we also report the fabrication of MSB p+ and n+ contacts on SOI and measure their contact resistivity with different contact areas.
In chapter 5, the 2-D carrier/dopant profiling technique using the Kelvin-probe force microscopy (KPFM) method is first explained. To measure the surface potential, a feedback control circuit is fabricated to improve the signal response speed. The effect of the surface treatment on the surface potential image is also studied. Then the correlations between the surface potential difference measured by KPFM and the surface carrier/dopant concentration obtained by spreading resistance profiling technique, capacitance-voltage method, and secondary ion mass spectroscopy analysis are established.
Finally, in chapter 6, we summarize the important conclusions obtained in this dissertation. Some worthwhile works are suggested for the future.
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Table 1-1 Variations of circuit performances by constant-field and constant voltage scaling method. [5]
Parameter Constant-Field Scaling
Constant-Voltage Scaling
Dimensions 1/k 1/k
VDD 1/k 1
Field 1 k
Vt 1/k 1
Current 1/k 1
Capacitance 1/k 1/k
Delay Time 1/k 1/k2
Power/Circuit 1/k2 k
Power/Area 1 1/k3
Line Resistance k k
RC 1 1
IR/VDD k k2
Table 1-2 ITRS roadmap 2008 Edition. [6]
Max. parasitic series resistance for bulk NMOS (Ω/□)
Sidewall spacer thickness for bulk MPU/ASIC (nm)
29 26.7 24.8 22 19.8
Max. silicon consumption for bulk
MPU/ASIC (nm) 14.5 13.4 12.4 11 9.9
Silicide thickness for bulk
MPU/ASIC (nm) 17.9 16.2 14.7 13 12
Contact silicide sheet resistance for bulk MPU/ASIC (Ω/□)
9.1 9.9 10.8 12.1 13.5
Contact Max. resistivity for bulk MPU/ASIC (Ω-cm2)
1.25 × 10-7 1.12 × 10-7 9.87 × 10-8 9.20 × 10-8 7.00 × 10-8
Table 1-3 Basic characteristics of common used metal silicides. [19]
W
Voltage, V Wiring
Original Device
Gate
n+ n+
p substrate, Doping= NA
Lg
Xd
tox
W/k Voltage, V/k Wiring
Scaled Device
Gate
n+ n+
Doping= kNA
Lg/k tox/k
Fig.1-1 Constant-field scaling down of MOSFET. [5]
40 50 60 70 80 90 100 110