As a MOSFET device is scaled down, channel resistance decreases with decreasing gate length. Therefore, the portion of parasitic resistance becomes increasingly significant and even becomes a hindrance for device performance. In 1986, K. K. Ng and W. T. Lynch calculated the relationship between the device structure and parasitic resistance, including the contact resistance, S/D sheet resistance, spreading resistance, and accumulation resistance [28]. In 2002, S. D. Kim reported an analysis of the series resistance when CMOS was scaled to the nanometer regime [29] and suggested that the overlap and contact resistances would dominate the total resistance as a device was scaled to the nanometer level. Moreover, the contribution of contact resistance would rapidly increase due to the shrinking of the contact area and therefore contact resistance would be the major part of the total series resistance. Based on the ITRS roadmap, they calculated the series resistance of NMOS and PMOS transistors, and found that the silicide-diffusion contact resistance always accounts for a large proportion of the total series resistance: 49% in an NMOSFET and 34.5% in a PMOSFET, as shown in Fig.1-2 [29]. MGFETs and GAAFETs are two structures that use sidewalls to increase the effective channel
width and improve the gate-controllability. However, the problem of a smaller contact area, which causes a higher contact resistance, is still unsolved. If the contact resistance is larger than the channel resistance, the scaling down of the device would be meaningless. Therefore, a method to effectively reduce the parasitic resistance is an important issue.
1-3 Motivation
The possible applications of nickel silicide in the microelectronic industry have been studied since the early 1980s. The main issue with NiSi is its poor thermal stability, including thin film agglomeration and high-resistivity phase (NiSi2: 40~50 µΩ-cm) transformation [19]. Since the line width and thickness of NiSi are continuously being scaled down, a new technique to improve its thermal stability is required. Several methods have been proposed to improve the thermal stability of a NiSi film on a Si substrate. For example, fluorine ion implantation [30,31], nitrogen ion implantation [32,33], capping layers [34,35], palladium (Pd) incorporation [36], and platinum (Pt) incorporation [37-38] have all been tried. Among these methods, Pt incorporated Ni silicide showed the most promising results. A drawback of Pt-incorporation is the higher resistivity due to Pt doping.
In the 1980s, Ge ion implantation was reported as a substrate amorphization technique to eliminate the dopant channeling effect [39-41]. Several investigations on the effects of the Ge pre-amorphization implantation (PAI) process on metal-silicide formation have been reported [42-45]. Most of these papers have focused on Ti-silicides and Co-silicides. High-dose Ge PAI can improve the thermal stability of TiSi2, while low dose (≤ 1 × 1015 cm-2) Ge PAI does not play any role [44]. On the
other hand, the incorporation of Ge causes an increase in the nucleation temperature of CoSi2 from about 600 °C to about 800 °C [45]. The effects of Ge incorporation on Ni-silicides were reported recently [46-50]. Kittl et al. found that Ge PAI can increase the growth rate of Ni2Si at 250 °C [46]. Surdeanu et al. reported that a shallow junction and better short channel effect in MOSFETs can be obtained with Ge PAI [47]. Yun et al. observed that Ge PAI to a dose of 1×1014 cm-2 could cause a smooth NiSi/Si interface and suppressed the oxidation on arsenic doped n+ Si [48]. However, medium dose Ge PAI did not affect the thermal stability of NiSi. The retardation of the phase transformation from NiSi to NiSi2 was found on a SixGe1-x substrate, but the NiSi agglomeration and Ge out-diffusion on a SixGe1-x substrate were worse than those on a Si substrate [49,50]. Kim et al. reported that a thin Si capping layer on a Si0.81Ge0.19 substrate could improve the NiSi(Ge) agglomeration temperature due to the strain effect [51].
According to the above reports, a suitable concentration of Ge-incorporation may benefit the thermal stability of NiSi films, but the effect of Ge-incorporation on the NiSi-contacted shallow junction has not been investigated. This thesis discusses a thorough study of the thermal stability improvement of NiSi/Si (S/D contacts) and NiSi/poly-Si (gate contacts) structures by Ge ion implantation. The effects of Ge ion implantation on the electrical characteristics of shallow n+-p and p+-n junctions were also examined.
For non-classical MOSFET structures, which were generally fabricated on an SOI substrate for SCE improvement, NiSi was reported to have good thermal stability even when the formation temperature was over 900 °C. Because the junction depth is limited by the thickness of the top Si layer, the junction improvement of UTBFETs, MGFETs, and GAAFETs focused on the reduction of the S/D resistance and S/D lateral diffusion length. Schottky-barrier (SB) MOSFETs have some advantages such
as a superior scaling ability due to the abrupt S/D junctions, low extrinsic parasitic resistance, and process compatibility with CMOS technology [52,53]. Because of the inherent physical scalability, the abrupt junction formed at the silicide/Si interface was beneficial to the scaling-down of the gate length to the sub-10-nm region. The Schottky barrier at the source side can also improve the drain induced barrier lowering (DIBL) and SCE [54]. However, SB MOSFETs were often fabricated with mid-gap-metal silicides, such as NiSi. These provide extremely poor saturation driving-currents and high subthreshold leakage currents due to a high gate induced drain leakage (GIDL) and junction leakage [53]. In 2004, Kinoshita et al.
demonstrated a 50-nm high-performance Schottky-like NMOSFET device by using a dopant-segregation (DS) technique to form an approximately 10-nm-thick interfacial dopant layer at the source and drain [55,56]. Then in 2005, B. Y. Tsui and C. P. Lin reported a Modified-Schottky-Barrier (MSB) FinFET on SOI, which had an S/D extension-like interfacial layer placed between the silicide S/D and channel region, provided by an implant-to-silicide (ITS) technology [57]. This interfacial dopant layer was thought to be created by a dopant segregation effect. The main advantage of Schottky-like devices is the ability to reduce the effective barrier height for n and p-type Si due to different implanted dopants. Thus, they can also keep the driving current high enough and eliminate the subthreshold leakage current.
Using the reported ITS method, we fabricated some MSB n+-p and p+-n junctions.
The purpose of this thesis is to make a differential comparison of an MSB junction’s characteristics on SOI substrate, including P+, As+, and BF2+
doping. Different thermal budgets were tested to examine their segregation efficiency. In addition, we measured the electrical characteristic of MSB junctions.
The importance of contact resistance was stated in section 1-3. The contact resistances of Ge I/I and MSB junctions are also an interesting topic for device scaling;
both of them are still unknown. Some studies have reported that Ge ions can assist Boron doping activation [58]. The segregated dopant concentration dominates the barrier height and contact resistance of an MSB junction. Thus, based on measurements using the cross bridge Kelvin resistor (CBKR) method [59,60], we designed some structures to obtain their contact resistances.
For non-classical MOSFETs, there is another disadvantage with regard to electrical characteristic analysis. In order to simulate and model device performance precisely with technology computer aided design (TCAD) tools, the measurement of the two-dimensional (2-D) carrier/dopant distribution is becoming increasingly important. However, traditional methods like SRP and SIMS cannot be applied to these non-classical MOSFET structures. Scanning probe microscopy might be a possible solution to measure the 2-D carrier concentration of a device’s cross section.
Thus, Kelvin-probe force microscopy (KPFM) [61-62] was used to measure the 2-D carrier concentration of a p-n junction in our report.