矽化鎳之熱穩定性與超淺接面應用的研究

國

立

交

通

大

學

電子工程學系 電子研究所

博 士 論 文

矽化鎳之熱穩定性與超淺接面應用的研究

A Study on the Thermal Stability and Shallow Junction

Applications of Nickel Silicide

研 究 生：謝志民

指導教授：崔秉鉞 教授

矽化鎳之熱穩定性與超淺接面應用的研究

A Study on the Thermal Stability and Shallow Junction

Applications of Nickel Silicide

研 究 生：謝志民 Student：Chih-Ming Hsieh

指導教授：崔秉鉞 Advisor：Bing-Yue Tsui

國 立 交 通 大 學

電子工程學系 電子研究所

博 士 論 文

A Dissertation

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy in

Electronics Engineering October 2009

Hsinchu, Taiwan, Republic of China

矽化鎳之熱穩定性與超淺接面

應用的研究

研究生

研究生

研究生

研究生：

：

：

：謝志民

謝志民

謝志民

謝志民 指導教授

指導教授：

指導教授

指導教授

：

：崔秉鉞

：

崔秉鉞

崔秉鉞 博士

崔秉鉞

博士

博士

博士

國立交通大學

國立交通大學

國立交通大學

國立交通大學

電子工程

電子工程

電子工程

電子工程學

學

學系

學

系

系 電子研究所

系

電子研究所

電子研究所

電子研究所

摘要

摘要

摘要

摘要

在現今微縮驅使下，矽化鎳是最常用在先進製程中的金屬矽化物。在矽化鎳熱穩 定性及接面特性之研究方面，本論文提出利用高劑量鍺離子佈值來改善其熱穩定性。 我們發現在矽基板上，鍺摻雜可提升結塊及二矽化鎳相轉變溫度各攝氏 50~100 度。 而將其利用在高摻雜之 n 型或 p 型矽基板上時，因受其它高摻雜離子影響，改善程度 只有攝氏 50 度左右，但是對於 n 型或 p 型多晶矽閘極，卻仍保有攝氏 100 度的改善 能力。此外還發現高劑量鍺離子佈值可以改善矽化鎳與矽的介面平坦度。在熱穩定性 研究的基礎下，進一步研究 n 型或 p 型二極體特性的改善。我們發現對於漏電流而言， 雖然有鎳沿著鍺離子佈植產生的缺陷往下擴散之影響，仍可以看出對週邊漏電流降低 以及整體漏電流耐溫增加的改善。 為了減少寄生電容及改善短通道效應，電晶體結構趨向多閘極結構，並可能進一 步製作在絕緣層上矽(SOI)的晶片上面。由於先將離子植入矽化鎳，再經過退火後， 會使得佈值離子被離析到矽中，可形成超淺接面，本論文遂利用此技術在 SOI 上製做 並研究超淺接面之特性。在現今常用的二氟化硼(BF2+)、磷(P+)、砷(As+)離子佈值入

矽化鎳後再經由攝氏 500~750 度的再退火製程，可以發現其具有良好的熱穩定性及可 得到遠低於矽化鎳蕭基特接面的漏電流。在此也針對其週邊二氧化矽介面造成漏電流 的捕獲能態密度進行探討，藉由閘極二極體(gated-diode)及電荷捕捉(charge pumping) 兩種方法量測捕獲能態密度的大小，分析漏電流機制。 針對上述兩種在不同基板上製作的超淺接面，我們製作不同的結構來量測此兩種 接面的矽化鎳/矽的接觸阻抗。在矽基板上，經過鍺離子佈值後，矽化鎳對高摻雜 p 型基板的接觸阻抗可以低到 10-8 _Ω-cm2_{的數量級，而在 SOI 上可量到 BF} 2+佈值的接 面有 2

×

10-8 Ω-cm2_{的低接觸電阻率，而 P}+_{佈值的接面則有偏高的 3}

_×

10-7的接觸電 阻率。

最後我們希望利用掃描探針顯微術之ㄧ的 Kelvin-Probe Force Microscopy (KPFM) 來量測半導體表面電位差，透過常用的的幾種不同一維載子濃度分布測定方法為基 準，來推算表面二維載子濃度分布。雖可成功利用在較深的 p-n 接面剖面濃度的分析， 但是空間解析度不理想，尚待改善。 整體而言，本論文研究了利用鍺離子佈植改善矽化鎳的熱穩定性和利用離子植入 矽化鎳再經退火之方法改善蕭基特二極體接面的電特性，以及研究了它們的接觸阻抗 大小並期待利用 KPFM 來量測超淺接面深度。

A Study on the Thermal Stability and

Shallow Junction Applications of Nickel Silicide

Student：

：

：Chih-Ming Hsieh Advisor：

：

：

：

：Dr. Bing-Yue Tsui

Department of Electronics Engineering & Institute of Electronics

Nation Chiao-Tung University

Abstract

In the ULSI IC industry, as the gate length is being scaled down to the nanometer level, metal silicides are being used as contact materials to reduce parasitic resistance. Among the different silicide materials, nickel silicide is the most popular. In a study on the thermal stability and junction properties of nickel monosilicide (NiSi), I proposed high-dosage germanium ion implantation (Ge I/I > 5 × 1015 cm-3) before silicide formation to improve the thermal stability. The experimental results showed that Ge implantation resulted in an improvement in both the phase transformation and agglomeration temperatures of NiSi by 50~100 _{°C. We applied this technique to NiSi contacted n}+-p and p+-n shallow junctions. The improvement was reduced to 50 _{°C due to the high} concentration of dopants in the bulk-Si substrate. However, the application to a highly doped poly-Si gate yielded in improvements by 100 _{°C. Additionally, for samples} implanted with Ge I/I before NiSi formation, we found a very smooth NiSi/Si interface at 750 _{°C. Although fast Ni diffusion via the defects induced by the Ge I/I was present, we} still observed smaller peripheral leakage currents and better thermal stability by electrical characterization.

Multi-gate transistors fabricated on silicon-on-insulator (SOI) wafers were developed against the short channel effect and demonstrated lower parasitic capacitance. When using the implant-to-silicide (ITS) technique, the implanted atoms diffused out of the silicide and piled up at the silicide/silicon interface during the post-annealing process. The segregated atoms formed an ultra-shallow junction. In my study, the ITS technique was utilized to fabricate lateral modified Schottky barrier (MSB) junctions on SOI wafers. BF2+, As+, and

P+ dopants were used and the electrical characteristics of the diodes after annealing from 500 _{°C to 750 °C were compared. It was found that the MSB junction maintained a good} thermal stability and had much lower leakage currents than the NiSi contacted SB junction. We also measured the interface trap density between the Si and SiO2 of MSB p+-n and n+-p

diodes. Charge pumping and gated diode methods were used to measure the interface trap density and analyze the leakage current mechanism for MSB diodes.

We designed contacts and structures with different dimensions to measure the contact resistance of the NiSi/Si interface for a p+-n junction with Ge I/I on bulk-Si and MSB junctions on SOI. The specific contact resistivity for the p+-n junction with Ge I/I was around 10-8 Ω-cm2, 2 × 10-8 Ω-cm2 for the p+ MSB contact, and 3 × 10-7 Ω-cm2 for the n+ MSB contact.

Finally, we demonstrated a two-dimensional (2-D) carrier/dopant profiling technique that uses Kelvin-probe force microscopy (KPFM) to measure the surface potential of a p-n junction. The correlations between the surface potential difference measured by KPFM and the results of secondary ion mass spectroscopy (SIMS), the surface carrier concentration obtained by spreading resistance profiling, and the capacitance-voltage method were established. These results indicate that 2-D carrier depth profiling of a p-n junction was successfully achieved.

To summarize, the thermal stability and junction properties of NiSi were improved by Ge I/I and ITS techniques, respectively. The contact resistances were measured, and a 2-D

carrier depth profiling technique was proposed, which is expected to be very useful for NiSi contacted ultra-shallow junction applications in the future.

Contents

Abstract (Chinese)……….………i

Abstract (English)…..………...…..iii

Contents………..………..…....vi

Acknowledgements…………...………... ix

Table Captions...……..………..x

Figure Captions....………..………..……...xi

Chapter 1 Introduction…..………..1

1-1 Scaling down of CMOS…...……….………...1

1-2 Scaling down of a Junction……...………..…...2

1-2-1 Contact Silicide Issues for a Junction……….3

1-2-2 Series Resistance Issues for a MOSFET………...4

1-3 Motivation……..………..…………5

1-4 Thesis Organization...………..……...………..8

Chapter 2 Improvement of Nickel Silicide Characteristics with

Germanium Ion Implantation………..………....…...23

2-1 Introduction ……….………..23

2-2 Samples Preparation and Experimental Procedures………...25

2-2-1 Ni-Silicides on Bulk-Si Substrate……….………...…….25

2-2-2 Ni-Silicides on Heavily Doped Si Substrate……….26

2-2-3 Material Analysis……….……….27

2-3 Results and Discussion ….……….…...……….28

2-3-1 Ni-Silicides on Bulk-Si Substrate…..………...……...28

2-3-2 Ni-Silicides on Heavily Doped Bulk-Si Substrate...32

2-4 Conclusions………...……….36

Chapter 3 Electrical Characteristic of NiSi Shallow Junction

with Ge Ion Implantation ……...………....65

3-1 Introduction……...………..………65

3-2 Experimental procedures…..……….……….66

3-2-1 Junction Sample Preparation……….66

3-2-2 Cross Bridge Kelvin Resistor Structure Fabrication…..……...67

3-2-3 Analysis Method………...68

3-2-4 Characterization Techniques……….68

3-3 Results and Discussion………..….………….………...69

3-3-1 Electrical Properties of n

+

-p Shallow Junctions………....69

3-3-2 Electrical Properties of p

+

-n Shallow Junctions………....71

3-3-3 Contact Resistance Measurement………...………..73

3-4 Conclusions……….…..…..………..…….74

Chapter 4 Electrical Characteristics of NiSi Modified Schottky

Barrier Lateral Junction on SOI substrate

_{…..………...98}

4-1 Introduction……….………..….………98

4-2 Experimental procedures……….………….………..…..……100

4-2-1 MSB Junction Device Preparation………...………...…100

4-2-2 Device Preparation for CKR structure on SOI…...…………101

4-2-3 Analysis Method………..…...…102

4-3 Results and Discussion………..…………...…….……...102

4-3-1 Thermal Stability of NiSi on SOI………102

4-3-2 Electrical Characteristics of Conventional Junctions……….103

4-3-4 Interface Trap density Measurement of MSB Junctions…….106

4-3-5 Contact Resistance Measurement…….………..…....107

4-4 Conclusions………....………..108

Chapter 5 Carrier Concentration Profiling of P-N Junction by

Kelvin-Probe Force Microscopy…..………..143

5-1 Introduction…..………...………….143

5-2 Operating Principle and System Setup…..………...144

5-3 Experimental procedures…..………....147

5-4 Results and Discussion…..…….……….……….149

5-4-1 Effects of surface treatment………149

5-4-2 Correlation between surface potential difference

and surface carrier/dopant concentration………150

5-4-3 Depth profiling of p-n junction and detection of

junction array………..152

5-5 Conclusions……..………..……..…………153

Chapter 6 Summary and Future Works…..………...175

6-1 Summary…..………175

誌

誌

誌

誌 謝

謝

謝

謝

能夠順利完成論文，我想感謝我的指導教授 崔秉鉞老師。感謝

老師在我這七年來博士生涯中實驗、研究、與論文上的指導跟教誨，

並感謝老師在我遇到困難跟發生意外時給予的關懷，謝謝老師的體諒

跟這麼多年來的照顧。

其次我要感謝在實驗上提供幫助的國家奈米元件實驗室、交通大

學奈米中心、清大果老師實驗室跟漢民科技公司提供優良的機台設備

以及管理完善的實驗環境使得實驗可以順利進行，並感謝在奈米中心

跟 NDL 廠內服務的技術人員們，謝謝你們提供的服務與實驗上寶貴

經驗和建議。

感謝我的實驗室伙伴們，謝謝已畢業學長及同學們: 國龍、家

彬、誌鋒、琪聰、修維、偉豪、明賢們在實驗上幫忙跟規劃，也謝謝

畢業或在學的學弟妹們能在漫漫長夜的無塵室內一起打拼，也特別感

謝俊凱跟振銘學弟在我車禍時生活上的幫忙，真的很謝謝大家。其次

我想感謝這麼多年來一起打球的龍捲風隊員跟東方球隊的大叔們，能

跟你們打球真的很快樂，也謝謝你們在為人處世上提供的寶貴經驗。

最後我想感謝我的家人母親、大哥跟大嫂、妹妹跟舅舅、姑姑們，

謝謝你們的支持跟這麼多年來的栽培與體諒，也希望在天上的父親跟

阿嬤可以替我高興。

Table Captions

Chapter 1

Table 1-1 Variations of circuit performances by constant-field and constant voltage scaling method………...………18 Table 1-2 ITRS roadmap 2008 Edition……….19 Table 1-3 Basic characteristics of common used metal silicides………..20

Chapter 2

Table 2-1 Process split conditions of the blanket samples.……….…..43 Table 2-2 Process split conditions of the p-n junction samples.……….…………..43 Table 2-3 Process split conditions of the gate samples.……….….…..44 Table 2-4 Summary of the thin film agglomeration temperatures and phase transformation

temperatures of the blanket control samples, GIBS samples and GIAS samples….44

Chapter 4

Table 4-1 Average leakage currents of MSB p+-n junction annealed at 600 oC………..……112

Chapter 5

Table 5-1 Surface treatment methods and samples IDs used in this work………..……159

Chapter 6

Figure Captions

Chapter 1

Fig.1-1 Constant-field scaling down of MOSFET………..21 Fig.1-2 Series resistance of (a) NMOS and (b) PMOS transistors with different gate

lengths………..………22

Chapter 2

Fig.2-1 Normalized sheet resistance values (Rs) of the GIBS samples after annealing

at different temperatures for 10 sec. The sheet resistance values are normalized to those of the 500 _{°C annealed samples………...45} Fig.2-2 Normalized sheet resistance values (Rs) of the GIAS samples after annealing

at different temperatures for 10 sec. The sheet resistance values are normalized to those of the 500 _{°C annealed samples. ……….………...46} Fig.2-3 Normalized sheet resistance values (Rs) of the GIBS and GIAS samples with

Ge I/I at 40 and 50 keV, respectively to a dose of 1 × 1016 cm-2. The annealing time is 30 sec. The sheet resistance values are normalized to those of the 500 °C annealed samples.………...…………47 Fig.2-4 Surface morphology inspected by SEM of the control sample, GIBS and GIAS samples after annealing at different temperatures for 30 sec………...…….48 Fig.2-5 XRD spectra of the control sample after annealing at different temperatures for 30 sec………...…………..49 Fig.2-6 XRD spectra of the GIBS samples with Ge ion implantation at 50 keV to a

sec………...……….50 Fig.2-7 XRD spectra of the GIAS samples with Ge ion implantation at 40 keV to a dose of 1 × 1016 cm-2 after annealing at different temperatures for 30 sec………...……….51 Fig.2-8 Cross-sectional TEM micrograph of the GIBS sample with Ge ion implantation at 50 keV to a dose of 1 × 1016 cm-2 after annealing at 750 ºC for 30 sec………...52 Fig.2-9 SIMS depth profile of Ge atoms of the GIBS samples with Ge I/I at 50 keV to a dose of 1 × 1016 cm-2 after annealing at 600 _{°C for 30 sec. The depth is} measured from the top surface of the NiSi film………..53 Fig.2-10 SIMS depth profile of Ge atoms of the GIAS samples with Ge I/I at 40 keV

to a dose of 1 × 1016 cm-2 after annealing at 600 _{°C for 30 sec. The depth is} measured from the top surface of the NiSi film…………..………54 Fig.2-11 (a) Normalized sheet resistance values and (b) Plan-view SEM images of the

NiSi films on n+-Si layer after annealing at different temperatures for 30 sec. The sheet resistance values are normalized to those of the 500 _{°C annealed} samples………...……….55 Fig.2-12 (a) Normalized sheet resistance values and (b) Plan-view SEM images of the

NiSi films on p+-Si layer after annealing at different temperatures for 30 sec. The sheet resistance values are normalized to those of the 500 _{°C annealed} samples………56 Fig.2-13 XRD analysis results for (a) n+-p GeI/I and (b) p+ -n junction samples at

different RTA annealing temperatures for 30 sec………57 Fig.2-14 Cross-sectional TEM micrographs of the (a) n+-p and (b) p+-n samples with

Ge I/I after annealing at 600 _{°C for 30 sec………..58} Fig.2-15 Normalized sheet resistance values of Ni silicide on n+ and p+ poly-Si gate

for Ge I/I and without Ge I/I samples as a function of RTA annealing temperature. The sheet resistance values are normalized to those of the 500 _°C annealed samples………...………..59 Fig.2-16 XRD analysis results for (a) without and (b) with Ge I/I on p+ gate at different RTA annealing temperatures……….60 Fig.2-17 Plan-view SEM images of NiSi for (a)~(c) with GeI/I and (d)~(f) without GeI/I samples after various RTA annealing temperatures for 30 s on n+ gate.61 Fig.2-18 Plan-view SEM images of NiSi for (a)~(c) with GeI/I and (d)~(f) without

GeI/I samples after various RTA annealing temperatures for 30 s on p+ gate.62 Fig.2-19 Cross-sectional view SEM images of NiSi (a)~(c) for n+ and (d)~(f) for p+ on GeI/Igate samples after various RTA temperature for 30 s………....63 Fig.2-20 SIMS analysis results for Ge I/I on n+_{gate after silicide formation at 650} o_C

RTA annealing for 30 s……….64

Chapter 3

Fig.3-1 A cross Kelvin resistor (CBKR) test structure……….………...79 Fig.3-2 Basic I-V characteristic of n+-p shallow junction (a) without and (b) with Ge ion implantation (Ge I/I)……….80 Fig.3-3 n values of the n+-p junctions……….81 Fig.3-4 Surface roughness of NiSi/Si interface on n+-p shallow junction by AFM Ge

I/I and (b) without Ge I/I……….82 Fig.3-5 Reverse biased junction leakage current statistics of the n+-p shallow

junctions after annealing at different temperatures for (a) 30 and (b) 60sec..83 Fig.3-6 SIMS depth profiles of the 600_{°C annealed n}+-p junctions (a) with and

Fig.3-7 JR versus P/A plot of (a) with and (b) without Ge I/I n+-p shallow junctions

annealed at different temperature. The extracted JRA and JRP values were

respectively plotted as (c) and (d).………..85 Fig.3-8 Activation energy of the (a) with and (b) without Ge I/I n+-p shallow

junctions annealed at 600 oC…….………..86 Fig.3-9 Basic I-V characteristic of p+-n shallow junction (a) without and (b) with Ge

ion implantation (Ge I/I)………..87 Fig.3-10 n values of the p+-n junctions………88 Fig.3-11 Reverse biased junction leakage current statistics of the p+-n junctions after annealing at different temperatures for 30 sec……….89 Fig.3-12 SIMS depth profiles of the 600 _{°C annealed p}+-n junction with Ge I/I…....90 Fig.3-13 TEM image of the 800 _{°C annealed p}+-n junction without Ge I/I…………91 Fig.3-14 JR versus P/A plot of (a) with and (b) without Ge I/I p+-n shallow junctions

annealed at different temperature. The extracted JRA and JRP values were

respectively plotted as (c) and (d)………...92 Fig.3-15 Activation energy of the (a) with and (b) without Ge I/I n+-p shallow

junctions annealed at 600 oC……….………..93 Fig.3-16 Current paths and calculation formula of L-type and D-type………...94 Fig.3-17 Fabricated D-typ CBKR structure with Ge I/I on p+-Si…………..………..95 Fig.3-18 Measured contact resistance of D-type structure………..96 Fig.3-19 Measured contact resistance of D-type structure with 0.5 µm hole size…..97

Chapter 4

Fig.4-1 Process flow for MSB n+-p junction……….113 Fig.4-2 TEM cross section view of MSB n+ region edge………...…….…..114

Fig.4-3 Two categories of MSB junction’s active region. (a) is Island type marked as “I“, and (b) is Line type marked as “L“………..……..……….115 Fig.4-4 Sheet resistance values of the ITS samples after annealing at different temperatures for 30 sec……….……….116 Fig.4-5 XRD spectra of the P implanted ITS samples after annealing at different temperatures for 30 sec……….….117 Fig.4-6 XRD spectra of the As implanted ITS samples after annealing at different temperatures for 30 sec………..…118 Fig.4-7 XRD spectra of the BF2 implanted ITS samples after annealing at different

temperatures for 30 sec………..119 Fig.4-8 Plan-view SEM images of NiSi with P implanted ITS samples after various RTA annealing temperatures for 30s on SOI……….………120 Fig.4-9 Plan-view SEM images of NiSi with BF2 implanted ITS samples after various

RTA annealing temperatures for 30s on SOI……….121 Fig.4-10 Plan-view SEM images of NiSi with As implanted ITS samples after various

RTA annealing temperatures for 30s on SOI……….122 Fig.4-11 Basic I-V characteristic of conventional n+-p and p+-n junctions, the width

of them were designed as 500 or 1000 μ m for L and I type junctions………....123 Fig.4-12 Basic I-V characteristic of conventional n+-p and p+-n junctions after

passivation oxide annealed at 950oC for 30 min in N2……….….124

Fig.4-13 Reverse biased (3V) junction leakage current statistics of the (a) n+-p and (b) p+-n junction after passivation oxide annealed at 950oC for 30min in N2………...125

Fig.4-14 Reverse biased (3V) junction leakage current statistics of the (a) 500I and (b) 1000I type MSB p+-n junctions. ………...126

Fig.4-14 Reverse biased (3V) junction leakage current statistics of the (c) 500L and (d) 1000L type MSB p+-n junctions. ………...………….127 Fig.4-15 Band diagram of (a) Schottky and (b) MSB p+-n junction at reverse

biased……….128 Fig.4-16 Reverse biased (3V) junction leakage current statistics of the (a) 500I and (b)

1000I type MSB n+-p junctions with As+ implantation……….…….129 Fig.4-16 Reverse biased (3V) junction leakage current statistics of the (c) 500L and

(d) 1000L type MSB n+-p junctions with As+ implantation………...130 Fig.4-17 Reverse biased (3V) junction leakage current statistics of the (a) 500I and (b)

1000I type MSB n+-p junctions with P+ implantation………...131 Fig.4-17 Reverse biased (3V) junction leakage current statistics of the (c) 500L and (d) 1000L type MSB n+-p junctions with P+ implantation………..….132 Fig.4-18 (a) Activation energy of 600 oC in 1000I type junction, and (b) Summary of Ea in different post-annealed conditions of MSB p+-n

junctions……….…...133 Fig.4-19 Activation energy of 600 oC annealed MSB n+-p 1000I junction (a) with P+ implantation and (b) with As+ implantation………..134 Fig.4-20 Schematic diagrams of gated-diode method (a) was the measurement setup

diagram and (b) was the measured I-V characteristic……….………...135 Fig.4-21 Gated-diode I-V characteristics of MSB (a) p+-n and (b) n+-p for 1000I type 600 oC annealed junction……….…..136

Fig.4-22 (a) measurement schematic diagram and (b) band diagram vs I-V characteristics of charge pumping method……….…...137 Fig.4-23 Charge pumping method measured Icp versus Vbase result………..138

Fig.4-24 (a) Icpmax. versus Frequency Plot and (b) Qss versus ln(f) Plot…………..139 Fig.4-25 Fabricated lateral CBKR structure on SOI……….………140 Fig.4-26 Measured specific contact resistivity values of n+ MSB contact…………141 Fig.4-27 Measured specific contact resistivity values of p+ MSB contact…………142

Chapter 5

Fig.5-1Block diagram of the KPFM with an external feedback control module used in this work………160 Fig.5-2 (a) Circuit and (b) Band diagram schematic drawing of a p-n junction

measured by a KPFM system………..………..161 Fig.5-3 Surface potential image of a p-n junction measured by KPFM with a built-in feedback control circuit……….162 Fig.5-4 Block diagram of the external feedback control circuit………163 Fig.5-5 Surface potential image of a p-n junction measured by KPFM with an external feedback control circuit………..…….164 Fig.5-6 Surface potential images of samples A, B, C, and D measured by KPFM. The

surface treatment methods for the four samples are listed in Table I………165 Fig.5-7 The F 1s binding energies of samples A and B measured by XPS………...166 Fig.5-8 The O 1s binding energies of samples A and B measured by XPS………...167 Fig.5-9 Surface potential images of samples with different ion implantation conditions: (a) As+ 5 × 1015, (b) As+ 2 × 1014, (c) BF2+ 5 × 1015 and (d) BF2+ 2

Fig.5-10 Surface potential images with BF2+ implantation at a dose of 5 × 1015

cm-2………..………….169 Fig.5-11 Correlation between surface potential difference and surface carrier concentration of the n+-p junctions with different As+ ion implantation doses………..170 Fig.5-12 Correlation between surface potential difference and surface carrier

concentration of the p+-n junctions with different BF2+ ion implantation

doses………..171 Fig.5-13 Surface image and the potential profile of a p+-n junction in vertical

direction after cleaving and polishing………...172 Fig.5-14 Carrier depth profiles of the p+-n junction shown in Fig.13 measured by

KPFM and SIMS………...173 Fig.5-15 Surface potential image of p-n junction array (a) 0.8 × 0.8 µm2 and (b) 0.4 ×

Chapter 1

Introduction

1-1 Scaling down of CMOS

In 1960, the first successful metal-oxide-semiconductor field-effect transistor (MOSFET) was demonstrated by D. Khang and M. M. Atalla [1]. Later, the first CMOS circuit was invented by Frank Wanlass in 1963 [2]. The CMOS circuit gradually went on to become the building block of integrated circuits. In order to obtain high-performance, high-density MOSFET devices, it became necessary to scale down the dimensions of these devices; it was found that this scaling down followed Moore’s Law, proposed in 1965 [3]. The paper, “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” published in 1974, is regarded as providing the earliest guiding principle for MOSFET, circuit, and chip design [4]. Table 1-1 shows the variation in circuit performance obtained by constant-field scaling or constant-voltage scaling [5]. The basic aim of these methods is to scale down the size of a MOSFET by a factor “k” to produce a smaller MOSFET with similar electrical behavior. In constant-field scaling, for example, all voltages and dimensions are reduced by a scaling factor, and the doping and charge densities are increased by the same factor. However, the parameters of a MOSFET were tuned to eliminate the disadvantages of constant-field scaling, as illustrated in Fig.1-1 [5]. No matter which type of scaling method is used, as the device is scaled down, the resistance effects become more and more pronounced. Since 1992, the Semiconductor Industry Association has annually published The International Technology Roadmap

for Semiconductors (ITRS). This roadmap provides future technology targets for the semiconductor industry.

As mentioned above, devices are scaled down for achieving better performance, higher device density, lower operation voltage, and also lower cost. However, there are some disadvantages that arise as a result of devices being scaled down: The parasitic resistance increases when the dimensions of a device are reduced, the gate leakage current increases as the gate oxide thickness shrinks, and the short channel effect (SCE) becomes increasingly pronounced as the gate control capability weakens. ITRS reports have suggested some new materials and structures that might provide solutions to these problems [6]. The parasitic resistance can be reduced by using a metal gate, increasing S/D, and using a silicide contact. High-dielectric constant dielectrics can be used to reduce the effective oxide thickness and gate leakage currents, while maintaining better performance than before [7,8]. Several methods have been proposed to suppress the SCE, such as raising the substrate doping concentration, utilizing ultra-shallow source/drain (S/D) junctions, and increasing gate controllability [9]. Some structures have been invented to enhance the gate control capability and suppress the SCE, such as ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs [10,11], multigate (MG) FETs [12-14], and gate-all-around (GAA) FETs [15]. Most of these structures have been fabricated on an SOI substrate. An additional advantage of an SOI wafer is that the bottom oxide layer (BOX) can also reduce the parasitic capacitance [16].

1-2

Scaling down of a Junction

We now focus on the effects of junction scaling: the scaling down of the junction depth and series resistances of a MOSFET. Table 1-2 lists some important parameters

stipulated by the 2008 ITRS roadmap [6], such as the junction depth, junction leakage current, silicide sheet resistance, silicide thickness, and contact resistivity. Junction depth scaling includes reducing the diffusion depth of the dopant and shrinking the thickness of the contact silicide. The series resistances are dominated by silicide materials, which affect the Schottky barrier height between the silicide and junction, and the activated dopant concentration of the junction.

1-2-1 Contact Silicide Issues for a Junction

Metal silicides have been used in the Si microelectronics industry for more than thirty years. Since the first paper on the application of metal silicide to doped poly-silicon for low-resistivity interconnections was published in 1979 [17], many noble and refractory metals have been found to have potential to form stable silicide with silicon. In the integrated circuit industry, metal silicides are usually used as contact materials at source, drain, and gate regions. Their low sheet resistances are an important virtue in device applications for reducing the parasitic resistance and signal propagation delay time [18]. Table 1-3 shows the characteristics of some commonly used metal silicides [19].

Titanium disilicide (TiSi2) was the first metal silicide successfully used in the IC

industry [18]. However, its phase transformation from the high-resistivity phase (C49-TiSi2: 60~80 µΩ-cm) to the low-resistivity phase (C54-TiSi2: 10~16 µΩ-cm)

becomes more and more difficult as the line width shrinks to less than 0.2 _{µm [20-23].} Unlike TiSi2, CoSi2 solves the narrow line width impact on sheet resistance and also

the bridging effect. Therefore, at the 0.18 _{µm technology node, TiSi}2 was replaced by

cobalt disilicide (CoSi2: 14~20 µΩ-cm) [22,24]. However, the high Si volume

consumption during CoSi2 formation is no longer acceptable after the 90-nm node

junction.

Recently, nickel monosilicide (NiSi: 14~20 µΩ-cm) has become a popular contact material due to its low sheet resistance. Moreover, NiSi has less Si consumption (0.82 nm Si for 1 nm NiSi), low film stress, and low formation temperature (~350 °C) [19,25-27]. The main problem with NiSi is its poor thermal stability, and some improvements should be made to integrate NiSi into nanometer-scale device fabrication.

1-2-2 Series Resistance Issues for a MOSFET

As a MOSFET device is scaled down, channel resistance decreases with decreasing gate length. Therefore, the portion of parasitic resistance becomes increasingly significant and even becomes a hindrance for device performance. In 1986, K. K. Ng and W. T. Lynch calculated the relationship between the device structure and parasitic resistance, including the contact resistance, S/D sheet resistance, spreading resistance, and accumulation resistance [28]. In 2002, S. D. Kim reported an analysis of the series resistance when CMOS was scaled to the nanometer regime [29] and suggested that the overlap and contact resistances would dominate the total resistance as a device was scaled to the nanometer level. Moreover, the contribution of contact resistance would rapidly increase due to the shrinking of the contact area and therefore contact resistance would be the major part of the total series resistance. Based on the ITRS roadmap, they calculated the series resistance of NMOS and PMOS transistors, and found that the silicide-diffusion contact resistance always accounts for a large proportion of the total series resistance: 49% in an NMOSFET and 34.5% in a PMOSFET, as shown in Fig.1-2 [29]. MGFETs and GAAFETs are two structures that use sidewalls to increase the effective channel

width and improve the gate-controllability. However, the problem of a smaller contact area, which causes a higher contact resistance, is still unsolved. If the contact resistance is larger than the channel resistance, the scaling down of the device would be meaningless. Therefore, a method to effectively reduce the parasitic resistance is an important issue.

1-3 Motivation

The possible applications of nickel silicide in the microelectronic industry have been studied since the early 1980s. The main issue with NiSi is its poor thermal stability, including thin film agglomeration and high-resistivity phase (NiSi2: 40~50

µΩ-cm) transformation [19]. Since the line width and thickness of NiSi are continuously being scaled down, a new technique to improve its thermal stability is required. Several methods have been proposed to improve the thermal stability of a NiSi film on a Si substrate. For example, fluorine ion implantation [30,31], nitrogen ion implantation [32,33], capping layers [34,35], palladium (Pd) incorporation [36], and platinum (Pt) incorporation [37-38] have all been tried. Among these methods, Pt incorporated Ni silicide showed the most promising results. A drawback of Pt-incorporation is the higher resistivity due to Pt doping.

In the 1980s, Ge ion implantation was reported as a substrate amorphization technique to eliminate the dopant channeling effect [39-41]. Several investigations on the effects of the Ge pre-amorphization implantation (PAI) process on metal-silicide formation have been reported [42-45]. Most of these papers have focused on Ti-silicides and Co-silicides. High-dose Ge PAI can improve the thermal stability of TiSi2, while low dose (≤ 1 × 1015 cm-2) Ge PAI does not play any role [44]. On the

other hand, the incorporation of Ge causes an increase in the nucleation temperature of CoSi2 from about 600 °C to about 800 °C [45]. The effects of Ge incorporation on

Ni-silicides were reported recently [46-50]. Kittl et al. found that Ge PAI can increase the growth rate of Ni2Si at 250 °C [46]. Surdeanu et al. reported that a shallow

junction and better short channel effect in MOSFETs can be obtained with Ge PAI [47]. Yun et al. observed that Ge PAI to a dose of 1×1014 cm-2 could cause a smooth NiSi/Si interface and suppressed the oxidation on arsenic doped n+ Si [48]. However, medium dose Ge PAI did not affect the thermal stability of NiSi. The retardation of the phase transformation from NiSi to NiSi2 was found on a SixGe1-x substrate, but the

NiSi agglomeration and Ge out-diffusion on a SixGe1-x substrate were worse than

those on a Si substrate [49,50]. Kim et al. reported that a thin Si capping layer on a Si0.81Ge0.19 substrate could improve the NiSi(Ge) agglomeration temperature due to

the strain effect [51].

According to the above reports, a suitable concentration of Ge-incorporation may benefit the thermal stability of NiSi films, but the effect of Ge-incorporation on the NiSi-contacted shallow junction has not been investigated. This thesis discusses a thorough study of the thermal stability improvement of NiSi/Si (S/D contacts) and NiSi/poly-Si (gate contacts) structures by Ge ion implantation. The effects of Ge ion implantation on the electrical characteristics of shallow n+-p and p+-n junctions were also examined.

For non-classical MOSFET structures, which were generally fabricated on an SOI substrate for SCE improvement, NiSi was reported to have good thermal stability even when the formation temperature was over 900 °C. Because the junction depth is limited by the thickness of the top Si layer, the junction improvement of UTBFETs, MGFETs, and GAAFETs focused on the reduction of the S/D resistance and S/D lateral diffusion length. Schottky-barrier (SB) MOSFETs have some advantages such

as a superior scaling ability due to the abrupt S/D junctions, low extrinsic parasitic resistance, and process compatibility with CMOS technology [52,53]. Because of the inherent physical scalability, the abrupt junction formed at the silicide/Si interface was beneficial to the scaling-down of the gate length to the sub-10-nm region. The Schottky barrier at the source side can also improve the drain induced barrier lowering (DIBL) and SCE [54]. However, SB MOSFETs were often fabricated with mid-gap-metal silicides, such as NiSi. These provide extremely poor saturation driving-currents and high subthreshold leakage currents due to a high gate induced drain leakage (GIDL) and junction leakage [53]. In 2004, Kinoshita et al. demonstrated a 50-nm high-performance Schottky-like NMOSFET device by using a dopant-segregation (DS) technique to form an approximately 10-nm-thick interfacial dopant layer at the source and drain [55,56]. Then in 2005, B. Y. Tsui and C. P. Lin reported a Modified-Schottky-Barrier (MSB) FinFET on SOI, which had an S/D extension-like interfacial layer placed between the silicide S/D and channel region, provided by an implant-to-silicide (ITS) technology [57]. This interfacial dopant layer was thought to be created by a dopant segregation effect. The main advantage of Schottky-like devices is the ability to reduce the effective barrier height for n and p-type Si due to different implanted dopants. Thus, they can also keep the driving current high enough and eliminate the subthreshold leakage current.

Using the reported ITS method, we fabricated some MSB n+-p and p+-n junctions. The purpose of this thesis is to make a differential comparison of an MSB junction’s characteristics on SOI substrate, including P+, As+, and BF2+doping. Different thermal

budgets were tested to examine their segregation efficiency. In addition, we measured the electrical characteristic of MSB junctions.

The importance of contact resistance was stated in section 1-3. The contact resistances of Ge I/I and MSB junctions are also an interesting topic for device scaling;

both of them are still unknown. Some studies have reported that Ge ions can assist Boron doping activation [58]. The segregated dopant concentration dominates the barrier height and contact resistance of an MSB junction. Thus, based on measurements using the cross bridge Kelvin resistor (CBKR) method [59,60], we designed some structures to obtain their contact resistances.

For non-classical MOSFETs, there is another disadvantage with regard to electrical characteristic analysis. In order to simulate and model device performance precisely with technology computer aided design (TCAD) tools, the measurement of the two-dimensional (2-D) carrier/dopant distribution is becoming increasingly important. However, traditional methods like SRP and SIMS cannot be applied to these non-classical MOSFET structures. Scanning probe microscopy might be a possible solution to measure the 2-D carrier concentration of a device’s cross section. Thus, Kelvin-probe force microscopy (KPFM) [61-62] was used to measure the 2-D carrier concentration of a p-n junction in our report.

1-4 Thesis Organization

There are seven chapters in this dissertation. In chapter 1, a brief review of the scaling down issues of metal silicide and S/D junctions is given. The motivation for the thesis is also described.

In chapter 2, the thermal stability of NiSi with Ge ion implantation (Ge I/I) is investigated. The energies and dosages of Ge I/I before and after silicide formation are examined to test the efficiency improvement. Applications on differential substrates for poly-Si and bulk-Si are also carried out. The sheet resistance, SEM, TEM, AFM, SIMS, and XRD are employed to examine the thermal stability of NiSi.

junction fabrication. The electrical characteristics of p+-n and n+-p junctions with Ge I/I are investigated in detail. We also discuss the temperature and time effects for the junction leakage. The contact resistance between the NiSi and p+ Ge I/I layer is measured by the CBKR structure.

In chapter 4, the ITS technology is utilized in the fabrication of MSB p+-n and n+-p lateral junctions on SOI. The electrical characteristics of MSB p+-n and n+-p junctions are discussed. Different temperatures and durations are used to examine the dopant segregation efficiency. The interface trap density between the Si and SiO2 of

the MSB p+-n and n+-p junctions is also measured. Charge pumping and gated-diode methods are used to measure the interface trap density. Here, we also report the fabrication of MSB p+ and n+ contacts on SOI and measure their contact resistivity with different contact areas.

In chapter 5, the 2-D carrier/dopant profiling technique using the Kelvin-probe force microscopy (KPFM) method is first explained. To measure the surface potential, a feedback control circuit is fabricated to improve the signal response speed. The effect of the surface treatment on the surface potential image is also studied. Then the correlations between the surface potential difference measured by KPFM and the surface carrier/dopant concentration obtained by spreading resistance profiling technique, capacitance-voltage method, and secondary ion mass spectroscopy analysis are established.

Finally, in chapter 6, we summarize the important conclusions obtained in this dissertation. Some worthwhile works are suggested for the future.

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Table 1-1 Variations of circuit performances by constant-field and constant voltage scaling method. [5] Parameter Constant-Field Scaling Constant-Voltage Scaling Dimensions 1/k 1/k VDD 1/k 1 Field 1 k Vt 1/k 1 Current 1/k 1 Capacitance 1/k 1/k Delay Time 1/k 1/k2 Power/Circuit 1/k2 k Power/Area 1 1/k3 Line Resistance k k RC 1 1 IR/VDD k k2

Table 1-2 ITRS roadmap 2008 Edition. [6]

Year of production 2009 2010 2011 2012 2013 DRAM 1/2 pitch (nm) 52 45 40 36 32

Drain extension Xj for bulk

MPU/ASIC (nm)

11 11 11 10 9

Max. parasitic series resistance for bulk NMOS (Ω/□)

200 200 200 200 180

Max. drain extension sheet resistance for bulk MPU/ASIC (NMOS) (Ω/□)

660 680 750 810 900

Contact Xj (nm) for bulk

MPU/ASIC 29 26.7 24.7 22 19.8

Allowable junction leakage for bulk MPU/ASIC (µA/µm)

0.25 0.48 0.71 0.7 0.64

Sidewall spacer thickness for bulk MPU/ASIC (nm)

29 26.7 24.8 22 19.8

Max. silicon consumption for bulk

MPU/ASIC (nm) 14.5 13.4 12.4 11 9.9

Silicide thickness for bulk

MPU/ASIC (nm) 17.9 16.2 14.7 13 12

Contact silicide sheet resistance for bulk MPU/ASIC (Ω/□)

9.1 9.9 10.8 12.1 13.5

Contact Max. resistivity for bulk MPU/ASIC (Ω-cm2)

Table 1-3 Basic characteristics of common used metal silicides. [19] Silicide Resistivity (µΩ-cm) Stable on Si up to (℃℃) ℃℃ nm of Si consumed per nm of metal nm of resulting silicide per nm of metal Barrier height to n-Si(eV) Film stress (dyne/cm) PtSi 28-35 ~750 1.12 1.97 0.84 1×1010 TiSi2(C54) 13-16 ~900 2.27 2.51 0.58 1.5×1010 TiSi2(C49) 60-70 x 2.27 2.51 x x Co2Si ~70 x 0.91 1.47 x x CoSi 100-150 x 1.82 2.02 x x CoSi2 14-20 ~950 3.64 3.52 0.65 1.2×1010 NiSi 14-20 ~650 1.83 2.34 0.67 6×109 NiSi2 40-50 x 3.65 3.63 0.66 x WSi2 30-70 ~1000 2.53 2.58 0.67 x MoSi2 40-100 ~1000 2.56 2.59 0.64 x TaSi2 35-55 ~1000 2.21 2.41 0.59 x

W Voltage, V _Wiring

Original Device

Gate n+ n+ p substrate, Doping= NA Lg Xd tox W/k Voltage, V/k _Wiring

Scaled Device

Gate n+ n+ Doping= kNA Lg/k tox/k

40 50 60 70 80 90 100 110 0 20 40 60 80 100 120 140 29% 42.5% S er ie s R es is ta nc e Gate Length (nm) NMOSFET Rdp Rext Rov Rcsd 49%

(a)

40 50 60 70 80 90 100 110 0 20 40 60 80 100 120 140 160 180 200 21% 33% S er ie s R es is ta nc e Gate Length (nm) PMOSFET Rdp Rext Rov Rcsd 34.5%

(b)

Fig.1-2 Series resistance of (a) NMOS and (b) PMOS transistors with different gate lengths. [29]

Chapter 2

Improvement of Nickel Silicide Characteristics

with Germanium Ion Implantation

2-1 Introduction

The reactions of Ni and Si for possible use in microelectronic manufacturing have been studied starting in the early 1980s [1,2]. The electrical and mechanical properties of Ni-silicdes depend on the thickness of silicide film and the incorporation of various impurities. The main disadvantage of the nickel monosilicide (NiSi) is its poor thermal stability including thin film agglomeration and high-resistivity phase (NiSi2) transformation. Agglomeration starts with grain grooving in the silicide,

followed by grain separation and then forms silicide islands. Some models based on surface/interface energies, grain boundary grooving, and silicide grain size have been proposed to predict the onset of agglomeration on single crystal Si [3-6]. These models involve the following process: dissolution and transport of Si atoms in silicide, precipitation and epitaxial re-growth of Si, and deformation of silicide. Because the NiSi phase is not in equilibrium with Si at high temperature, the expected reaction of NiSi + Si
NiSi2 will occur. Similar to the thin film agglomeration, the phase

transformation is a nucleation-controlled reaction and depends on silicide thickness, dopant impurities, and annealing ramp rate because of changing activation energies for nucleation. Several methods have been proposed to improve the thermal stability of NiSi film on Si substrate; for example, fluorine ion implantation [7-8], nitrogen ion implantation [9-10], capping layers [11-12], palladium (Pd) incorporation [13], and

platinum (Pt) incorporation [14-17]. Among these methods, Pt incorporated Ni silicide produces the most promising results in terms of NiSi agglomeration and NiSi2 phase

transformation. One of the drawbacks of the Pt-incorporation method is the higher resistivity due to Pt doping. Recently, carbon incorporation has been reported to improve the thermal stability of NiSi [18-20], however, the solid-state solubility of C in Si is very low and improper thermal budget after carbon incorporation would produce a large amount of interstitial carbon and result in junction leakage. Since the line width and thickness of NiSi scale down continuously, new technique to improve its thermal stability is required.

In the 1980s, Ge ion implantation was reported as a substrate amorphization technique in order to eliminate dopant channeling effect for shallow junction formation [21-23]. Several investigations regarding to the effects of Ge pre-amorphization implantation (PAI) process on metal-silicide formation have been reported [24-27]. Most of these papers focused on the Ti-silicides and Co-silicides. The formation energy of Ti-silicides is substantially reduced by Ge PAI on Si substrate. Low-resistivity C54-TiSi2 film can be achieved with a lower thermal budget

and at 250nm narrows line width [28]. High dose Ge PAI can improve the thermal stability of TiSi2 while low dose (≤ 1 × 1015 cm-2) Ge PAI does not play any role [26].

On the other hand, the incorporation of Ge results in an increase in the nucleation temperature of CoSi2 from about 600 °C to about 800 °C which is too high for the

manufacturing of advanced devices [27]. The studies of the effects of Ge incorporation on Ni-silcides were reported recently [29-34]. Kittle et al. [29] found that the Ge PAI can increase the Ni2Si growth rate at 250 °C, and Yun et al. [31]

observed that Ge PAI to a dose of 1 × 1014 cm-2 results in a smooth NiSi/Si interface and suppresses oxidation on arsenic doped n+ Si. However, medium dose Ge PAI did not affect the thermal stability of NiSi. The retardation of phase transformation from

NiSi to NiSi2 was found on the SixGe1-x structure [32]. Although NiSi2 phase

transformation can be suppressed, the NiSi agglomeration and Ge out-diffusion on SixGe1-x substrate during Ni silicide formation are worse than those on Si substrate at

low temperature [33]. Kim et al. reported that a thin Si capping layer on Si0.81Ge0.19

substrate can improve the NiSi(Ge) agglomeration temperature due to the strain effect [34].

According to the above reports, Ge incorporation to a suitable concentration may benefit the thermal stability of NiSi films but the effect of Ge incorporation on the NiSi-contacted shallow junction has not been investigated. Moreover, Ge incorporation by high dose ion implantation has not been employed. In this chapter, a thorough study on the thermal stability improvement of the NiSi/Si (likes Source/Drain regions) and NiSi/poly-Si (likes Gate region) structure by Ge ion implantation has been carried out.

2-2 Samples Preparation and Experimental Procedures

2-2-1 Ni-Silicides on Bulk-Si Substrate

The starting materials were boron-doped 6-inch (100) Si wafers with resistivity of 15~25 Ω-cm. Wafers are divided into two categories: GIBS and GIAS.

1. GIBS (Ge Implantation Before Silicidation) sample preparation: After initial clean, a 20 nm thick screen oxide was thermally grown on blanket wafers. Some of the blanket samples were implanted by Ge ions at 20 keV or 50 keV to a dose of 5 × 1015 cm-2 or 1 × 1016 cm-2. The projected ranges (Rp) of Ge implantation at 20 keV

and 50 keV are about 5 nm and 25 nm below the Si surface as simulated by the Monte Carlo method, respectively. For the 20 keV samples, the Ge implanted layer would be