2-2-1 Fabrication of MSB TFTs
Fig.2-1 shows the schematic process flow of the MSB TFT. In order to simulate the glass substrate, a 1um thick oxide was deposited on 6-in wafer first. Then, a 50 nm thick a-Si layer was deposited as device active layer in a low pressure chemical vapor deposition (LPCVD) system at 550℃ using SiH4 as Si source. The active layer was crystallized by solid phase crystallization (SPC) process at 600℃ for 24 hours in N2 ambient. After patterning the active layer, a 50 nm thick TEOS oxide layer was deposited in a LPCVD system at 700℃ as gate oxide. A 100 nm thick a-Si layer was
subsequently deposited in another LPCVD system at 550℃ using SiH4 as Si source as gate electrode. Then, the a-Si gate electrode layer and the gate oxide layer were etched in a poly-Si etcher of model TCP-9400 and an oxide etcher of model TEL-5000, respectively. To form a sidewall spacer to avoid the bridging effect between gate and S/D in the following NiSi silicidation process, a 100 nm thick TEOS oxide was deposited in a LPCVD system at 700℃ followed by dry etching process. A 22nm-thick Ni film was then deposited in a sputtering system immediately after a diluted-HF dip for 40 sec. The spacer length was reduced to about 50-60 nm after the diluted-HF dip process. The Si layer at S/D region was converted to NiSi completely by a rapid-thermal annealing at 500℃ for 40 seconds in N2 ambient.
After the silicidation process, the un-reacted Ni was selectively removed by H2SO4/H2O2 solution for 10 minutes at 100~120 ℃ . Fig.2-2 shows the Id-Vg characteristic of a device with 5 um channel length and 5um channel width measured at this stage. The am-bipolar characteristic indicates that a typical Schottky barrier (SB) device has been fabricated successfully.
Implant-to-silicide (ITS) process was employed to form MSB junction. BF2+ ions were implanted at 45 KeV for p-channel MSB TFTs (MSB pTFTs) and P+ ions were implanted at 30KeV for n-channel MSB TFTs (MSB nTFTs). Two dosages of 1x1015 and 5x1015 cm-2 were used to study the effect of implantation dose. Dopants were then diffused out of silicide to form an ultra-shallow SDE at the channel-S/D interface by a low temperature annealing process in N2 ambient. This process was performed in a RTA system at temperatures of 600, 650, 700 and 750℃ for 30, 90, and 150 sec. Table 2-1 summarizes the process conditions studied in this thesis.
In order to simply the fabrication process, source, drain, and gate electrodes were defined large enough so that devices can be measured directly without additional metallization process. The typical layout of devices is shown in Fig.2-3.
2-2-2 Fabrication of Conventional TFTs
Besides the fabrication of MSB TFTs and SB TFTs, conventional (CN) TFTs were also fabricated for comparison purpose. The process steps for CN TFTs were identical to those for MSB and SB TFTs until spacer formation. S/D and gate were doped by BF2+
ion implantation at 25KeV to a dose of 5x1015 cm-2 for pTFTs and P+ ion implantation at 18 KeV to a dose of 5x1015 cm-2 for nTFTs. In order to activate dopants, a 300 nm thick TEOS oxide was deposited in a plasma enhanced chemical vapor deposition (PECVD) system at 300℃ followed by a furnace annealing for 12 hours at 600℃ in N2 ambient for CN pTFTs and by a RTA annealing for 20 seconds at 700 ℃ in N2 ambient for CN nTFTs. Finally, typical contact opening and metallization processes were performed to complete the device fabrication. A 30 minutes alloy process was carried out at 400℃ for reducing the contact resistance.
2-2-3 Structural Analysis of MSB TFTs
Fig.2-4 shows the cross-sectional transmission electron microscopy (TEM) micrographs of a MSB nTFT with gate length (Lg) of 5um, gate width (Wg) of 5um, and channel thickness (Tch) of 50nm. The oxide sidewall spacer is indicated by white dashed line. It is clear that the S/D region was fully silicided and a 50 nm thick NiSi was formed on a-Si gate. The slight sunken of S/D near gate edge is due to the micro-trenching effect during the plasma etch of gate oxide. Fig.2-5(a) and (b) show the energy dispersive X-ray (EDX) spectra of region A and region B as indicated in Fig.2-4, respectively. Region B is Ni-silicide and region A is still poly-Si. It is confirmed by the EDX spectra that the lateral growth of Ni-silicide is limited and the S/D silicide does not overlap with gate electrode. The phase of silicide at S/D region and gate region were identified to be NiSi2 and NiSi, respectively, by electron diffraction pattern as shown in Fig.2-6. This result is identical with that observed in MSB FinFET [27] and the mechanism is still under investigation.
The silicide layer on a-Si gate is about 45 nm, leaving unreacted a-Si of about 74 nm thick. Fig.2-7 shows the secondary ion mass spectroscopy (SIMS) depth profile of boron at gate region. The implantation dose is 5x1015 cm-2 and the activation condition is RTA at 600℃ for 30 sec in N2 ambient. It is observed that most of the boron atoms were confined in Ni-silicide and only a very shallow p-type layer formed at the Ni-silicide/a-Si interface. It is expected that the ultra-shallow SDE at S/D region should be similar. It should be noted that since the a-Si gate was not doped before silicidation, gate depletion becomes unavoidable and device performance will be suffered. All of the device performance of MSB TFTs presented in the next chapter could be improved if the a-Si gate electrode were heavily doped in advance.
Table 2-1 Experimental split condition of MSB TFTs
Activation Temperature
Temperature 600℃、650℃、700℃、750℃
Time 30sec Dosage 5x1015 cm-2 System RTA
Activation Time Temperature 600℃
Time 30sec、90sec、150sec Dosage 5x1015 cm-2
System RTA
Implant Dosage Temperature 600℃
Time 30 sec
Dosage 1x1015 cm-2、5x1015 cm-2 System RTA