The constant drain current method is used to determinate the threshold voltage. The threshold voltage (Vth) is defined as the gate voltage required to achieve a normalized drain current as 10nA at Vds= 0.1 V
@ 10
th gs ds
V V I W nA
= = L × ………..(2-1)
where the W and L are the channel width and length, respectively. It should be noted that the channel width of FEN POST SONOS is defined as 0.6n μm (W = n strips × 2 wires/strip × 300 nm/wire = 0.6n μm), where the n is the number of dummy strip. The surrounding width of each nanowire channel is 300 nm as shown in Fig. 2-6. The subthreshold swing (SS) is determined from the subthreshold region of Ids-Vgs curve at Vds= 0.1 V. POST SONOS. It is obvious that (as shown in Table 2-1) the FEN POST SONOS with GAA structure device has superior performance than CP device with higher on current, smaller Vth and steeper subthreshold swing (SS), higher on/off ratio, and higher mobility, which are contributed to the enhanced gate control ability by the three sharp corners and GAA structure together with the reduced number of grain-boundary defect in the nanowire channel [48]. For memory operations, in this work, the TFT SONOS memory is programmed and erased by Fowler-Nordheim (FN) tunneling mechanism. Figure 2-8(a) and 2-8(b) show the transfer characteristics of the CP and the proposed FEN POST SONOS devices after DC stress at Vgs= 7 V condition. The results, clearly, indicate the transfer characteristics are the same even
the stress time is 1000 sec. Thus, the read disturb can be neglected under the normal transistor operation. Figure 2-9 and 2-10 show the transfer characteristics of the CP and FEN POST SONOS devices with various programming times at a gate voltage 15 V, respectively. For erasing operations, the transfer characteristics of the CP and FEN POST SONOS devices with various erasing times at gate voltage -15 V are shown in Figs. 2-11 and 2-12, respectively. It is obviously found that the program/erase (P/E) efficiency of the FEN POST SONOS device is significantly better than the CP one. In the programming characteristics, the FEN POST SONOS exhibit a large Vth shift of 2.71 V in 1 ms at a gate pulse of +15 V, while there is only 0.49 V shift in CP device.
The erase characteristics also show that the FEN POST SONOS devices are much faster (a Vth shift of 2.11 V in 1 ms at a gate pulse of -15 V) than the CP counterparts.
The improvement on P/E speed and window can be attributed to the field enhancement from the three sharp corners to promote carrier injection through the tunneling oxide into the nitride storage layer. The Vth shifts after programming and erasing operation for the CP and FEN POST SONOS devices with various voltage are plotted in Figs. 2-13(a) and 2-13(b).
For further clarifying this P/E efficiency enhancement, the simulations of electrical fields for the CP and FEN POST SONOS structures were performed by ISE-TCAD simulator. The distribution of electrical field and band diagrams across the stacked ONO dielectrics was numerically simulated at a gate bias of 15 V for the CP and FEN POST SONOS devices as shown in Fig. 2-14 and 2-15, respectively. The sharp geometry of these three corners enhances the electric field at the Si/tunneling oxide interface and depresses the electric field in the blocking oxide. The large field at the Si/tunneling oxide interface enhances the carrier-injection probability and thus increases both the P/E speeds of FEN POST SONOS device. In addition, the reduction of the electric field in the blocking oxide prevents charges tunneling from
the nitride to the poly-gate and from the poly-gate to the nitride. The P/E activity is thus facilitated between the channel and tunneling oxide rather than between the blocking oxide and the gate. In contrast, for CP SONOS structures, as shown in Fig.
2-14, the electric field in the tunneling oxide is equal to that in the blocking oxide, leading to lower P/E efficiency. In addition, Figure 2-15 exhibits the FEN POST SONOS device has shorter tunneling distance than the CP SONOS device. Figure 2-16 shows the retention characteristic of FEN POST SONOS device, where the memory window is maintained with negligible degradation up to the tested time of 104 sec. It shows the memory window will be larger than 1.1 V after extrapolating to retention time of 10 years. The endurance characteristic of FEN POST SONOS device is shown in Fig. 2-17, the memory window was kept 1.68V and rises about 1 V after 104 P/E cycles. The rising of memory window results from both the charges in Si3N4
deep level traps are hard to be erased and the subthreshold swing is degradation due to the tunneling oxide is damaged during P/E cycles.
2-5. Summary
In summary, we have demonstrated the FEN POST SONOS devices, the FEN POST SONOS devices have superior performance than CP devices with higher on current, smaller Vth, steeper subthreshold swing (SS), higher on/off ratio, and higher mobility which are contributed to the enhanced gate control ability by the three sharp corners and GAA structure together with the reduced number of grain-boundary defect in the nanowire channel. In addition, the proposed FEN POST SONOS exhibits higher P/E speed than CP SONOS due to larger electric field in the tunneling layer
and lower electric field in the blocking oxide. The proposed FEN POST SONOS also exhibits stable endurance/retention characteristics. And, the process simplicity and good device performance is very promising for future SOP and 3-D ICs applications.