2-1. Introduction
In recent years, poly-Si thin film transistors (TFTs) have been widely used as pixel switching elements in active-matrix displays. For further achieving system-on-panel (SOP) applications, other functional elements based on poly-Si TFT technology, such as memories, sensors, drivers, and controllers, are also required to fully integrate on the same display panel [35-39]. It is well-known that the nonvolatile memory (NVM) is a critical element for data storage, signal processing, and power saving in portable electronic systems [40]. Silicon–oxide–nitride–oxide–silicon (SONOS) flash memory has been investigated to realize vertical scaling of flash memory. The faster programming speed and lower operating voltage of SONOS devices were accomplished in the past by reducing the tunnel-oxide thickness [41-44].
However, this seriously degrades the retention capability of the memory devices.
Several efforts have been made to improve the retention time of SONOS devices.And, due to the process is compatible with poly-Si TFT, silicon–oxide–nitride–oxide–silicon (SONOS)-type devices, instead of traditional floating-gate ones, have been considered as a promising nonvolatile memory candidate for future System on Panel (SOP) applications [45-47].
2-2. Fabrication Sequences of FEN POST SONOS Memory with a Gate-All-Around Structure
The fabrication steps of field-enhanced-nanowire poly-Si TFT SONOS (FEN POST SONOS) with gate-all-around (GAA) structure devices are schematically shown in Fig. 2-1. At first, a 50-nm-thick Si3N4 (as etch-stop layer) and a 300-nm-thick tetra-ethyl-ortho-silicate (TEOS) SiO2 (as sacrificial layer) films were sequentially deposited on oxidized silicon wafer by low pressure chemical vapor deposition (LPCVD) system at 580 °C and 700 °C, respectively. Several strips with step height of 100-nm as shown in Figs. 2-1(a) and 2-1(b) were patterned on surface of the sacrificial SiO2 layer by reactive ion etch (RIE), and followed by a conformal deposition of 100-nm-thick a-Si layer by LPCVD at 550 ℃. After source/drain (S/D)-pad lithography and its RIE process, couples of spacer nanowires were in-situ resided against the sidewall of those designed strips and naturally connected to the S/D pads as shown in Figs. 2-1(c) and 2-1(d), which were formed to be the device active region. It should be noted that each spacer nanowire inherently features three sharp corners, and the nano-scale dimension of the nanowire channels can be defined only by controlling the RIE time without any advanced lithography [48-50], each dummy strip produces twin nanowire channels, as well as the multiple channels can be designed with patterning several dummy strips (n strips x 2 wires/strip = 2n wires).
Subsequently, a solid phase crystallization (SPC) at 600 °C in N2 ambient for 24 hours was performed to transform the a-Si into poly-Si. After that, the suspending channels were formed by etching the sacrificial SiO2 layer with 3:50 diluted HF, and the etching-stopper layer would stop etching process down to the buried oxide as shown in Figs. 2-1(e) and 2-1(f) in the tilted and cross-section views, respectively. Then,
a 5-nm-thick tunneling oxide, a 10-nm-thick nitride trap layer, a 10-nm-thick blocking oxide, and a 200-nm-thick phosphorous in-situ doped poly-Si were sequentially deposited conformally to wrap around those suspending spacer nanowires by LPCVD systems. The poly gate was defined as shown in Figs. 2-1(g) and 2-1(h) in the tilted and cross-section views, respectively, and a phosphorous ion implantation was performed with a dosage of 5×1015cm-2and a energy of 30 keV. Then, a 300-nm-thick passivation oxide deposition and S/D activation were sequentially performed. The contact holes were patterned to etch the passivation layer by RIE and the Al metal layer was deposited by sputter system. Finally, the Al metal layer were patterned and etched by RIE to complete the fabrication. For the purpose of comparison, the conventional planar TFT SONOS (CP SONOS) with single top-gate structure were also fabricated at the same process run.
2-3. Materials Analysis of FEN POST SONOS Memory with a Gate-All-Around Structure
The previous section briefly describes the process sequence of the FEN POST SONOS. In this section, the scanning electron microscope (SEM) and transmission electron microscope (TEM) have been used to analyze the detailed process parameter in the fabrication of FEN POST SONOS.
Figures 2-2(a) and 2-2(b) show the SEM images before and after sacrificial oxide stripping by HF acid, respectively. And, Figs. 2-2(c) and 2-2(d) show their corresponding schematic images. It can be shown that the sacrificial SiO2layer has been removed and there are two suspending nanowires remained after oxide stripping.
Figures 2-3(a) and 2-3(b) show the tiled-view SEM image and the corresponding schematic image of the multiple suspending nanowire channels after HF etching.
Different channel width can be easily designed by adjusting the number of sacrificial SiO2 strips. The cross-section view SEM image and the corresponding schematic image of the suspending channels are shown in Figs. 2-4(a) and 2-4(b), respectively.
The multiple nanowire channels are hung in the air with a height 200 nm above the Si3N4 etch-stop layer and connected to the source and drain pads.With the aid of the suspending nanowire channels, the ONO dielectric layers and poly gate deposited by LPCVD can be easily surrounding the channel to form the GAA structure. Figures 2-5(a) and 2-5(b) show the top view SEM image and the corresponding schematic image after patterning gate, respectively. It should be noted that there are residual bottom gates remained below the source/drain extensions after gate patterning. The source/drain extensions shield (prevent) the residual bottom gates from the anisotropic RIE. Figure 2-6 exhibits the cross-section TEM image of each gate-all-around nanowire and shows the ONO dielectrics and poly gate which were conformally deposited on the three sharp corners. The polycrystalline nanowire channel in the center of graph is formed by the TCP-RIE and the dimension of nanowire is precisely controlled by etching time. The TEM image shows that the vertical sidewall thickness, the horizontal width and bevel length of each NW channel are about 85 nm, 85 nm and 130 nm, respectively. Thus the total surrounding width of each NW channel is 300 nm.