In addition to the short gate length, a small gate resistance is essential for HEMTs for high gain, low noise, and high power applications. A short gate length is also important for high frequency and high speed HEMT devices. In general, one conventional approach for achieving low gate resistance is the use of a T-shaped or mushroom-shaped gate. In the T-shape structure, the small footprint defines the length and the wide top provides a low resistance. T-shape gates have been fabricated using Deep UV lithography or using multilayer resist technique with e-beam lithography.
Figure 2-17 illustrates the process flow of using Deep-UV lithography. The SEM image of a 0.5μm T-shaped gate is shown in Figure 2-18. The process flow of forming 0.15μm T-gate bi-layer PMMA/PMMA-MAA photo-resist and the SEM image of lifted-off metal gate are shown in Figure 2-19 and 2-20, respectively.
The selective wet chemical gate recess etching has been widely used to achieve good current and threshold voltage uniformity for the HEMTs. From the previously reports, many efforts have been made to achieve a high selective etch between GaAs/AlGaAs. The etch Selectivity by using different solutions with various x values of the GaAs/AlxGa1-xAs structures are summarized in Table 2-2. In citric acid system, the selectivity of 2700, 159, 143, 137 for GaAs over AlxGa1-xAs with x=1, x=0.3, x=0.23, x=0.2, respectively, using the 1.5:1 solution of citric acid/H2O2 at 23℃.
The wet etching mechanisms generally include both diffusion limited and reaction rate limited process. Wet chemical etching proceeds through chemical reactions that occurred at the surface of the material. The etchant must reach the surface in order that appropriate reactions could occur and the reaction products should be removed from the surface. If the etching is reaction rate limited, then the material dissolution is a function of the chemical reaction rate between the etchant and the semiconductor.
For the reaction rate limited mechanism, etching rate is linearly proportional to the etching time, and is unaffected by stirring or agitation of the liquid etchant. If it is diffusion limited etching, the material dissolution depends on the transport of the active etching components to the material surface and on the removal of the reaction products away from the surface. Therefore, etching rate is proportional to the square root of the etching time, and increases with the agitation of the liquid etchants.
In generally, the etchants will contain oxidizer and the dissolving agent. The hydrogen peroxide is usually used as the oxidizing agent. The citric acid based solution is the dissolving agents in the selective etching solution. Most etchants for GaAs operate by oxidizing the surface first and then dissolve the oxides, thereby removing the reacted oxides. As a results, the lower etch rate was observed for AlxGa1-xAs with increasing x due to the formation of AlxOy which is difficult to remove by the citric acid.
After the gate lithography and resist development, the exposed HEMT channel area
is recessed to achieve the desired channel current and threshold voltage. In addition, the donor layer of the HEMT is very thin and heavily doped, therefore, the HEMT gate recess is more difficult to control than that of GaAs MESFET. The depth to which the gate is recessed is a critical parameter in FET performance. The method used to control the etch depth is to monitor the source-to-drain current during the etching process. The saturated current is reduced as the slot is etched into slice as shown in Figure 2-21 and the test key of current monitor as shown in Figure 2-22.
The slot is etched until the target recess current is reached. This requires alternate steps of etching and current measurement, so it is not possible to monitor current while wet etching is proceeding. The concentration of the etchant should be adjusted to provide an etch rate that is sufficiently slow to allow good control over recess process, and reach the target current value without overshooting. Placing the metallization on the GaAs creates a zero-bias depletion zone in the GaAs and results in a saturated drain current drop after metallization. Therefore, the recess etching process must use a target current than that of the desired device current.
Pseudomorphic HEMTs have demonstrated exceptional power performance at millimeter frequency. The limiting factor of power performance has been the relatively low gate-drain breakdown voltage. The use of an undoped cap has been suggested to alleviate this limitation. However, this can increase both the source and
drain parasitic resistances leading to degraded microwave performance. A common technique used to improve the breakdown voltage while maintaining low source resistance is to use a doped cap and offset the gate toward the source side of a wide recess trench. This process requires two lithography steps, one to define the large area where the doped cap is to be removed, and the other to define the much narrower region for gate recess and metallization, as illustrated in Figure 2-23.
After gate recess process, the wafer was cleaned in the solution of HCL: H2O = 1:10 solution to remove the native oxide and the gate metal Ti/Pt/Au was deposited by e-beam evaporator [1].