The choice of the VCO architecture is based on the consideration of linearity, jitter performance, power and some implementation issue. We give the summary of the performance of the VCOs in TT-25℃ in Table 3-1. In Table 3-1, it shows the poor linearity of the current-starved VCO due to the second order relationship between Vctrl and frequency. The linearity of the supply controlled VCO is great, but this type of VCO is only suitable for the high voltage level of the control voltage. For our application the input is in the low voltage level so the additional bias circuit is required for this architecture which costs the additional power consumption. For the bulk-control VCO the linearity is good but the offset frequency is large that causes too large power consumption. For the ground controlled ring VCO, it has good linearity and good jitter performance. Its offset frequency is low, so the power consumption is
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less than other architectures. And the voltage range is also suitable for our application.
So, with these reasons, we choose the ground controlled ring VCO for our design.
Architecture linearity Jitter (max) Frequency
(MHz)
Table 3-1 Performance comparison of VCO
3-3 Counter
Counter which is triggered by the transition edge of VCO output is the component that converts the time information into the digital value. The requirement of counter should cover the oscillation number which VCO operates at the maximum frequency in whole sampling period as equation(3.14).
vco 2
s
max(F ) Bit number of Counter log ( )
F (3.14)
According to the spec in Table 1-1, the sampling frequency of ADC is 10k Hz.
We can calculate the bit requirement for the counter should be more than 17 bits. For this large bit number requirement, the dynamic power of counter may be one of the issues. In the following section, we compare both of the synchronous and asynchronous counters and choose the suitable one for our ADC.
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3-3.1 Synchronous
Synchronous counter is composed of an adder and the flip-flop. The adder calculates next the counter value during each VCO oscillation cycle. And flip flops pass the result of adder to the counter output at once as shown in Fig.3-38. In this architecture, the counter CLK is the output of VCO. The synchronous counter all the flip-flops are triggered by the CLK. The high operating frequency of counter causes the power consumption of counter is quite large. For the 17 bits counter, operating in 65MHz its power is about 4.5uW dominating the overall power consumption of Fig.3-38 synchronous counter: (a) Architecture; (b) Timing diagram
3-3.2 Asynchronous
needed in this type of counter, so the power of combination circuit is zero. But, due to the carry-in information is propagated by each stage flip-flops, the timing criteria of55
counter is depended on the propagation delay from D to Q of flip-flops. Here, we choose the high performance flip-flop in standard cell to ensure the counter operation.
F/F
Fig.3-39 Asynchronous counter: (a) Architecture; (b) Timing diagram
But still, in the timing diagram shown in Fig.3-39(b), we can see that the carry-in propagation delay is quite large. There might have large probability of flip-flops sample the intermediate value of counting. For avoiding the sampling flip-flops sampled the wrong value during propagation, we add the other set of flip-flops which triggered by the delayed CLK to double sample the counter value. The delays for CLKs triggered these two sets flip-flops should cover the region of carry in propagation. Due to the working principle of asynchronous counter, the propagating is starting from the LSB, we can determine the correct value from flip-flops. During the propagation, LSBs will first turn to 0 before the MSB turns to 1, the value of counter will first decrease before carrying in. So, if the value triggered from the delayed CLK is smaller than the value of regular CLK, we can judge that the counter is during propagation at the delayed CLK the proper value is chosen as the regular CLK.
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In Fig.3-40, we denote FF_SP as flip-flops triggered by the regular sampling CLK, FF_SP_D as flip-flops triggered by the CLK with delay. There are 3 different sampling situations:
A. FF_SP samples the value before propagation and FF_SP_D samples the value after propagation.
B. FF_SP samples the value before propagation and FF_SP_D samples the value during propagation.
C. FF_SP samples the value during propagation and FF_SP_D samples the value after propagation.
Due to the delay for sampling CLK is designed to be larger than the carry-in propagation, the case that both FF_SP and FF_SP_D sample the value during propagation will not happen. The value during propagation is always smaller than the value is settled, no matter before or after propagation for case B and C. For case A, both two values are settled, so the correct value is depended on which sampling CLK we want. Here, we choose the value of original sampling clk. So, we choose FF_SP for case A. and value of case B is modified by FF_SP_D-1.
Algorithm 1: Asynchronous F/Fs determination Input: FF_SP and FF_SP_D
Output: OUT
ifFF_SP_D< FF_SPthen OUT = FF_SP else
OUT = FF_SP_D-1 End
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A B C
CNTR_CLK OUT[0]
OUT[1]
OUT[2]
Sampling CLK Delayed Sampling CLK
FF_SP 3
4 FF_SP_D