The details of process are illustrated in Fig.3-2:
1. Laser marking of 6-inch Si wafer
The 6-inch n-type silicon wafers were commercially obtained from Wafer Works Corp. Then laser marker of model NEC SL473D2 was used to mark the wafers for label. To remove the particles produced by laser marking, a standard clean 1 (SC-1) which is the cleaning process of soaking wafers into the solution containing NH4OH :
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H2O2 : H2O = 1 : 4 : 20 for 600 seconds at 75 °C was performed after laser marking.
2. Pre-furnace standard (STD) clean and dry oxide 10 nm
Before the dry oxidation, the STD clean was performed. The STD clean contains SC-1 and SC-2. A DI water rinse was performed before and after each clean step.
SC-2 is the cleaning process of soaking wafers into the solution containing HCl : H2O2 : H2O = 1 : 1 : 6 for 600 seconds at 75 °C. After the STD clean, the dry oxidation to grow a 10-nm-thick SiO2 pad layer was performed at 925 °C by a horizontal furnace system.
3. Pre-furnace STD clean and LPCVD Nitride 80 nm
If this deposition process was subsequent to previous process, the STD clean could be skipped. Otherwise, after the pre-furnace STD clean, a 80-nm-thick LPCVD nitride layer as a masking layer for STI process was formed by a horizontal furnace system.
4. Trench patterning
The lithography process was performed by TEL CLEAN TRACK MK-8 for photo resist (PR) coating and development and the Canon FPA-3000i5+ stepper for exposure. After the lithography process, the 300 nm trench was patterned by TCP 9400SE etcher. The Mattson AspenII Asher was used to remove the PR residue by O2
plasma when patterning process was completed. It is noticed that dummy patterns were inserted at this step to prevent the dishing problem from the later chemical mechanical polishing (CMP) process.
5. Pre-furnace standard (STD) clean and dry oxide 10 nm
After the pre-furnace STD clean, a 10-nm-thick SiO2 liner layer was grown at 925 °C by a horizontal furnace system to reduce surface damage and interface charges resulting from the trench etching.
6. Pre-furnace STD clean and LPCVD TEOS oxide 600 nm for trench filling
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After the pre-furnace STD clean, a 600-nm-thick LPCVD TEOS oxide layer was formed by a horizontal furnace system for trench filling in STI process.
7. Horizontal furnace annealing for LPCVD TEOS oxide layer
After LPCVD TEOS oxide deposition, a 900 °C, 30 minutes, N2 annealing was performed to densify the TEOS oxide layer for the purpose of bearing the damage during the CMP process.
8. CMP planarization
It is anticipated that after CMP planarization the top of TEOS would be slightly higher than that of the nitride on the active region, illustrated in Fig.3-3, in order to prevent excess consumption of TEOS oxide during latter steps. The CMP process was performed by Westech model 372M with PS-2515 diluted with DI water in equal proportion as the polishing slurry. The polish pad is IC1000-A2. The process parameters consist of carrier pressure of 4 psi, plate pressure of 1 psi, carrier speed of 42 rpm, plate speed of 40 rpm, and slurry flow rate of 180 mL/min, and the final polishing rate is about 110 nm/min. Fig.3-3(a) shows the cross-sectional SEM image near the edge of active region after the CMP planarization, and Fig.3-3(b) shows the OM image of the top view.
9. Post-STI process
To remove oxynitride on the silicon nitride, the wafers were dipped in diluted HF consisting of HF : DI water = 1 : 50 for 30 seconds at first. Next, the nitride layer was removed by soaking in a 200 ppm solution of Dihydrogen hexafluorosilicate (H2SiF6) diluted in Phosphoric acid (H3PO4) at 150 °C, which achieves a better etching rate selectivity between nitride and TEOS oxide. Then, a diluted HF dipping was performed to remove pad oxide, and finally the STI process was accomplished.
10. Pre-furnace standard (STD) clean and dry oxide 10 nm
After the pre-furnace STD clean, a 10-nm-thick sacrificial SiO2 layer was grown
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at 925 °C by a horizontal furnace system to consume the damaged surface layer of silicon to reduce defects and interface charges resulting from the CMP process. Also, for the later implantation and dopant activation process, this oxide layer acts as a capping layer to keep dopant from out-diffusion.
11. BF2 implantation and dopant activation After implanted by BF2+
at 15 keV to a dose of 5 × 1015 cm-2, wafers were performed a 1000 °C, 5 seconds rapid thermal annealing (RTA) by KORONA RTP 800.
12. PECVD TEOS oxide 40 nm
A 40-nm-thick PECVD TEOS oxide layer was deposited by Oxford 100 PECVD system to avoid breakdown due to leakage path from probing pad to substrate when device is measured.
13. Contact hole patterning
The lithography process was performed by TEL CLEAN TRACK MK-8 for photo resist (PR) coating and development, and the Canon FPA-3000i5+ stepper for exposure. After the lithography process, a total 50-nm-thick oxide was patterned by soaking in diluted buffered oxide etchant (BOE, NH4F : HF = 6 : 1) solution containing BOE : DI water = 1 : 100 in volume.
14. NiSi silicidation
After ICP clean by Ar plasma at a flow rate of 200 sccm for 50 seconds, a Ni(15 nm)/TiN(15 nm) stack was sputtered by the FSE cluster PVD system. Then, the residual photoresist and metal were lifted-off by sonicating in acetone for 1 minute.
After that, a 500 °C, 30 seconds RTA was performed in N2 ambient to form nickel silicide. The unreacted Ni and the TiN were selectively removed by SPM solution containing H2SO4 : H2O2 = 3 : 1 for 10 minutes at 75 °C. The OM image of the top view of the mTLM structure after silicidation is shown in Fig.3-3(c).
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15. Al pad patterning
The lithography process was performed by a mask contact aligner of model Karl-Suss MJB-3. After the lithography process, a 150-nm-thick Al layer was deposited by a thermal evaporation coater of model ULVAC EBX-6D. The lift-off process was performed, and finally the device fabrication was finished by a 400 °C, 30 minutes N2 annealing. Fig.3-3(d) shows the OM image of the top view of the final mTLM structure, and Fig.3-3(e) shows that of the final CBKR structure.