7-2-1 Metal / Insulator / Silicon (MIS-C) Sample Preparation
MIS capacitors were fabricated on p-type (100)-oriented silicon wafers with 8~10 Ω -cm nominal resistivity. After standard RCA clean process, three surface treatment methods were performed prior to film deposition. They are dilute HF-dip (HF-treatment), NH3-annealing (NH3-treatment) and rapid thermal oxidation (RTO-treatment). The HF-treatment is to immerse wafers into a 100:1 diluted HF solution after RCA clean and then spin dry without rinse in DI water. NH3-treatment is to anneal wafers in pure NH3 ambient at 800℃ for 60 minutes in a LPCVD system after RCA clean. Ellipsometry measurement indicates that a 1 nm thick silicon nitride layer is grown during this treatment. After NH3-treatment, some wafers were annealed in N2O ambient at 600℃ or 800℃ for 30sec prior to film deposition to improve the interface property between the nitride layer and silicon.
The RTO-treatment is to grow a thin oxide layer on Si surface in a rapid thermal oxidation system at 800℃ for 30sec in pure O2 ambient and then anneal in nitrogen ambient at 1000℃
for 30sec in the same chamber.
After surface treatment, wafers were put immediately into a MOCVD system for HfO2
deposition. Three different deposition temperatures, 345℃, 400℃ and 500℃, were used to study the temperature effects. The reaction gases are O2 and N2O with various flow rates. The thickness of HfO2 was set to 6 nm in most cases, which is controlled by the pulse number. The deposition rate was extracted by depositing thick HfO2 film and measuring thickness with n&k analyzer. Because the system is designed for 200 mm wafers, a quarts carrier is adapted so that our 150mm wafers can be handled. Just prior to deposition, wafers were heated in O2 ambient for 10min at the deposition temperature for thermal equilibrium and to replace the surface hydrogen termination with oxygen. The monolayer is expected to reduce the interface state density, which affects the electrical property significantly.
nitrogen or oxygen ambient. The deposition and annealing conditions are summarized in Table 7-3.
Pt-gated and Al-gated capacitors were formed in an e-beam evaporating system through a shadow mask after PDA. Pt has stable and inert chemical properties, but its adhesion with oxide is poor. Al is the most common electrode and is easy preparation in simple thermal evaporator system. A recently reported alloy gate electrode, Ta-Pt, was also prepared for comparison. After gate electrode deposition, 500nm thick Al was deposited at wafer backside as electrode for all samples to make good conductive contact to measurement system. The process flow of this MIS structure is illustrated in Fig.7-5.
7-2-2 Poly-Si / Insulator / Silicon (MIS-C) Sample Preparation
Since poly-Si is still the commonly used gate electrode in standard CMOS process, the MIS capacitor with poly-Si gate was also fabricated. The side-benefit of poly-Si gate is the gate patterning can be performed with conventional photolithography and etching techniques.
The gate edge effect can be eliminated if suitable isolation technology is employed.
Typical LOCOS isolation structure was used for the poly-Si gate capacitor. After isolation process, HfO2 was deposited at 400℃ and 500℃ with various O2 and N2O gas flow ratio following different surface treatments. All of these samples were annealed in N2 ambient at 600℃ for 30sec after deposition. Un-doped Poly-Si of 200 nm thick was immediately deposited after the PDA process. Gate electrode patterns were defined by the conventional photolithography and the plasma etching techniques. The poly-Si gate was doped by ion-implantation of As+ ions at 20 keV to a does of 3x1015 cm-2 followed by an activation annealing in N2 RTA for 30sec at 900℃ or 1000℃. Finally, a 500 nm thick Al was deposited at wafer backside to make good conductive contact to measurement system.
7-2-3 Analysis Techniques
For electrical analysis, a precision impedance meter of model Agilent 4284 was used for C-V measurement and a semiconductor parameter analyzer of model Agilent 4156C was used for I-V measurement. High frequency C-V measurement was performed at 100 kHz, with a small ac signal of Vrms=30mV. In general, the bias voltage is swept from inversion mode to accumulation mode. In some case, forward and backward sweeps were performed to monitor
dielectric was calculated from the capacitance at accumulation mode and the calibrated gate area.
For material analysis, cross-sectional Transmission Electron Microscopy (TEM) inspection, atomic force microscopy (AFM), X-Ray Diffraction (XRD), transmission electron diffraction (TED), and X-ray photoelectron spectroscopy (XPS) were employed. Detailed analysis conditions and results will be discussed in the next chapter.
7-3 Electrical Results
Fig.7-6 is a schematic drawing indicating the relationship between measured effective oxide thickness and physical parameters. The effective oxide thickness (EOT) is defined as the physical thickness of gate dielectric divided by the ratio of dielectric constant of the dielectric material to the dielectric constant of SiO2 (3.9). The CETacc and CETinv is the capacitance equivalent thickness of gate dielectric calculated from the measured gate capacitance at accumulation mode and inversion mode, respectively. The CETacc consists of the EOT and the equivalent thickness of accumulation layer due to quantum effect (Tqm) [10].
The CETinv consists of the EOT, Tqm and the equivalent thickness of gate depletion layer (Tpd) [10].
7-3-1 Effect of Gate Electrode
Before studying the effect of deposition parameters on the HfO2 film properties, suitable gate electrode must be selected. It had been reported that metals show good adhesion to dielectric might form an interfacial layer between metal and dielectric [11]. It was also reported that an AlOx-like interfacial layer may form at the Al/HfO2 interface, while no interfacial layer was observed between Pt and HfO2 [11]. Fig.7-7 shows the C-V characteristics of Al gate MIS-C and Ta-Pt gate MIS-C, where Ta-Pt is a newly reported gate materials [12]. The dielectric was 14nm thick HfO2 deposited on HF-treated Si substrate followed by a N2 RTA at 600℃ for 30sec. The flatband voltage difference is attributed to the work function difference between Al (4.1eV) and Ta-Pt (4.6eV) [12]. The capacitance at accumulation mode of Ta-Pt gate MIS-C is higher than that of Al gate MIS-C. After
both samples. It is thus postulates that as reported previously, an interfacial layer forms at the Al/HfO2 interface.
It is known that the heat of formation of Al2O3 is 399 Kcal/mol, which is larger than that of HfO2, 271 Kcal/mol [11]. It is reasonable that the AlOx-like interfacial layer could form during Al evaporation. Due to the inert chemical property of Ta-Pt alloy, no interfacial layer would form between Ta-Pt and HfO2. It is suggested that metals with heat of formation of metal oxides higher than that of HfO2 is not likely to be used as gate electrode.
Fig7-8 shows the C-V characteristics of poly-Si gate and Pt-gate devices with 8 nm thick HfO2 films deposited on NH3-treated wafers followed by a 600℃ PDA in N2 ambient for 30 sec. The CET values of poly-Si gate devices are larger than that of the Pt gate devices. This can not be explained by the poly-gate depletion effect because the CET is measured at accumulation mode. The only reasonable explanation is that an additional low dielectric constant interfacial layer formed at the poly-Si/HfO2 interface during poly-Si deposition and dopant activation processes. The CET value increases with the increase of activation temperature supports the explanation.
Both Ta-Pt and Pt exhibit inert chemical properties and are suitable for studying HfO2 properties. The deposition of Ta-Pt is more complicate than that of Pt. So, Pt is employed in the remaining part of the thesis. It should be noted that the adhesion of Pt to HfO2 is poor so that it is difficult to form good gate contact. Besides, the lightly doped Si substrate adds additional series resistance to the device. As the leakage current of gate dielectric is not negligible, the measured capacitance using simple parallel circuit is lower than the actual capacitance due to the contribution of the series resistance [13-14]. In this thesis, 100 kHz was employed and no equivalent circuit correction was performed.
7-3-2 Effect of Gas Sequence
In the MOCVD system, precursor provides the hafnium atoms and O2 gas provides oxygen atoms. The effect of gas injection sequence is examined in this subsection. The case of Hf-precursor being injected at first is called Hf-first and the case of O2 being injected at first is called O2-first. Fig.7-9(a) and (b) show the C-V characteristics and current density at -1V, respectively, of samples with HfO2 deposited at 400℃ and 450℃. The O2 flow rate is 300sccm and the deposition pressure is 3mbar. No PDA was performed in this experiment.
initial stage of these two deposition schemes so that Hf may react with Si or Hf-rich thin film may be formed to lead to larger leakage current. Although the O2-first scheme results in larger CET, which accounts or thicker interfacial layer, this scheme is still recommended due to the much lower leakage current. The reduction of interfacial layer thickness is rendered to surface treatment.
7-3-3 Effect of Surface Treatment
In order to improve the interface properties between HfO2 and Si interface, some surface treatment methods were employed prior to HfO2 deposited. In this subsection, HF-treatment, NH3-treatment, and RTO-treatment were performed and compared. The C-V characteristics of MIS-C with different surface treatment are shown in Fig.7-10, where the HfO2 film was deposited at the condition of T=400℃, O2 flow rate=300sccm, and pressure=3 mbar. No PDA was performed. The C-V curves of NH3-treatment sample and RTO-treatment sample show less distortion than that of HF-treatment sample. This result indicates that the previous two treatments result in less interface states. From the shape of the distorted C-V curves, the interface states are attributed to donor-like interface states. Although the NH3-treatment sample has higher accumulation capacitance than the RTO-treatment samples, the NH3-treatment sample shows more sever hysteresis phenomenon than the RTO-treatment sample due to higher tensile stress between the SiNx and silicon substrate [15]. It should be note that the RTO-treatment sample shows negligible hysteresis phenomenon. The major drawback is low accumulation capacitance which compiles thicker interfacial layer.
Fig.7-11(a) and (b) show the current density versus PDA temperatures in N2 and O2 ambient, respectively. The RTO-treatment samples show the lowest leakage current and the HF-treatment samples show the highest leakage current among the three different surface treatment methods. It is postulated that the RTO-treatment forms a high quality interfacial layer, which results in low accumulation capacitance together with low leakage current. The HF-treatment samples should have similar interfacial layer thickness as the RTO-treatment samples because of the same accumulation capacitance. However, the poor quality of interfacial layer results in the highest leakage current among the three treatment methods.
In Fig.7-11(a), it is observed that the leakage current increases with the increase of PDA
greatly. Micro-structural analysis will be shown and discussed in the next chapter. The temperature beyond which the leakage current decreases with PDA in O2 ambient reduces to 700℃. This result implies that the interfacial layer growth in O2 ambient is much faster than that in N2 ambient.
Similar results can be observed on poly-Si gate devices. Fig.7-12 compares the leakage current of HfO2 deposited at 400℃ and 500℃ followed by a 600 ℃ PDA in N2 ambient. The O2 flow rate is 500sccm and the deposition pressure is 5mbar. The magnitude of leakage current is still in the sequence of RTO-treatment < NH3-treatment < HF-treatment. Another interesting phenomenon is that the leakage current of 500℃ deposited samples is lower than that of 400℃ deposited samples by a factor of 5 orders of magnitude. Furthermore, the effect of surface treatment becomes less pronounced as the HfO2 film is deposited at 500℃. The effect of deposition temperature will be investigated in the next subsection and the mechanism will be proposed in chapter 4.
Based on the results shown from Fig.7-10 to Fig.7-12, a tradeoff between interface quality and CET exists. One possible method to improve the interface quality of the NH3 treatment sample is adding a N2O annealing after NH3-treatment to convert the interfacial layer from nitride to oxy-nitride. Fig.7-13 shows the magnitude of hysteresis of NH3-treatment samples wafer with post treatment annealing (PTA) at 600℃ and 800℃ in N2O ambient for 30sec. The HfO2 film was deposited at 400℃ with O2/N2O gas flow ratio rate of 250sccm/250sccm and pressure of 5 mbar. It is observed that an 800℃ PTA reduces the hysteresis phenomenon effectively. For the samples without PTA, high temperature PDA can still reduce the hysteresis effectively. It is summarized that by converting the interfacial layer from nitride-liked layer to another type interfacial layer such as oxide-liked layer, the hysteresis phenomenon can be reduced. The high hysteresis of samples with 600℃ PTA and 750℃ PDA cannot be explained now. It might be due to some process errors.
Fig.7-14 shows the leakage current density and CET of the samples with PTA. Although PDA can improve hysteresis phenomenon and reduce leakage current, the cost is the increase of CET, which is unacceptable for nano-scaled CMOS devices. Better surface treatment method must be developed. Before that, NH3-treatment was employed in the following subsections to study the HfO2 film properties.
leakage current. In this subsection, the effect of deposition temperature and deposition ambient was investigated systematically. About 6 nm thick HfO2 film was deposited at temperatures of 345℃, 400℃, and 500℃ in pure O2 ambient (500sccm), O2/N2O mixed ambient (250/250sccm), and pure N2O ambient (500sccm) on NH3-treatment wafers. The deposition pressure was kept at 5 mbar.
Fig.7-15 shows the current density at -1V and CET versus deposition temperatures at different deposition ambient before PDA. The CET of HfO2 deposited at T=500℃ in pure N2O ambient is not shown in this figure because the leakage current is too large to measure correct C-V curve. The CET values of all deposition conditions are similar. However, the effect of deposition ambient on leakage current is significantly different with increasing deposition temperature, especially at high deposition temperature. In oxygen-contained deposition ambient, the leakage current decreases with the increase of deposition temperature, while in pure N2O ambient the trend is reversed. Although the CET values are similar, the leakage current of HfO2 film deposited in pure oxygen ambient is lower than that deposited in O2/N2O mixed ambient, especially at high deposition temperature. Adding N2O gas reduces the deposition rate at all temperatures. Pure N2O ambient has the lowest deposition rate but the highest leakage current.
Fig.7-16 and 7-17 show the current density and CET values, respectively, of HfO2 films deposited at different temperatures and ambient on NH3-treatment samples versus PDA temperatures. For HfO2 films deposited in pure O2 ambient (Fig.7-16(a)) at 345 and 400 ℃, the leakage current increase with the increase of PDA temperature at first and then decreases with the increase of PDA temperature. This trend is similar to that shown in Fig.7-12.
However, for HfO2 film deposited at 500 ℃, the leakage current decreases with the increase of PDA temperature monotonically. This is a quite different trend that has never been reported.
On the other hand, the CET values decrease slightly after 600 ℃ PDA and then increases with the increase of PDA temperature as shown in Fig.7-17(a). The mechanism of the change of CET values will be explored in the next chapter. What important to be highlighted here is that the CET values of HfO2 film deposited at different temperature are similar while the leakage current has orders of magnitude difference. Thus, another mechanism other than
films deposited in pure O2 ambient, especially for the 500 ℃ deposited films. The HfO2 film deposited in pure N2O ambient shows even higher leakage current in Fig.7-16(c). To summarize, higher deposition temperature and purer O2 ambient is benefit to the leakage current performance. The mechanism is not related to the interfacial layer thickness.
Fig.7-18 compares the electrical properties of HfO2 films deposited at 500℃ with O2 flow rate of 500 sccm on NH3-treated and HF-treated wafers. The HF-treatment results in thicker CET but similar leakage current density. Again, the leakage current is dominated by the HfO2 film itself.
7-3-5 Effect of O2 Flow Rate
From the above results, HfO2 deposited at higher temperature in pure oxygen ambient has better electrical properties. In this subsection, the effect of O2 flow rate was examined.
Fig.7-19(a) and (b) show the C-V characteristics and the leakage current at –1V versus PDA temperature, respectively, of the HfO2 films deposited at 500℃ with different O2 flow rates on HF-treated wafers. The film deposited with low O2 flow rate shows severely distorted C-V characteristic. The leakage current density of samples deposited with high O2 flow rate is lower than that with low O2 flow, too. The deposition temperature plays the same role at low O2 flow rate as at high flow rate. Fig.7-20 shows the leakage current at -1V versus PDA temperature. The deposition parameters are the same as those used in Fig.7-15 except that the deposition ambient is pure O2 at flow arte of 300 sccm. The lower the deposition temperature is, the higher the leakage current density is. These results indicate that higher O2 flow rate, i.e.
sufficient O2 supply in reaction ambient, and higher deposition temperature, i.e. sufficient decomposition of Hf-precursor, are necessary to deposit high quality HfO2.
7-4 Summary
In this chapter, electrical characteristics of HfO2 films deposited at various deposition conditions were investigated. Several important phenomena were observed and summarized as follows.
1. Metals with heat of formation of metal oxides higher than that of HfO2 is not preferred to be used as gate electrode. For example, Al will react with HfO2 to form Al2O3 interfacial layer during Al deposition and poly-Si may react with HfO during dopant activation
2. The gas injection sequence affects the formation of interfacial layer at HfO2/Si interface.
In comparison with the Hf-first scheme, the O2-first scheme results in thicker CET, which accounts for thicker interfacial layer. However, this scheme is still recommended due to the much lower leakage current. To reduce CET to meet the requirement of sub-65nm devices, suitable surface treatment and post deposition processes must be developed.
3. Surface treatment affects the growth of interfacial layer and thus affects the electrical properties. The magnitude of leakage current is in the sequence of RTO-treatment <
NH3-treatment < HF-treatment. NH3-treatment results in the thinnest CET among the three surface treatment methods. However, the hysteresis phenomenon of NH3-treatment sample is severer than that of the RTO-treatment samples apparently.
4. Post surface treatment annealing in N2O ambient or post deposition annealing in N2 or O2
ambient can improve the hysteresis problem but the cost is the increase of CET. Within the experimental conditions in this chapter, it is suggest that in terms of the best interface properties and the lowest leakage current density, RTO-treatment is the best choice.
However, to achieve the thinnest CET, NH3-treatment becomes the most promising method.
5. Higher deposition temperature and purer O2 ambient is benefit to the leakage current
5. Higher deposition temperature and purer O2 ambient is benefit to the leakage current