9-1. Introduction
Silicon dioxide (SiO2) have been used as gate dielectric of CMOS devices for several decades because of its superior properties such as low interface state density, large energy bandgap (8.9eV), low leakage current, and good thermal stability for Si substrate and poly-Si gate. As device dimensions scale down, the thickness of SiO2 must be reduced to keep sufficient current driving capability. But when the thickness of SiO2 becomes thinner than 3.5nm, direct tunneling current increases 100 times for every 0.4~0.5 nm decrease of thickness [1]. This high gate leakage current would increase standby power consumption and induce loss of inversion layer charges. In order to reduce gate current caused by direct tunneling, the physically thickness of dielectrics must increase such that the effective oxide thickness (EOT) can scale down continuously. New gate dielectrics with dielectric constant (k) higher than SiO2 must be developed. Many alternative high dielectric constant (high-k) materials with dielectric constant higher than SiO2 have been studied to overcome the challenge of gate dielectric scale down [2-10]. However, a side effect called fringing-induced barrier lowering (FIBL) arising from the use of high-k gate dielectric has been reported [11-16]. The fringing electric field originated at drain penetrates into channel through the high-k gate dielectric and suppress the barrier height from source to channel. Therefore, the off-state drain current (Ioff) increases and the maximum allowable k value of high-k dielectric is limited by the FIBL effect.
Several works had been performed to understand the effect of FIBL on device and circuit performance. Some works also discussed the effect of device structure on FIBL. Yeap et al reported the FIBL for the first time. The FIBL is clearly evident for k>25 [11]. Remaining high-k dielectric under spacer greatly enhances the FIBL. It is also proposed that an oxide buffer layer under high-k dielectric can suppress the FIBL. Lai et al studied the effect of stack gate dielectric more detailed [12]. But the results of severer FIBL at shallower junction depth and longer spacer
having different source and drain spacer dielectrics [13]. They found that FIBL is caused largely by drain side high-k spacers. On the basis of their results, long spacer length and low dielectric spacer are preferred. Kamata et al simulated the effect of FIBL on elevated source/drain devices and concluded that although the FIBL is enhanced with the extension elevation, the enhancement is negligible with the presence of thin low-K sidewalls [14]. Lin and Kuo reported that the effect of FIBL on SOI devices is similar to that on bulk devices [15], while X. Liu et al reported that the fully depleted SOI device has better immunity on the FIBL induced Ioff degradation [16].
Recently, Mohapatra et al studied the effect of stack gate dielectric and lateral channel engineering and proposed that the overlap length (Lov) between gate and source/drain is an important parameter for FIBL [17, 18].
Although so many works have been conducted to understand the effect of FIBL on device characteristics, the knowledge about FIBL is still insufficient. At first, the above literatures simulated FIBL with different EOT, gate length, junction depth, and/or spacer length (Lsp).
Therefore, some literature reports several orders of magnitude increase of Ioff due to FIBL while another literature reported only a few times increase of Ioff [11, 13, 15]. On the other hand, some confused results were reported for example the longer the spacer is, the severer the FIBL effect is [12]. Finally, the shortest gate length (Lg) studied in previous literature is 50nm [13, 18] but is known that high-k gate dielectric will not be used until the 65 nm technology node which implies a Lg of shorter than 40nm [19].
In this work, two-dimensional simulators SUPREME and MEDICI [20, 21] were employed to study the effect of device structure on FIBL with Lg down to 25 nm. The structural parameters studied including the gate length, the spacer length, the overlap length between gate and source/drain, the stack gate dielectric, and the material of spacer material. The impact of high-k dielectric under spacer is also evaluated. Finally, the effect of FIBL on SOI device is also investigated at the same basis.
9-2 Simulation Procedure
Commercial SUPREME and MEDICI programs were used to generate doping profile and to simulate electrical characteristics, respectively. A typical device structure with simple shallow
doping profile of the 25 nm device are carefully adjusted so that the threshold voltage (Vth) is 0.25 V and the Ioff as k=3.9 is 3x10-7A/um at a drain voltage of 1 volt. This device is called as the 25nm reference device. During the device simulation, poly-depletion, quantum-effect, impact ionization, energy balance, and channel surface scattering are all considered to make sure the designed 25nm reference device with k=3.9 is practical. Five different k values of gate dielectric are simulated. They are 3.9, 15, 25, 50, and 100. The k value of 15 is close to that of Hf-silicate or Zr-silicate while the k value of 25 is close to that of HfO2 or ZrO2 [22]. The channel width and effective oxide thickness is fixed at 1um and 1 nm, respectively. For the SOI devices, the thickness of Si layer is 50 nm and the channel and source/drain doping profiles are identical to those used for bulk devices. Because it is a fully depleted device, the threshold voltage of the SOI device is slightly lower than that of the bulk device. In the whole work, only NMOSFET was simulated.
9-3 Results and Discussion
9-3-1 Basic Phenomenon
Fig.1 compares the Ioff/Ioff(k=3.9) ratio as a function of k value of devices with Lg=50nm and 25nm. The doping condition of the 50 nm device is identical to that of the 25 nm reference device.
As expected, the Ioff degradation increases with the decrease of gate length and the increase of k value of gate dielectric. Since the Lsp and device doping are fixed, the observed difference of Ioff degradation between devices is simply attributed to the gate length effect. It should be noted that the increase of Ioff as k value increases from 3.9 to 100 is less than one decade even if the Lg is only 25 nm. It seems that the FIBL effect does not degrade Ioff as serious as those reported previously. This discrepancy will be discussed later.
It was reported that the high-k dielectric should exist under gate electrode only. Otherwise, the high-k dielectric under spacer will enhance the FIBL effect [11]. Unfortunately, to remove exposed high-k dielectric after gate etching is very difficult. At first, traditional poly-Si gate etching must stop on gate dielectric to avoid micro-trenching phenomenon at gate edge. Second, the thermal annealed HfO2 or ZrO2 film is hard to be wet etched [23, 24]. No chemical which can etch HfO2 or ZrO2 at sufficient high etching rate while has sufficient selectivity to field oxide has been proposed till now. Since the above suggestion is drawn at the condition of Lg=70nm, k=100,
under spacer at sub-45nm technology node.
The structure with high-k dielectric under gate electrode only is noted as UG structure and the structure with high-k dielectric under both gate electrode and spacer is noted as UGS structure.
Fig.2 shows the Ioff/Ioff(k=3.9) ratio as a function of k value of devices with Lg=25nm. The inset is the schematic drawings of UG and UGS structures. It is clear that as k value is lower than 25, the FIBL effect is not serious and the difference between UG device and USG device is negligible.
This result indicates that it is not necessary to remove high-k dielectric immediately after gate patterning if the k value is not higher than 25 if there are no other issues such as contamination, parasitic capacitance, etc. The device integration can be simplified.
9-3-2 Effect of Lov
Electric potential distribution is simulated with the MEDICI program and is shown in Fig.3.
Both Lg and Lsp are 25nm and k value is 100. In this simulation, gate, source, and substrate are all grounded and drain is biased at 1V. It is observed that most of the fringing field lines which originate from drain region out of spacer and under spacer tend to terminate at gate electrode. The main fringing field resulting in barrier lowering originates from the gate/drain (G/D) overlap region.
Since the fringing field originates from the G/D overlap region, FIBL should be sensitive to the length of overlap region (Lov). To verify this inference, devices with doping profile identical to that of the 25nm reference device but with various G/D overlap were simulated. The Lov in Fig.3 is 1 nm. To increase the Lov while keeps the same source/drain doping profile and similar device performance, the spacer, gate electrode, and gate oxide were removed after generating the reference device. Then, gate structure with Lg=50 nm was reconstructed so that the Lov becomes 13.5nm. Fig.4 shows the simulated equal potential contours at drain voltage of 1V. Comparing with Fig.3, the long Lov enhances the penetration of fringing field into channel region. Fig.5 shows that the Ioff degradation of device with Lov=13.5 nm is one order of magnitude higher than that with Lov=1nm. Since the Lov decreases with the scale down of design rule to control the short channel effect, the degradation of Ioff due to FIBL effect could be relaxed due to the short Lov. In the earlier study on FIBL effect, device structure is designed following the 90nm or 130nm
9-3-3 Effect of Spacer Length
Because both Lg and Lsp were scaled down simultaneously in most of the literatures, which factor dominates the Ioff degradation is not clear. To clarify the effect of Lsp on FIBL, devices with identical effective channel length but different Lsp must be generated. To achieve this, the 25nm reference device was generated at first. Then the spacer was removed and a 50nm long spacer was reformed. Fig.6 shows the I-V curves of devices with various Lsp as k=100. The inset illustrates the schematic structure of the devices. It is observed that the Ioff degradation is reduced by the reduction of spacer length. This observation is similar to that reported by Lai et al. [12].
Lai explained their observation by the decrease of FIBL region as Lsp decreases. However, as discussed in previous sub-section, the fringing field originating from the region out of the gate/drain overlap region plays minor role on the FIBL effect. We propose a new mechanism to explain the effect of spacer length.
It is known that the fringing field exits at both drain side and source side. The drain electrode is biased at high voltage and the fringing field from drain side tends to lower the electron injecting barrier height near source side. Since the source electrode is grounded, the fringing field from source side tends to sustain the channel barrier height. This is called the Fringing-Induced Barrier Shielding (FIBS) and was proposed by D. L. Kencke et al and Y.
Kamata et al. [13, 14]. As the Lsp increases, the FIBL effect from drain side is less affected by the long spacer because the FIBL effect is dominated by the gate/drain overlap region. However, the source electrode becomes away from channel as the spacer length increases and the FIBS effect from source side becomes weak. The shorter the Lsp is, the stronger the FIBS effect is. For the short Lsp device, the FIBS effect from source side compensates the FIBL effect from drain side partly. Therefore, shorter Lsp results in less Ioff degradation. Fig.7(a) and (b) show the equal potential contours of the devices with Lsp=25nm and Lsp=50nm, respectively. The dense potential contour at source side of the Lsp=25nm device supports the above explanation. This phenomenon is positive because the spacer length scales with the gate length.
9-3-4 Stack Gate Dielectric
It is known that stack gate dielectric, a buffer SiO2 layer under or above the high k dielectric,
under high-k layer than above high-k layer. This difference can be explained by the observation in the previous sub-section. Since the fringing field originates from the G/D overlap region, it enters high-k layer if the buffer SiO2 layer is located above high-k layer. In the case of fixed EOT, the effect of buffer layer is to reduce the thickness of high-k layer. Therefore, the improvement of FIBL effect is very limited. On the other hand, as the buffer layer is located under the high-k layer, fringing field enter the buffer layer at first. Therefore, the low dielectric constant of the buffer layer relaxes the FIBL effect apparently. Fig.8 shows the simulated I-V curves of devices with various gate dielectric structures. The device structure parameters are Lg=25 nm, Lsp=25 nm, Lov=1 nm, and EOT=1 nm. It is observed that the FIBL induced Ioff degradation as k=100 can be reduced by 50% using stack gate dielectric of 0.3nm thick buffer SiO2 layer under the high-k layer. However, the FIBL effect can not be eliminated totally using this strategy.
In real case, it is difficult to avoid a buffer layer or interfacial layer between Si channel and high-k layer. Buffer SiO2 layer can improve carrier mobility [25, 26] but it will hurt the EOT because of its relatively low k value. Fortunately, several literatures reported that a Hf-silicate (Zr-silicate) layer forms if HfO2 (ZrO2) is used as gate dielectric [27-29]. The k-value of both kinds of silicate is around 15. Fig.9 compares the effect of k value of buffer layer. The EOT of buffer layer is fixed at 0.3nm and the total EOT of stack gate dielectric is fixed at 1nm. The k value of high-k layer is 100. It is observed that as Lov is 1 nm, either the k value of buffer layer being 3.9 or 15 results in almost identical Ioff. However, as Lov=13.5nm, buffer layer with higher k value results in slightly lower Ioff. To explain this unexpected phenomenon, the electric potential distribution of devices with Lov=13.5nm and different buffer layer are examined. Using SiO2 as buffer layer, Fig.10(a) shows that because the SiO2 layer is only 0.3nm thick, fringing field can penetrate the SiO2 layer and enter the high-k layer easily. Since the EOT of buffer layer is fixed at 0.3nm, the physical buffer layer thickness as k=15 is thicker than that as k=3.9 so that less fringing field enters the upper high-k layer as shown in Fig.10(b). According to the result shown in Fig.1, the FIBL effect as k=15 is negligible and then the FIBL effect of device with buffer layer of k=15 is lower than that of k=3.9. It is thus concluded that the interfacial layer formed at the high-k/Si interface can relax the FIBL effect no matter it is oxide or silicate and silicate is preferred from the FIBL effect point of view.
Since the fringing field terminating at gate electrode plays no role on Ioff degradation, it is expected that using conductive spacer to attract fringing field may be a possible solution to suppress FIBL effect. Device with conductive spacer has been proposed by F. Gonzalez et al to reduce short channel effect [30]. Fig.11 shows the equal potential contours of device with conductive spacer. The device parameters are Lg=25nm, Lsp=25nm, Lov=1nm, and k=100. The spacer is consists of an insulating layer of 3nm thick and a conductive layer of 22 nm thick. The conductive spacer is kept at the same potential as the gate electrode. It is observed that that fringing field near gate edge directs toward conductive spacer now. Fig.12 shows the efficiency of conductive spacer on the Ioff degradation. With Lov=1nm and 13nm, Ioff as k=100 can be improved to 3.6 and 2 times of that as k=3.9, respectively. Again, G/D overlap length dominates the FIBL effect.
Fig.13(a) and (b) summarize the FIBL of 25nm devices with various structures. As Lov=1nm, single high-k dielectric results in Ioff degradation of 23 times. A 0.3nm thick interfacial SiO2 layer reduces the degradation to 3.6 times, while conductive spacer reduces the dagradation to 3.3.
Combining stack dielectric and conductive spacer, the Ioff degradation can be reduced to 1.6 times.
As Lov=13nm, similar tendency is observed but Ioff degradation is higher than one order of magnitude for all structures. It should be noted that as the k value is reduced to 25, all of the corresponded Ioff degradation are lower than 1.5.
9-3-6 SOI versus Bulk Devicesl
The FIBL effect on SOI devices have been studied in some literatures [15, 16]. It is reported that SOI devices, especially fully depleted SOI devices, has better resistance to FIBL effect. The gate length used in the previous studies is 70-100nm. Since SOI device would be the mainstream beyond the 45nm technology node, the FIBL induced Ioff degradation on SOI and bulk devices are compared. The Lg and Lsp are 25nm and the EOT is 1nm for both SOI and bulk devices.
In Fig.14, it is confirmed that the Ioff degradation of SOI device is smaller than that of bulk device. This phenomenon can be explained by the thin Si layer. Because the thin Si layer of SOI, the space charge in channel depletion region of SOI device is fewer than that of bulk device, and then gate voltage has higher efficiency to control the channel surface potential. It is also clear that stack gate dielectric and conductive spacer can relax the Ioff degradation. Longer Lov results in
the Lov can be controlled to be 1 nm, simple stack gate dielectric scheme can reduce the Ioff
degradation factor to two even if the K-value of high-k dielectric is 100. It is expected that the novel device structures such as ultra-thin body SOI, double gate SOI, as well as FinFET can further improve the Ioff degradation.
9-4 Conclusion
In this work, TCAD tools were used to investigate the FIBL effect at sub-45nm technology node and beyond comprehensively. The effect of device structure was also examined. Although the FIBL effect becomes more pronounced as gate length becomes shorter, the Ioff degradation due to FIBL from drain side will be partly compensated by the FIBS from source side if the spacer length scales down with the gate length. The key factor to affect the FIBL effect is the gate to drain overlap length. Most of the fringing field originating from this region. Since the overlap length must be reduced to control short channel effect, it is expected that the FIBL effect can be further relaxed. Because the overlap length plays important role, high-k material existing under spacer does not affect FIBL apparently if K-value does not exceed 50. This result implies that the most promising high-k candidate – HfO2 can be removed after spacer formation. The device integration can be easier.
It is known that stack gate dielectric scheme with a buffer SiO2 layer between high-k dielectric and Si substrate can relax the FIBL effect. This work reveals that a medium K-value buffer layer, for example Hf-silicate, still has the same influence. Conductive spacer is another effective method to reduce FIBL effect but the process is more complicate.
Fully depleted SOI device shows better resistance to FIBL induced Ioff degradation due to
Fully depleted SOI device shows better resistance to FIBL induced Ioff degradation due to