A 10-bit 100-MS/s Two-Step ADC

5.1 Introduction

For wireless communication, a 10-bit 100-MSPS ADC can be a good design example. In general, the pipelined ADC architectures are often considered to implement with oper-ational amplifiers. But due to the characteristic of nanometer CMOS devices, amplifier design is more difficult if the device’s length is smaller at low supply voltage. This is because the operational amplifier needs higher gain-bandwidth requirement (for example, 10-bit ADC needs an operational amplifier with open-loop gain of over 60dB, but intrinsic gain of nanometer CMOS transistors is generally lower than 20dB.). To maintain enough output dynamic range of the amplifier, the amplifier design becomes more complicated.

Moreover, the amplifier design is highly sensitive to CMOS technologies. It means that analog designers may think of new amplifier’s architecture while changing to next ad-vanced CMOS process. To solve this issue, we must simplify the analog circuits to adapt for scaled CMOS technologies.

Considering the fact that flash ADC architecture consists of only comparators which are easily implemented with the nanometer CMOS devices. But unfortunately, for 10-bit resolution, flash ADC is not suitable due to the usage of 1024 comparators. Subranging ADC architecture is similar to flash ADC, but with less comparators. For medium speed operation (between 20-MSPS and 200-MSPS), subranging ADCs provide another choice with lower power consumption. There is no high linearity amplifier requirement to

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plement a subranging ADC. In general, it only needs comparators, MUX and a resistor string. The resolution of the comparator is one of the key issues. Another issue is the complex MUX which is always the bottleneck of ADC operating speed. Again, due to the nanometer CMOS devices, the performance of the switches is worse. To improve the issues of the subranging ADC, the two-step ADC architecture was proposed. It contains coarse-ADC, fine ADC, resistor-string DAC and residue amplifier. Combining with the considerations of flash ADC and subranging ADC architectures, we examine the two-step ADC architecture and demonstrate their performances in the nanoscale CMOS technolo-gies. Our proposed ADC design concept is to simplify the necessary analog circuits and digitally enhance the analog circuitry by the proposed background calibration technique.

In this chapter, the proposed ADC architecture is illustrated in Section 5.2. Section 5.3 describes the building blocks with their circuit designs in detail. Section 5.4 shows the measurement results. Section 5.5 draws a brief summary with the 10-bit ADCs compari-son results.

5.2 Architecture

The proposed 10-bit two-step ADC architecture is shown in Figure 5.1. The ADC operates with two non-overlapping clocks, φ₁ and φ₂. The duty ratios for φ₁ and φ₂ are 25% and 75% respectively. The clock φ1a is the advanced version of φ1, for the bottom plate sampling purpose. The major clock timing is shown in Figure 5.2. φ₁, φ_1a and φ₂ are global clocks, generated from the clock generator. The clocks φcand φpare locak clocks, generated in coarse ADC. φc is applied to driving the latch circuits and φp is applied to offset compensation for the latch circuits. The clocks φ^f and φx are locak clocks, generated in fine ADC. φfis applied to driving the latch circuits and φxis applied to offset compensation for the latch circuits. The clock φd is used for digital circuits, including calibration processor and DEC.

At the beginning of φ2 = 1, the coarse ADC (CADC) compares the analog input V₁ with 33 coarse references VRC to estimate the magnitude of V₁, yielding the 5-bit digital output D₁. The VRC references are generated from a resistor string. The D₁code and q drives the resistor-DAC (RDAC) to select one voltage from 96 possible voltages,

φ1

Figure 5.1: Proposed two-step ADC architecture.

φ

Figure 5.2: Major clock signals used in the two-step ADC.

generated by the resistor string. Its output, Vda, is an estimation of the input V1.

During φ1 = 1, the analog input V1 is also sampled onto the sampling capacitor Cs. During φ₂ = 1, the residue amplifier (RAMP) amplifies the difference between V1 and V_da, yielding the amplified residue signal V₂. The RAMP is an open-loop amplifier with a nominal voltage gain of 8. The fine ADC (FADC) then compares the residue V2 with 65 fine references VRF to estimate the magnitude of V₂, yielding the 6-bit digital output D₂. The FADC has an input range of 64 steps. In an ideal two-step ADC, the FADC needs only an input range of 32 steps. The 1-bit redundancy is added to tolerate the gain error and offset of the RAMP, and comparator offset in the CADC. It is also used to accommodate the extra signal range required by the RAMP digital calibration. The RAMP voltage gain mitigates the FADC resolution requirement. To reduce power consumption, the RAMP uses an open-loop single-stage amplifier. Its gain error and nonlinearity are corrected by the digital calibration processor (DCP) shown in Figure 5.1. The DCP receives the D₂ code from the FADC and generates a corrected D^c₂ code. The digital error correction (DEC) then combines D₁ and D^c₂ to produce the final ADC digital output D_o. The DCP also generates a digital random sequence q ∈ {−1, 0,+1}. The q sequence also drives the RDAC so that a random signal is injected into the RAMP. The DCP uses this random signal to calibrate the RAMP in the background.

The analog signal path of the ADC is fully differential. The top and bottom reference voltages are set to be VDD and VSS respectively. Using supply and ground voltages as the references can save the power consumption of the reference buffers. The ADC differential input range is ’2 × VDD’ (in this design, it is 2 V). One LSB is 1.95 mV for 10-bit resolution. To adapt for output range and gain of the residue amplifier, the FADC has a differential input range of 1 V and a step size of 8 LSB. The gain of residue amplifier can really mitigate the resolution of the FADC.

D1

Figure 5.3: The 5-bit flash type CADC.

5.3 Circuits Description

5.3.1 Comparator

The CADC is a 5-bit flash ADC, shown in Figure 5.3, which consists of 33 comparators, de-bubble logic, clock buffers and a dynamic ROM encoder. The comparator is imple-mented by the latch type comparator with an offset compensation loop, mentioned in Section 3.4. The analog input V₁is directly connected to the ADC’s input. The reference voltages VRC[n], n = 0 · · · 32 are provided by the resistor string in the RDAC. The extra two references VRC[0] and VRC[32] are applied to checking the top and bottom range of the ADC input signal. Two global clock signals φ_1a and φ₂ provide the CADC timing information.

Figure 5.4 shows the architecture of the comparator in the CADC. Its function is com-paring the input V₁ with a reference V_RC[n], where n is an integer between 0 and 32 for indexing one of the VRC coarse references. The comparator includes a regenerative latch with an offset calibration control loop. To reduce power consumption, there is no conven-tional pre-amplifier. The VOS in front of the latch represents the input-referred offset of the latch due to device mismatches. The Vcmrepresents the input common-mode voltage.

The latch is triggered by the clock φc, which is generated from the clock signals φ_1aand φ₂. Comparisons are made near the beginnings of both φ1 and φ2periods. The compar-ison determines the polarity of the differential voltage at the input port V^a, but with an equivalent input offset of VOS+ Vc− V_cm. In Figure 5.4, the switch S3 is controlled by the clock φ1a, which is an advanced version of the clock φ1. The switch S3 is opened before

φ _c

Figure 5.4: CADC comparator architecture.

t3

Figure 5.5: Timing generator for comparator.