é .é@~X
}ÿ¡Z
±£vfó»ð
'*
Low-Power Analog-to-Digital Converters
Design Techniques
@~ß : 'KÁ
¼0>0 : Ò+/
'*
Low-Power Analog-to-Digital Converters
Design Techniques
@~ß : 'KÁ
Student : Yung-Hui Chung
¼0>0 : Ò+/
Advisor : Jieh-Tsorng Wu
»ñø;.
é .
é@~X
}ÿ¡Z
A Dissertation
Submitted to Department of Electronics Engineering
and Institute of Electronics
National Chiao-Tung University
in partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
July 2010
Hsin-Chu, Taiwan, Republic of China
ºÓ»ÜèÜOÚ`
'*
.ß : 'KÁ
¼0>0 : Ò+/
»ñø;.
é .
é@~X
`
Í¡ZxÎ"D3{ CMOS % ìA¢'×Í{Pv±Ý vfó»ð (Analog-to-Digital Converter, ADC) ¼ÙþnÝmO× vfó»ð Îãf´ w vf né é õóé XxWf´ w ÎËË´éÝvfé{%Ýéþ μ>¼"¼±EóébÁÝ? Ey± (+y°-Õâ- ) |f´ xÝvfó»ð | E®3?{Ýãø£¸Æ|.%¹ÇÍJxãf´ ¼X Ey{ (+yè-Õè"- ) |w xÝvfó »ð ÚxãyºTéD±éþÝ/IéD¦Ç{% ¬^b©½Ý? 8DÝvfó»ð XmÝÞãw éº.±ºT éD±/IéD¦Ç?9£.hA¢3{% ì. î ËËvf馣|'{Pv±Ývfó» ð JÎÍ¡ZÝ@~¥F i»ð ݣ͡Zè×Í|¦Å (Latch) xÝf´ éAh |tGHw XmÝV£ny¦Å ÝíáÉéD®ÞJ¢ ã×ÍÁ±ÝÉlÑ]¼;9˱lÝf´ ½¸à3f´ xÝvfó»ð |»ª±ÍJ£ 3w Ý']« Ýã{Þ@w Í¡Zè©¿àÝ ]±£-w ¼wGr9ËÝw |ÊT CMOS %Ý "!`ô;vféÝ'ÓQ9Ëw b¦Ç0-C&aPÝ &§ 3Å(vfó»ð Ñð ®ìÍ¡ZèÝ×ͱlÝó eÿlÑ*¼ÑÑîw Ý&§P«E¹Ý%¹9ó| w xÝvfó»ð K¿àÍ¡ZXèÝóeÿlÑ*¼¹y '` ª±J£ &Æè×ÍÞ$Pvfó»ð 'æl¼JÍ¡ZXèÝ* |¾W±ºTéD±£ÝO9Í'Î×Íè-NJ× gãø Þ$Pvfó»ð â×Íyõw ÜèâÍf´ 9Ívfó »ð þnÎ| 90 { CMOS %%®ºTéDÎ 1.0 ©3íá*r £ ×y0>+`¾Õ 75dB ÝPÓ÷*rVP (SFDR) C 58dB Ý* rEÓG´Ëf (SNDR) ¿àÝw éGݱPf´ é 9Í»ð ÍÝJ£ 6 mÝ/Iþn« 0.36 ¿]m{& ÆXèÝólÑ § Í£y 1 mÝ ii
Design Techniques
Student : Yung-Hui Chung
Advisor : Jieh-Tsorng Wu
Department of Electronics Engineering
and Institute of Electronics
National Chiao-Tung University
Abstract
This thesis describes how to design a high performance and low power analog-to-digital converter (ADC) to meet the SOC requirement on nanoscaled CMOS technolo-gies. In general, an ADC is constructed by comparators, amplifiers, analog switches, capacitors, resistors and digital circuits. Comaprators and amplifiers are two power con-suming analog circuits. Digital circuits benefit CMOS scaling since transistor is smaller, speed is faster and power consumption is lower. For low resolution (between 4 and 8 bits) comparator-based ADCs, they can operate at higher sampling frequency. They also bene-fit CMOS scaling, and their power consumption is dominant by comparators. For medium and high resolution (between 10 and 15 bits) amplifier-based ADCs, they do not benefit from nanoscaled CMOS technologies. On the contrary, larger power consumption is nec-essary for accurate amplifiers in ADCs due to lower supply voltage and lower transistors intrinsic gain. Therefore, how to design high performance and low power ADCs without larger power dissipation due to comparators and amplifiers is the research emphasis in
For comparator design, traditional design concepts usually use pre-amplifier to reduce its overall input offset voltage. However, the static power consumption of the pre-amplifier will greatly increase the comparator-based ADC power dissipation. In this thesis, we uses a latch-type comparator to eliminate the static power consumption of the pre-amplifier. About the input offset voltage of a latch, we proposed a very low power offset calibration loop to improve. The proposed comparator can be widely applied to comparator-based ADCs to reduce their overall power dissipation.
For amplifier design, instead of high accurate amplifier, we proposed a simple low power open-loop differential amplifier to amplify the residue signal. This amplifier can adapt for scaled CMOS technologies and also simplify the design complexity for analog circuits. But this simple amplifier has certain non-idealities: gain error and nonlinear-ity. Without interrupting ADC normal operation, we proposed a new digital background calibration technique to correct these non-idealities. Most amplifier-based ADCs can use the proposed calibration technique to shorten the design time and reduce overall power dissipation for continuous CMOS scaling.
A two-step ADC prototype is manufactured to verify the proposed techniques in this thesis to achieve the requirements of low supply voltage and low power consumption. It is a 10-bit 100-MS/s two-step ADC including one residue amplifier and ninety-eight comparators. This ADC is fabricated using a 90 nm CMOS technology with 1.0 V supply voltage. At 1 MHz input frequency, this ADC can achieve the performance of 75 dB SFDR and 58 dB SNDR. Using a simple open-loop amplifier and proposed comparator circuits, this ADC dissipates a total power of 6 mW and occupies die area of 0.36 mm2. The power consumption of the proposed digital calibration processor is less than 1 mW.
&E&ݼ0>0 Ò+/>0lît{ݯ 3&ãÿ}ÿ. Ý9ð E&ݼ0ÜÃ/E@~`²]°Ý}OÑÎ&Æ Î¼3@~`t¥Ý*FÃæ?áݤC?½Ý.êW µ?¾!Ý@~W9°@~§FîÝ£[¸&åÇ9 & @~NÝ!.o@õ?ÑrÇ*rú] ¿39ð ¯ÆÝ8 E®ÞÝD¡èº&9ßþݶô?² °&Ý@~ô .Òh8ù âÅ"ùãO{³ b¯Æ3&˯îÝÜï&ÝT@~ ¨² æI*èºþnìaÝ^º /X ÝÜï &È5¿WþnÝ%® h²&©½ &Ý ×@GÎ&T·îÝ 3ô3@~Ý ¼î&÷W! &ÝÉu@ÝFFKÎîFE&ݽ ) t¡¯Þ&Ý¡Z¤&tÝÝlÒ ÆóèO¼ÝyÇò =
'KÁ
»ñø;. ºÓ»ÜèÜOÚ` vZ` i
English Abstract iii
* v
List of Tables xi
List of Figures xiii
1 Introduction 1
1.1 Green Power Era . . . 1
1.2 Motivation . . . 4
1.3 Organization . . . 5
2 Overview of the ADCs 7 2.1 Introduction . . . 7 2.2 Track-and-Hold Amplifier . . . 10 2.3 Flash Architecture . . . 14 2.4 Successive-Approximation Architecture . . . 16 2.5 Subranging Architecture . . . 18 2.6 Two-step Architecture . . . 22 2.7 Pipelined Architecture . . . 24 2.8 Summary . . . 27 vii
3.2 Traditional Comparator Design . . . 31
3.2.1 Spatial Averaging Technique . . . 35
3.2.2 Interpolation Technique . . . 38
3.2.3 Offset Storage Techniques . . . 39
3.3 Offset Feedback Compensation Schemes . . . 44
3.3.1 The Analog Latches . . . 47
3.3.2 Offset Compensation . . . 47
3.3.3 Offset Estimation . . . 54
3.4 Proposed Comparator Design . . . 57
3.4.1 Comparator Architecture . . . 57
3.4.2 Offset Cancellation . . . 59
3.4.3 Kickback Noise . . . 63
3.5 Summary . . . 65
4 Nonlinearity Calibration Techniques 69 4.1 Introduction . . . 69
4.2 Calibration Techniques . . . 71
4.2.1 Estimation . . . 72
4.2.2 Compensation . . . 77
4.2.3 Capability . . . 79
4.3 Prior Nonlinear Calibration Schemes . . . 83
4.3.1 Redundant Residue Calibration Technique . . . 87
4.3.2 Boostrapped Digital Calibration Technique . . . 90
4.3.3 Blind LMS Calibration Technique . . . 94
4.3.4 Harmonic Distortion Correction Technique . . . 97
4.4 Proposed Calibration technique . . . 100
4.4.1 Calibration Mechanism . . . 101
4.4.2 Signal Compensation . . . 104
4.4.3 Coefficient Estimation . . . 104
5 A 10-bit 100-MS/s Two-Step ADC 113
5.1 Introduction . . . 113
5.2 Architecture . . . 114
5.3 Circuits Description . . . 117
5.3.1 Comparator . . . 117
5.3.2 Residue Amplifier (RAMP) . . . 123
5.3.3 Resistor-String DAC (RDAC) . . . 126
5.3.4 Distributed Input Track-and-Hold . . . 128
5.3.5 Digital Calibration Processor . . . 130
5.3.6 Other Digital Circuits . . . 135
5.4 Experimental Results . . . 137
5.5 Summary . . . 145
6 Conclusions and Future Works 147 6.1 Conclusions . . . 147
6.2 Recommendations for Future Investigation . . . 148
Appendix A Lyapunov Second Theorem on Stability 151 Appendix B Comparator Modeling 155 B.1 Comparison Speed . . . 155
B.2 Input-Referred Noise . . . 160
Appendix C Design Considerations 167 C.1 Sampling Clock Jitter . . . 167
C.2 Distributed Input Track-and-Hold . . . 168
Appendix D Nanometer CMOS Characteristics 171 D.1 Supply Voltage . . . 171
D.2 Gate Leakage . . . 173
F
Publication List 190
2.1 Prior flash ADCs . . . 16
2.2 Prior SAR ADCs . . . 18
2.3 Prior subranging ADCs . . . 20
2.4 Prior two-step ADCs . . . 23
2.5 Prior pipelined ADCs . . . 27
5.1 RAMP transistor size summary . . . 124
5.2 Performance Summary . . . 144
5.3 10-bit ADCs comparison . . . 145
B.1 Comparison between predicted, simulated and measured input-referred noise σn . . . 164
1.1 Electrical components inside a representative cell phone. . . 2
2.1 Two simple partitions of Nyquist-rate ADCs. . . 8
2.2 Simplified T/H configurations: (a) switched-capacitor, (b) source-follower and (c) flip-around. . . 11
2.3 A flash ADC architecture. . . 13
2.4 A general comparator design. . . 15
2.5 A 4-bit SAR ADC and its quantization sequence. . . 17
2.6 A 10-bit subranging ADC architecture. . . 19
2.7 A 10-bit two-step ADC architecture. . . 21
2.8 A 10-bit pipelined ADC architecture. . . 23
2.9 Transfer curves for (a) 1-bit per stage and (b) 1.5-bit per stage. . . 25
2.10 ADC limitation boundaries between resolution and sampling frequency. . 29
2.11 ADC survey from 1997 to 2010 on two major conferences: ISSCC and VLSI. . . 30
3.1 A traditional comparator design. . . 33
3.2 Averaging technique to reduce the comparator’s offset. . . 36
3.3 DNL and INL reduction factors with respect to R1/R0. . . 37
3.4 Interpolation technique by resistive network. . . 38
3.5 Interpolation technique by capacitive network. . . 40
3.6 Output offset storage technique to cancel the comparator’s input offset. . . 42
3.7 Input offset storage technique to cancel the comparator’s input offset. . . . 43
3.8 A latch comparator with a feedback compensation loop. . . 45
3.11 Gm-Adjustment Offset Compensation Methods . . . 50
3.12 Gm-Adjustment: (a) input-injection (b) body-bias control (c) auxiliary compensation pair. . . 51
3.13 (a) C-adjustment offset compensation methods and (b) Digitally con-trolled capacitance implementation. . . 53
3.14 Deterministic offset estimation: (a) operation and (b) voltage adjustment. 55 3.15 Offset estimation by using statistics based detector. . . 56
3.16 Proposed offset-calibrated comparator architecture. . . 58
3.17 Proposed latch comparator schematic. . . 60
3.18 Variable adjustment voltage step to suppress the fluctuation range. . . 61
3.19 Simulation result for a latch comparator with OCCP. . . 62
3.20 Kickback noise reduction techniques. (a) Neutralization. (b) Isolation-1. (c) Isolation-2. . . 64
3.21 (a) Traditional design and (b) proposed design for kickback noise. . . 66
3.22 Kickback noise for different Vbx conditions with 1 KΩ resistor connection. 66 4.1 Residue amplifier by using (a) opamp with feedback resistor, (b) opamp with feedback capacitor and (c) open-loop amplifier. . . 70
4.2 The categories of calibration techniques. . . 72
4.3 Foreground estimation for A/D conversion. . . 73
4.4 Correlation-based background estimation for A/D conversion. . . 74
4.5 Background estimation with reference-ADC for A/D conversion (a) block diagram and (b) digital post processor. . . 76
4.6 Analog compensation methods for (a) circuit adjustment and (b) inverse function. . . 77
4.7 Digital compensation method. . . 79
4.8 Pipelined stage with 1.5-bit configuration and the transfer curve of MDAC. 81 4.9 Radix-2 1.5-b switched-capacitor network: (a) conventional, (b) back-ground calibration and (c) q-control transfer curve for N=4. . . 82
calibration and (c) with linear calibration. . . 86
4.12 Redundant residue calibration (a) block diagram, (b) two residue modes and (c) redundant residues with nonlinearity. . . 88
4.13 Digital post-processor for the redundant residue calibration. . . 90
4.14 Bootstrapped calibration technique (a) block diagram, (b) gain error cor-rection and (c) nonlinearity corcor-rection. . . 91
4.15 Pipelined ADC with blind LMS calibration technique. . . 94
4.16 (a) Calibration concept and (b) input-output characteristic of blind LMS calibration technique. . . 95
4.17 Simplified representation of a 14-bit pipelined ADC with HDC applied to the first pipeline stage. . . 97
4.18 Block diagram of the HDC logic in the first stage. . . 99
4.19 Proposed digital calibration processor. . . 102
4.20 Gain error and nonlinearity detection. . . 103
4.21 The digital signal compensator. . . 105
4.22 The digital coefficient estimator. . . 105
4.23 Convergent behavior for the estimation with (a) limit cycle issue, (b) global concave solution and (c) local concave solutions. . . 108
4.24 The global concave solution for b1and b3. . . 110
4.25 Linearity before and after calibration. . . 110
5.1 Proposed two-step ADC architecture. . . 115
5.2 Major clock signals used in the two-step ADC. . . 115
5.3 The 5-bit flash type CADC. . . 117
5.4 CADC comparator architecture. . . 118
5.5 Timing generator for comparator. . . 118
5.6 Schematic of the latch in CADC comparator. . . 120
5.7 FADC comparator architecture. . . 122
5.8 Schematic of the latch in FADC comparator. . . 122
5.11 Schematic of the bootstrapped switch. . . 126
5.12 Layout of two resistor strings with the opposite direction. . . 128
5.13 Schematic of the resistor-string DAC. . . 129
5.14 Distributed input track-and-hold. . . 129
5.15 The proposed digital calibration processor (DCP): (a) signal compensator and (b) coefficient estimator. . . 131
5.16 Transient behavior of the proposed digital calibration scheme. . . 134
5.17 Simplified dynamic ROM used in the FADC. . . 136
5.18 ADC chip micrograph. . . 138
5.19 Block diagram of the instrumentation setup. . . 139
5.20 Measured CADC differential nonlinearity (DNL). . . 139
5.21 Measured ADC differential nonlinearity (DNL). . . 141
5.22 Measured ADC integral nonlinearity (INL). . . 141
5.23 Measured output spectrum at 100MS/s before and after RAMP’s calibration.142 5.24 Measured output spectrum with 40MHz input frequency at 100MS/s. . . . 142
5.25 Dynamic performance versus input frequency. . . 143
5.26 Dynamic performance versus sampling frequency. . . 143
B.1 Latch-type comparator schematic. . . 156
B.2 Comparator schematic for noise analysis. . . 159
B.3 Large signal transient plot for three operating phase. . . 159
B.4 The input-referred noise depends on F and H. . . 165
C.1 Distributed input track-and-hold network, (a) queuing network and (b) tree network. . . 169
D.1 Amplifier output stage. . . 174
D.2 Supply voltage issue for sampling capacitance and sampling energy. . . . 174
D.3 Gate leakage on a high impedance node for (a) nMOS gate and (b) its equivalent circuit. . . 175
Introduction
1.1
Green Power Era
The electronic products can be simply categorized into battery-powered and non-battery-powered. In recent years, based on the technology development, the portable products increase dramatically rapidly. Their fantastic functionality brings people more conve-nience and fun. However, these portable products face a fundamental problem: how to extend the battery usage? Therefore, for more and more portable electronic products, how to achieve ultra low power dissipation becomes an important issue under the green power era. Low supply voltage can decrease the usage of battery. Moreover, low power elements of the products can maintain longer battery usage time.
In this decade, based on the Moore’s law, the CMOS integrated circuits can operate under lower supply voltage and less power dissipation. SOC (System-on-a-Chip) is a trivial methodology to achieve these fantastic characteristics. Using SOC, the extra power consumption of the interfaces between chips can be saved and the size of the product can be smaller. Advanced CMOS technologies (e.g. 65 nm) provide SOC methodology more powerful functions: lower power consumption, faster operating speed and more flexible utilities. We can say that combination of advanced CMOS technologies and SOC integra-tion, the portable products can be implemented more suitable for people’s requirements: low cost, convenient usage, and micro-volume.
In 2003, [1] provided their several points of view about the SOC and how does it
help to implement powerful personal Internet products (PIPs). These PIPs are designed as communication, computing and consumer products, which are enabled by the Internet: cell phones, PDAs, WLANs and Internet audio/video. These PIPs are based on digital signal processing (DSP) and analog functionalities. And they are made accessible to bil-lions of people around the globe by intense focus on cost through SOC integration. In the Internet age, Moore’s law will continue to be a technology imperative for the semicon-ductor industry. Moreover, SOC integration will be an additional technology imperative that drives down the cost of PIPs to mass market levels. SOC integration for PIPs requires the integration of analog, power analog, RF and memory onto the digital baseband pro-cessor, which is fabricated in high density, high performance and low cost digital CMOS technology.
Cell phone is the typical product of the PIPs. Figure 1.1 shows the electrical compo-nents in a cell phone. The digital, analog, RF and memory compocompo-nents are on separate ICs. To reduce the cost, SOC integration is further applied based on nanometer CMOS technologies. DSP functionality is greatly improved, but other analog and RF circuits will face the difficulties of implementation due to low supply voltage and poor transis-tors’ linearity. To implement SOC technology, analog circuits must be constructed on the same digital CMOS process and integrated with other digital and memory circuits. How-ever, nanometer CMOS devices are more suitable for digital circuits but worse for analog circuits. These transistors have faster speed but lower intrinsic gain and linearity.
To meet the required performance, some traditional analog designers use I/O devices with much higher supply voltage (for example, 1.0 V for core devices in digital circuits and 2.5 V for I/O devices for analog circuits on a 90nm CMOS). Such implementation not only increases extra power consumption but also limits the I/O supply voltage re-duction in the near future. To improve this issue, using core devices to implement these analog circuits is necessary. Another way is to reduce the usage of analog circuits. Some system architectures use less analog signal processing but more digital signal process-ing. However, some analog circuits are necessary to link the physical and digital worlds. Analog-to-digital converter (ADC) is one of the most important analog circuits. It sam-ples the analog signal, comes from physical world, and then quantize this analog signal into digital code to be processed by the digital signal processor in the SOC chip.
Gen-erally speaking, ADC can be viewed as an interface between physical analog and virtual digital worlds.
1.2
Motivation
For scaled CMOS technologies, the ADC design is more difficult with the following is-sues: lower supply voltage, lower transistors’ intrinsic gain, severe gate leakage and lower power consumption. Many ADC architectures are proposed for different applications. Flash architecture is a comparator-based design, which can be easily adapted for scaled CMOS technologies. It is very suitable for high speed operation. However, this archi-tecture is limited by its resolution. Higher resolution needs more comparators which dissipates a large amount of power and occupies large die area. In general, its resolution is limited by 6-bit. SAR ADC is another architecture to benefit the CMOS scaling. It uses only one comparator with repeated quantization to implement in one sampling pe-riod. This architecture has a perfect trade-off between resolution and speed. SAR ADC can operates both at 1 Gsample/s to achieve 6-bit resolution and at 100 Msample/s to achieve 10-bit resolution. Different from both above architectures, subranging ADC uses two flash sub-ADCs to make twice quantization. This architecture can achieve higher resolution than flash ADCs and higher sampling rate than SAR architecture. However, for scaled CMOS technologies, its complicated switch matrix becomes the bottleneck to slow down ADC’s speed.
Pipelined ADC is the most common architecture to achieve higher resolution at cer-tain sampling rate. Different from above three comparator-based architectures, it uses operational amplifier (opamp) with feedback configuration to implement the residue am-plifier. For scaled CMOS technologies, the opamp design is difficult to implement with low power consumption and low supply voltage. Another amplifier-based ADC architec-ture is two-step ADC. It uses only one residue amplifier with certain number of compara-tors. However, based on traditional design concept, the opamp needs higher dc gain and feedback compensation, which consumes a large amount of power.
In this thesis, a simple residue amplifier is applied with open-loop single-stage archi-tecture, which is improved by a proposed background calibration technique. The proposed
calibration technique can be applied to most amplifier-based architectures in the back-ground without interrupting ADC normal operation. It also corrects the non-idealities of the residue amplifier: gain error and nonlinearity. To benefit scaled CMOS VLSI, the correction is achieved in the digital domain. Minor circuit changes in the calibrated ADC can be easily implemented on most amplifier-based ADCs. The calibration scheme is robust since its effectiveness does not rely on the input’s amplitude distribution. Except the residue amplifier, the power consumption of the comparator is also reduced by the proposed offset compensation mechanism. All analog circuits are designed with lower accuracy requirement to adapt for scaled CMOS technologies. A 10-bit 100-Msamples/s two-step ADC is fabricated using a 90 nm CMOS technology. The two-step ADC contains one residue amplifier and two flash sub-ADCs, is the best ADC architecture to evaluate both digital calibrated residue amplifier and latch-type comparators with an offset calibra-tion loop. Its measurement results demonstrate the feasibility of the calibracalibra-tion technique and the benefit of low power comparator.
1.3
Organization
The organization of the thesis is described as follow:
Chapter 2 gives an overview of several ADC architectures. For every ADC architec-ture, a brief analysis is given to clarify their features. To realize different ADC archi-tectures can give readers a clear picture to understand the ADC characteristics or design high-performance low-power ADCs.
Chapter 3 examines the prior comparator designs by using traditional methods: aver-aging, interpolation and offset storage. Considering the power consumption of traditional design methods, the offset compensation techniques are then discussed. The proposed low power comparator design and analysis provide a clear picture to show its strength for comparator-based ADC architectures.
In Chapter 4, the features of the calibration technique are discussed firstly. Some nonlinear calibration techniques are then analyzed with brief descriptions. To benefit scaled CMOS VLSI, a digital nonlinear background calibration scheme is proposed and analyzed.
In Chapter 5, the prototyping ADC’s implementation is described, including compara-tor, amplifier and digital calibration processor. The experimental results shows the static and dynamic performances to prove the proposed calibration technique for residue am-plifier, and the offset compensation for comparators is also verified. A brief summary for 10-bit ADC is provided to show the achievement of the proposed two-step ADC.
Overview of the ADCs
2.1
Introduction
A Nyquist-rate ADC samples and digitizes an analog signal by using a combination of comparators, amplifiers, analog switches, and digital circuits. Many factors are consid-ered in choosing an ADC architecture, including sampling rate, resolution, power con-sumption, input loading, chip area, and fabrication technology. Here we consider the fol-lowing ADC architectures: flash ADC, successive-approximation register (SAR) ADC, subranging ADC, two-step ADC and pipelined ADC. In general, according to the key elements usage, these ADCs can be distinguished into two groups: comparator-based or amplifier-based, as shown in Figure 2.1. Flash ADCs, SAR ADCs and subranging ADCs are belong to the group of comparator-based ADCs. Pipelined ADC and two-step ADC are in the group of amplifier-based ADCs. Since the choice of the ADC architecture is highly dependent on the application fields, the understanding of the ADCs is a fun-damental necessity. Actually, in recent years, more and more designs use two or more architectures to be a hybrid ADC architecture. The more you can know about ADCs, the better ADC architecture you can determine to achieve the target specification.
In recent years, many techniques were proposed to reduce the power dissipation of these ADCs. Some of them are based on the power reduction of the fundamental ele-ments, which is called the ’element-based’ power reduction technique. These techniques, such as opamp-sharing and switched-opamp, modify the analog circuits to reduce their
Amplifier−based
Comparator−based
Subranging
Flash
SAR
Two−step
Pipeline
power consumption. Using these techniques can reduce the power consumption of the analog circuits, but the ADCs still need good enough opamps to achieve certain perfor-mance. Different from the ’element-based’ technique, some designs develop the calibra-tion mechanism, which is called the ’calibracalibra-tion-based’ power reduccalibra-tion technique, to maintain the ADC’s performance. Most of them uses digital calibration techniques to improve the power efficiency and relax the analog circuits.
Except the power dissipation, the design robustness is another important factor to evaluate the strength of ADC architectures. In SOC chips, to lower down their power consumption, the analog circuits must use the same type of transistors and same supply voltage as digital circuits. Therefore, the design robustness can be defined as whether the ADC architecture is sensitive to process migration or not?
To evaluate ADC’s performance, a generic FOM is defined as follow,
FOM= Power
min(Fs,2ERBW) × 2ENOBDC
(2.1)
where Fs is the ADC’s sampling frequency, ERBW is the ADC’s effective resolution
bandwidth, and ENOBDC is the ADC’s effective number of bits at low input frequency.
For every ADC architectures, their FOM represents the strength and weakness. This can help us to think about what kind of ADC architectures you can use or develope to achieve the target specification.
In this chapter, the track-and-hold (T/H) circuits are firstly discussed in Section 2.2. For most ADCs, the T/H circuit is necessary to process analog input signals. Section 2.3 describes the high-speed flash ADC architecture. The most energy-efficient SAR ADC architecture is discussed in Section 2.4. With scaled CMOS technologies, the SAR ADC can operate at faster speed with ultra low power consumption. Section 2.5 describes the subranging ADC which can extend comparator-based ADCs to achieve 10-bit or higher resolution with medium operating speed. Section 2.6 shows the two-step ADC archi-tecture to improve the speed bottleneck of the subranging archiarchi-tecture. The most pop-ular architecture for medium-to-high resolution is the pipelined ADC architecture. The pipelined architecture which provides good performance for resolution and speed is de-scribed in Section 2.7. Section 2.8 draws the summary.
2.2
Track-and-Hold Amplifier
The track-and-hold (T/H) circuit is the key element for A/D conversion. Actually, the T/H determines overall ADC accuracy since the analog input signal and all perturbations are mixed as the input of the ADC. In general, the ADC can not distinguish original input signal from the output of the T/H circuit.
Figure 2.2 shows three fundamental architectures to implement the T/H function in single-ended configuration. The simplest one, shown in Figure 2.2 (a), using a sampling switch S1 and a hold capacitor CSto implement. The clock signal φ1 controls the switch
S1 to build the connection between input and output signals. At the hold phase (φ1=0),
the input signal is stored in the capacitor CS. The capacitance of CS is determined by
either the thermal noise or the matching accuracy for resolution requirement. This T/H can operate at very fast speed, which is limited by on-resistance of the switch. The RC time constant must be small enough to meet operating speed and resolution requirement. With zero static power consumption, this configuration is popular for high-speed flash ADC architectures. However, at the hold phase, the hold signal can be affected by other disturbances to reduce its accuracy because it is a high-impedance node. The capacitor
CS may needs larger capacitance to suppress these disturbances, but it also slows down
T/H’s operating speed.
To improve this issue, an analog buffer is added to the switched-capacitor configura-tion. Figure 2.2 (b) shows a source-follower based T/H. The source follower provides better buffer capability to reduce the disturbances, but it also consumes certain amount of power. The buffer capability is proportional to its power consumption. The source-follower has several issues.
First issue is the linearity. For nanometer CMOS technologies, the supply voltage is lower down to around 1 V. It makes the source-follower to operate at low supply voltage with transistors which have severe channel length modulation effect. The current source is sensitive to the output signal range and not easy to keep constant. The current variation attenuates the output signal which is input-dependent. That causes the severe non-linearity at the output signal. Another cause of non-linearity is the threshold voltage Vthwith
Vi 1 Vih CS
φ
1 Vi 1 Vih CSφ
1 1a 1 CS 1 2 Viφ
1φ
2φ
1a Via Vis hold track hold track track hold I (a) S1 (c) (b) S1 S1 S2 S3 S4 OpAmp M1 virtually connected VSS VSS VSS VDDFigure 2.2: Simplified T/H configurations: (a) switched-capacitor, (b) source-follower and (c) flip-around.
with replica-bias control to virtually connect the source and bulk terminals.
The second issue is the level-shift problem. In general, the level-shift at the gate and source nodes of transistor M1 is necessary. It is the summation of the threshold voltage of M1 and the gate-overdrive voltage, Vov. Depending on the supply voltage, over-drive
voltage Vovis designed between several tens mV and several hundreds mV. At low supply
voltage, the level-shift will deteriorate the linearity of a source follower. To avoid this, the zero-Vth transistors can be applied for the transistor M1. However, it induces more
production cost due to extra masks usage. Using zero-Vthtransistor, the gate leakage issue
must be carefully considered. In general, the source follower is applied for the ADCs with lower resolution (≤ 10-bit). Actually, low supply voltage highly affects the source-follower operation.
To improve these issues from the source-follower, the flip-around track-and-hold am-plifier (FA-THA) was proposed, shown in Figure 2.2 (c). This architecture is usually applied for high-speed applications [2]. During the track phase (φ1=1), the input signal
is sampled onto the the capacitor CS. The operation amplifier (opamp) is at reset mode
by switches S2 and S4. During the hold phase (φ2=1), the capacitor CS is connected to
the opamp’s output node to act as a feedback capacitor by switch S3. The early clock φ1a
is applied to doing the bottom-plate sampling. By the close-loop configuration, the hold input signal can be represented at the output node of the opamp. The FA-THA shows per-fect performance until facing to the nanometer CMOS technologies. Other opamp-based THA were also proposed to provide good performance, such as charge-transferred THA [3], charge-redistribution THA [4] and pre-charged THA [5]. These opamp-based THAs usually dissipates large power, which is about one third power consumption of the ADC or more. Therefore, for low power application, the opamp-based THA may not become a good choice for ADCs. In recent years, many low power ADC designs use only switch-capacitor configuration, as shown in Figure 2.2 (a), to implement the T/H function with some circuit modifications.
VRB VRT Dout Vin Cs
φ
1 2N −1 D( ) 2N −2 2 N−1 ( ) − to − N D(1) N D( ) buffer Encoder Input sampler2.3
Flash Architecture
Flash ADC, shown in Figure 2.3, is the most commonly known architecture to be used for very high speed and low resolution applications. It contains an input sampler, a resistor ladder, a comparator array and an encoder. At the sampling phase (φ1 = 1), the input
signal is sampled onto the capacitor, Cs. At the comparison phase (φ1 = 0), all of the
comparators make comparisons with their individual slice levels to achieve high-speed operation. If the input signal is larger than its slice level, the output of the comparator is ’1’. If the input signal is smaller than its slice level, the output of the comparator is ’0’. Output data of the comparator array performs as a thermometer code. The digital output, Dout, is obtained by encoding this thermometer code in the encoder. These slice
levels are provided by a resistor string, which is connected to the top and bottom reference voltages, VRTand VRB respectively. The difference between VRT and VRBdefines the input
dynamic range of the ADC. For N-bit resolution, there are at least (2N −1) comparators
used to construct the overall quantization range. If the resolution is higher, the power consumption of the flash ADC will grow up dramatically.
For a high-speed flash ADC, the linearity is dominated by the input sampler, the re-sistor ladder and the comparators. Due to lower resolution requirement, in general, the linearity of the input sampler and the resistor ladder can be easily maintained. There-fore, the comparators determine the overall ADC linearity. Figure 2.4 shows a simplified general comparator design. It contains a pre-amplifier, a regenerative latch and digital circuits. The pre-amplifier is applied to reducing large input offset of the latch by its gain. If the amplifier’s gain is enough to suppress the latch’s offset, the equivalent input offset voltage is only dominated by the pre-amplifier. The output signals, Dpand Dn, are
digital-like analog signals to represent whether the input signal Vinis larger than reference voltage
VR[k] for the k-th comparator or not. If Vin is larger than VR[k], the comparator output
DO[k] is ’1’; otherwise, DO[k] is ’0’. There are two characteristics of the comparator
nec-essary to be considered: one is the input offset voltage and the other is the metastability. Both of them produce ’Bubbles’ in the thermometer code. These Bubbles will introduce wrong result at the encoder output to degrade the overall ADC performance.
reference-Vp Vn Dp Dn Do VR Vin Do [k]
Regenerative Latch Digital circuits Pre−amplifier [k] [k] VSS VSS VDD
Figure 2.4: A general comparator design.
related transistors, resistors or capacitors (if they are used in the comparators). The mis-match is mainly due to the imperfect manufacture in the semiconductor process and tem-perature variation during the operation. With the input offset voltage VOS, the equivalent
k-th reference voltage can be expressed as VR,eq[k],
VR,eq[k] = VR[k]+ VOS (2.2)
The above equation shows that the input offset voltage is necessary to be removed to maintain the original reference level for each comparator. To lower down the equivalent input offset voltage, these mismatch must be reduced by enlarging the size of the transis-tors in the pre-amplifier. However, using larger transistransis-tors usually results in large power dissipation. For a flash ADC, at the architecture level, there are several techniques pro-posed to mitigate the effect of comparator’s input offset voltage. These techniques include spatial averaging [6, 7], interpolation [8, 9], offset storage [10, 11], calibrated redundancy [12, 13], fault-tolerant encoding [14], feedback compensation [15, 16], and so on.
Metastability, an unwanted output state for the latch in the comparator, occurs while the input signal is very close to the reference level. If metastability happened, the out-put of the comparator is decided by the threshold level of the digital circuits. In general, metastability is caused by less driving current at the output nodes or short comparison time. It means larger power consumption is necessary to avoid this issue at certain sam-pling period. If comparators are applied to very high-speed flash ADC, the metastability issue must be carefully considered because the metastability condition usually does not happen in the design stage. In general, post-layout simulation can provide real condition
Table 2.1: Prior flash ADCs
Design Process Supply Resolution Speed ENOB Power FOM (/conv.-step)
[17] 90 nm 1.0 V 8-bit 1.25-GS/s 7-bit 207 mW 1.3 pJ
[18] 90 nm 0.9 V 6-bit 3.5-GS/s 5.3-bit 98 mW 0.95 pJ
[19] 90 nm 1.0 V 5-bit 1.75-GS/s 4.8-bit 7.6 mW 0.15 pJ
[20] 65 nm 1.2 V 6-bit 800-MS/s 5.63-bit 12 mW 0.3 pJ
due to the routing capacitance.
The input capacitance of the comparator is another issue for higher resolution flash ADCs. To reduce the input capacitance of the comparator array, a dedicated input sam-pler is usually built before the comparator array. The buffer is implemented by source follower circuits to maintain the buffering. For the high-speed A/D conversion, the input sampler can also improve the spurs-free dynamic range (SFDR). For over-GS/s operation, flash ADC architecture is the best choice to achieve the quantization for lower resolution applications (< 8-bit).
Table 2.1 presents several flash ADC designs. [17] and [18] use traditional design concept by using multi-stage pre-amplifiers to reduce the input offset of the comparator. Their FOMs are still around 1 pJ/conv.-step. On the other hand, [19] and [20] uses their offset-calibrated comparators to construct the flash ADCs. Their FOMs can be greatly improved to 0.15 and 0.3 pJ/conv.-step respectively. This result demonstrates the benefit of using offset-calibrated comparators to construct the flash ADCs.
2.4
Successive-Approximation Architecture
SAR ADC is contrast to the flash architecture, using only one comparator with N-times quantization to achieve N-bit resolution. The offset voltage of the comparator is not im-portant since it does not affect the conversion accuracy, only the offset of the overall SAR ADC. In general, the dedicated input sampler is necessary to maintain its operation. If the sampling time is equal to one quantization cycle time, the conversion time of the SAR ADC needs at least N+1 quantization cycles. It means the quantization cycle time must be (N+1)-times faster than the flash architecture to achieve the same Nyquist frequency.
Vda Vin VRB VRT b3 b2 b1 b0 VRT VRB Dout Vda Vin SHA Control Logic DAC CLK 4 1 2 3 4 = 1 = = = 0 1 0 1/2 3/4 5/8 7/16 k
Figure 2.5: A 4-bit SAR ADC and its quantization sequence.
ADC uses binary search for the possible sub-regions. The speed bottleneck is the DAC with precision on the order of the converter itself. The DAC is constructed with a resistor ladder with switches to select the reference voltage closest to the input signal. For higher resolution (> 8-bit), large amount of switches will limit the operating speed due to the wire loading capacitance at the node voltage, Vda, shown in Figure 2.5. Moreover, power
consumption of the dedicated input sampler (SHA) will dominate the overall power dis-sipation of the SAR ADC. To avoid the above two issues, the DAC can be designed with the capacitors to do the subtraction based on the charge redistribution mechanism. How-ever, the design consideration of the capacitors matching is necessary to maintain better performance.
The matching issue will increase the total input capacitance, which means the increas-ing of the input drivincreas-ing power. In recent years, several techniques are proposed to improve the ADC performance. Segmented capacitor array can reduce the necessary input capaci-tance to lower the input driving power. Redundancy quantization cycles [21] can relax the DAC settling time. Furthermore, asynchronous clocking [22] can reduce the overall quan-tization time to speed up the conversion rate of the SAR ADCs. Generally speaking, the SAR architecture shows an excellent trade-off between accuracy and speed for low-power
Table 2.2: Prior SAR ADCs
Design Process Supply Resolution Speed ENOB Power FOM (/conv.-step)
[23] 90 nm 1.0 V 7-bit 150-MS/s 6.5-bit 133 µW 10 fJ
[24] 90 nm 1.0 V 9-bit 40-MS/s 8.6-bit 820 µW 54 fJ
[21] 65 nm 1.2 V 10-bit 100-MS/s 9.5-bit 1.13 mW 15.5 fJ
[25] 130 nm 1.2 V 12-bit 45-MS/s 11-bit 3.0 mW 31.4 fJ
application to achieve low-to-medium resolution ADCs.
Table 2.2 presents several SAR ADC designs with ultra-low FOMs. Benefit from CMOS scaling, SAR ADCs achieve incredible performance on power consumption. [23] shows the advantages of SAR ADC architecture with amazing FOM, 10 fJ/conv.-step. [24] gives us the possibility that SAR ADC can achieve 9-bit or higher resolution by using only comparators, without residue amplification. In 2010, two SAR ADC designs [21] and [25] can achieve 10-bit 100-MS/s and 12-bit 45-MS/s performance respectively. This implies that SAR ADC may extend its application to higher resolution (> 10-bit) ADCs with sampling rate of around one hundred MS/s.
2.5
Subranging Architecture
Subranging ADC can be viewed as a trade-off between flash and SAR architectures. By quantizing the analog input signal into two steps, compared with the flash ADC, the num-ber of comparators can be reduced significantly. For N-bit resolution, this ADC only needs (2N/2+1−2) comparators. Therefore, this architecture is usually applied to achieving 8-bit
or higher resolution. A general 10-bit subranging ADC architecture and its quantization curves is shown in Figure 2.6. The subranging ADC quantized the input signal by two steps: coarse quantization and fine quantization. In general, a dedicated input sampler (SHA) is applied to maintaining the operation. The subranging ADC has a 5-bit coarse ADC consisting of 31 comparators and a 6-bit fine ADC consisting of 63 comparators. Coarse ADC makes the first quantization to yield coarse code, D1. It then drives a MUX to
select reference voltages which are close to the input for fine ADC. Fine ADC makes the second quantization to yield D2code, which is the exact magnitude of the input. Finally,
VRC VRT VRB D2 VRF D1 Dout Vin V1 D1 D2 D1 D1 D1 D1 D1 ADC Coarse ADC Fine MUX 63 =0 =1 =2 =3 =4 31 6 1023 SHA Encoder 5 10 levels fine coarse levels
Table 2.3: Prior subranging ADCs
Design Process Supply Resolution Speed ENOB Power FOM (/conv.-step)
[16] 90 nm 1.2 V 6-bit 1-GS/s 5.3-bit 55 mW 1.4 pJ
[26] 90 nm 1.0 V 10-bit 160-MS/s 9.2-bit 84 mW 0.89 pJ
[27] 90 nm 1.2/2.5 V 8-bit 300-MS/s 7.2-bit 34 mW 0.68 pJ
[28] 90 nm 1.2 V 8-bit 770-MS/s 9.3-bit 70 mW 0.94 pJ
Extra one-bit is designed for the fine ADC. These extra comparators can be used to relax the accuracy requirement of the coarse ADC. With the over-range protection, coarse ADC only need 5-bit accuracy, not 10-bit. There are two issues for the subranging ADC. One is that the comparators in the fine ADC still need 10-bit resolution, which is equal to the overall ADC accuracy. Such comparators are power-hungry circuits. The other is that the critical delay path is the MUX that has to select 63 reference voltages out of 1023 possible voltages generated by the resistor string. The MUX is constructed by the switches, which are made by MOS transistors. For nanoscaled CMOS technologies, the MOS switches usually have larger on-resistances if the bootstrapping techniques are not applied. Higher resolution also causes more complicated wire routing for these reference voltages. It results in larger parasitic capacitance at the references of the fine ADC. Both large parasitic capacitance and on-resistance increase the settling time of the reference voltages, which determine the overall ADC accuracy.
Due to the bottleneck of the MUX and high resolution comparator in fine ADC, sub-ranging ADC has obvious trade-off between resolution and sampling rate. In recent years, the resolution of subranging ADC is limited by 10-bit. Table 2.3 presents several sub-ranging ADC designs from 2006 to 2009. Due to CMOS scaling, the sampling rate can speed up to 1 GS/s, for 6-bit resolution. These FOMs are between 0.68 and 1.4 pJ/conv.-step. However, from these measurement results, subranging ADCs have certain trade-off between resolution and operation speed since the FOM differences are not large. In gen-eral, the subranging architecture is applied for several hurdreds MS/s sampling rate and medium resolution of 8-to-10 bits.
VRC VRT VRB D2 VRF V2 Vda D1 Vin V1 V1 D2 D1 V2 Dout A ADC Coarse MUX ADC Fine levles fine coarse levles 31 32 6 63 Residue Amplifier Encoder 5 10 SHA
2.6
Two-step Architecture
To relax the fine ADC and simplify the MUX in the subranging ADC, two-step ADC architecture was proposed over twenty years. Similar to subranging ADC, this architec-ture uses two quantization steps. Figure 2.7 shows a 10-bit two-step ADC architecarchitec-ture and its quantization curves. It still has a 5-bit coarse ADC and a 6-bit fine ADC with one-bit over-range protection. Different from the subranging ADC, this ADC only needs the MUX to select one reference output out of 32 possible voltages to generate the input estimation, Vda. The reference voltages of fine ADC are fixed, not selected by a complex
MUX. This architecture requires a residue amplifier that amplifies the difference between the hold input V1and the MUX output Vda.
Actually, two-step ADC can be viewed as a hybrid architecture of comparator-based and amplifier-based architectures. In this example, there are 31 comparators in the coarse ADC and 63 comparators in the fine ADC. The required comparator’s resolution in the fine ADC is relaxed by the amplifier’s gain, shown in Figure 2.7. However, for this 10-bit two-step ADC, the residue amplifier still dissipates a large amount of power to achieve accurate gain and linearity. For scaled CMOS technologies, it is not easy to implement high-precision amplifier with low power consumption.
Table 2.4 presents several two-step ADC designs from 2001 to 2009. By traditional design concept, the two-step ADC can achieve 12-bit resolution and several tens MS/s sampling rate, but it still consumes a large amount of power [29]. Considering the design difficulty of a high accurate residue amplifier, there seems to have a bottleneck for two-step ADC design. Until 2009, [30] presents a 6-bit 1-GS/s ADC to achieve the FOM of 1.24 pJ/conv.-step. Different from traditional design concepts, [31] shows a better FOM by using digital calibration technique for residue amplifier and offset-calibrated comparators for coarse and fine ADCs. With these calibration techniques, two-step ADC can be a good candidate for low-power and high-speed application to get a good FOM, not larger than 100 fJ/conv.-step.
Table 2.4: Prior two-step ADCs
Design Process Supply Resolution Speed ENOB Power FOM (/conv.-step)
[29] 250 nm 2.5 V 12-bit 54-MS/s 10.3-bit 295 mW 4.9 pJ [30] 130 nm 1.2 V 6-bit 1-GS/s 5.3-bit 49 mW 1.24 pJ [31] 90 nm 1.0 V 10-bit 100-MS/s 9.32-bit 6 mW 0.092 pJ
D1
Dj
DN
Vin
Dout
Vj
Dj
Vj+1
Vj
Dj
Stage 1
Stage j
Stage N
SHA
( )
da
Digital Encoder
+
x2
sub−
ADC
sub−
DAC
−
2.7
Pipelined Architecture
Pipelined ADC is a typical amplifier-based ADC architecture using several amplifiers to do residue amplifications. Different from the subranging ADC, shown in Figure 2.1, it is another trade-off between flash and SAR architectures with amplifier-based architecture. Figure 2.8 shows a conceptual N-bit pipelined ADC architecture with 1-bit/stage config-uration. It consists of N stages, each including a SHA, a sub-ADC, a sub-DAC, and an amplifier with gain of 2. The basic operation is similar to the two-step architecture. The first stage samples the analog input signal. The sub-ADC quantizes the hold input to yield the digital output D1. D1 drives the sub-DAC to generate the estimated input, Vjda(Dj).
The estimated input is subtracted from the hold input to generate the residue signal. It is then amplified to the next stage sampling. All stages are operated under two clock phases, sampling and amplification. All digital outputs are collected by the digital encoder with sequentially half clock delay to generate the final digital output, Dout.
Because the SHA is existed in each stage, after the amplification phase, the first stage can start sampling a new analog input signal while second stage processes the previous sample. All stages have the same operation process as the first stage, as the above de-scribed, to achieve the so-called pipelined architecture. For example, the first stage is k-th sampling and the second stage is (k-1)-th amplification; the third stage is (k-1)-th sampling and the forth stage is (k-2)-th amplification, et al. It means the operating speed of the pipelined ADC is determined by the operating speed of its first stage. The sim-plest architecture is the configuration of 1-bit per stage. Its transfer curve is shown in Figure 2.9(a). The sub-ADC consists of one comparator to decide the output Dj is 0 or
1. The 1-bit sub-DAC generates output of VR or −VR if Dj is 0 or 1 respectively. This
simplest configuration can not deal with the comparator’s offset. For the example shown in Figure 2.9(a), if the comparator has the offset of VR/8, the digital output will have
missing code due to the saturation of the transfer curve.
To solve this issue, the most common configuration is 1.5-bit per stage, as shown in Figure 2.9(b). The sub-ADC consists of two comparators with their slice levels of −VR/4 and VR/4, respectively. The amplified residue signal is typically in the range of
Vj
−VR
VR
Vj+1
Vj
VR
Vj+1
−VR
VR
VR
−VR
VR
−VR
VR
2
2
−
(a)
0
sub−ADC’s offset
(b)
0
sub−ADC’s offset
missing
code
corrected
range of {−VR, VR} which is available to processed by the next stage. With the
redun-dancy of comparators, the comparator’s offset requirement is relaxed. Actually the re-served output range tolerates the inaccuracy of sub-ADC, sub-DAC and the non-idealities of the opamp. It is the most popular architecture to achieve over 10-bit resolution ADCs with sampling frequency range from several tens MS/s to several hundreds MS/s.
Except the configuration of 1.5-bit per stage, multi-bit per stage configurations are also popular. The configurations of 2.5-bit per stage and 3.5-bit per stage are commonly used to reduce overall ADC power consumption. For such multi-bit configurations, the accuracy requirement of comparators is higher than that of 1.5-bit configuration. With the pipelined operation, this architecture makes an excellent optimization among power, speed and accuracy specifications.
The drawback of the pipelined architecture is the longer latency. Moreover, for ad-vanced CMOS technologies, the opamp implementation becomes a severe issue. The amplifier-based ADC architectures always face the issues for lower supply voltage (< 1.2 V) and lower intrinsic gain of the MOS transistors. Low supply voltage limits the input dynamic range of the ADC and makes the amplifier difficult to implement for high-resolution. Lower intrinsic gain makes the amplifier architectures more complex to maintain certain performance, but larger power consumption. Actually, for a complicated opamp circuit, extra power dissipation is wasted on the circuit stability, not the operating speed.
To solve both issues, many digital calibration techniques are proposed to improve the power dissipation of the pipelined ADCs. Linear calibration techniques can solve the gain error due to capacitor mismatch and the sub-DAC errors, but opamp still needs enough gain. To mitigate opamp’s gain requirement, nonlinear calibration techniques are pro-posed to improve the non-idealities, generated by opamp circuitry. To sum up, pipelined architecture is very popular to implement ADCs with various resolution (between 6 and 16 bits) and wider range of operation speed (between several MS/s to several GS/s).
Table 2.5 presents several pipelined ADC designs in recent two years. For higher resolution [32, 33] or higher sampling rate designs [34], their FOMs are between 0.3 and 0.5 pJ/conv.-step. In general, most higher resolution ADCs are noise-limited, but not matching-limited. Their power consumption will greatly increase due to larger
sam-Table 2.5: Prior pipelined ADCs
Design Process Supply Resolution Speed ENOB Power FOM (/conv.-step)
[34] 90 nm 1.2 V 10-bit 500-MS/s 8.5-bit 55 mW 300 fJ
[32] 90 nm 1.2 V 14-bit 100-MS/s 11.2-bit 130 mW 520 fJ
[33] 180 nm 1.8 V 16-bit 125-MS/s 12.8-bit 385 mW 432 fJ
[35] 90 nm 1.2 V 12-bit 50-MS/s 10-bit 4.5 mW 88 fJ
[36] 90 nm 1.0 V 10-bit 100-MS/s 8.9-bit 4.5 mW 98 fJ
pling capacitances. Actually, for 10 and 12-bit pipelined ADCs, their FOMs can be lower than 100 fJ/conv.-step. [35] presents a low power pipelined ADC by using zero-crossing based amplifiers in the pipelined stages to replace traditional opamps. [36] shows a 10-bit pipelined ADC with time sharing technique to reduce the overall ADC power consump-tion.
2.8
Summary
Several ADC architectures are illustrated in this chapter, except sigma-delta ADC and time-interleaved ADC architectures. Two categories are applied for these ADCs: comparator-based and amplifier-comparator-based architectures.
Comparator-based ADCs are insensitive to CMOS scaling and benefit faster operation speed. Generally speaking, flash ADC architecture is used to achieve high-speed appli-cation (over GS/s). However, it is also the most power consuming architecture and not suitable for higher resolution (> 8 bits). Subranging ADC is a good choice to meet higher resolution requirement (between 8 and 12 bits) with lower power consumption. But its operation speed is still limited by the complicated MUX (several hundreds MS/s). In recent years, SAR architecture is popular to implement medium and high speed ADCs. It is more energy-efficient than other ADC architectures. Its resolution is between 6 and 12 bits with the sampling rate from several tens MS/s to several GS/s. Moreover, small occupied area is another advantage for SAR ADCs. But, multiple quantization steps slow down the overall operating speed if higher resolution.
Different from comparator-based ADCs, amplifier-based ADCs benefit higher resolu-tion. Pipelined architecture is the most common architecture for ADCs, between 8 and
16 bits resolution. This architecture provides the best trade-off between resolution and speed. Amplifiers’ power dissipation dominants the overall ADC power consumption. Another amplifier-based architecture is two-step ADC, which can be viewed as a spe-cialized pipelined architecture. Different from pipelined ADC architecture, it only need one amplifier with lower output accuracy and more comparators in coarse and fine ADCs. In general, two-step ADCs have both amplifier and comparators with almost equivalent importance. Actually, two-step ADC architectures do not have the resolution limitation since the residue signal is amplified for next quantization stage. For higher resolution ADCs, the power consumption is noise-limited. However, for amplifier-based architec-tures, low supply voltage and low intrinsic gain of transistors are two issues for CMOS scaling, briefly illustrated in Appendix D.1.
For scaled CMOS technologies, except low supply voltage and low intrinsic gain of transistors, the gate leakage is another severe issue to affect ADC performance. Gate leakage deteriorates the droop rate of MOS transistors, used as hold capacitors or charge redistribution mechanism. It should be noted that the gate leakage issue must be carefully considered at the design stage. Gate leakage issue is discussed in Appendix D.2.
Figure 2.10 summaries the various ADC limitation boundaries between resolution and sampling frequency. We may find that pipelined ADC architectures have widest range, compared with other ADCs. Flash ADCs have the advantage at very high-speed oper-ation, but limited by the resolution. Subranging and two-step ADCs have their benefits at medium resolution and medium operation speed. SAR ADCs have lower boundary compared with other ADCs, but actually benefit the smaller area and ultra low power consumption. However, with digital calibration techniques, these boundaries will become indefinite.
Figure 2.11 summaries the ADCs published on the ISSCC and VLSI from 1997 to 2010 [37]. In 2010 ISSCC, for 10-bit ADCs, their figure-of-merit (FOM) are less than 100 fJ/conv.-step. Most of them are SAR ADCs using the scaled CMOS technologies to achieve 10-bit resolution and several tens MS/s sampling rate. Actually, SAR ADC can almost reach the FOM of 10 fJ/conv.-step.
Resolution (bits)
6
8
10
12
14
16
Subranging &
Two−step ADCs
10M
100M
1G
10G
1M
Sampling Frequency (Hz)
SAR ADCs
Pipelined ADCs
Flash ADCs
Comparator with O
ffset Compensation
3.1
Introduction
On the demand of advanced nanoscale CMOS technologies, analog circuits are more and more difficult to achieve the required performance by using traditional design concepts. Among most analog circuits, comparator is the best one to against the CMOS scaling. Ac-tually, analog comparator behaves like a digital circuit to provide fast operating speed. For a comparator-based ADC, it can benefit the advantage of advanced CMOS technologies.
In this chapter, the traditional design concepts and techniques are discussed in Sec-tion 3.2. Different from traditional designs, the feedback compensation mechanism is applied to reducing the equivalent input offset voltage of the comparators. Section 3.3 shows some feedback compensation schemes to cancel the comparator’s input offset to achieve low power consumption. With the feedback compensation mechanism, a low power comparator design is proposed in Section 3.4. Finally, Section 3.5 summarizes these comparator design techniques.
3.2
Traditional Comparator Design
In general, the comparator consists of a pre-amplifier and a regenerative latch, as shown in Figure 3.1(a). The pre-amplifier is usually applied before the latch to reduce the latch’s offset by the amplifier’s gain, which is defined as A. Here the latch’s and pre-amplifier’s
offset voltages are defined as VOS,L and VOS,P respectively. The overall input referred
offset voltage of the comparator, VOS.
VOS = VOS,P +
VOS,L
A (3.1)
If single amplifier’s gain is not enough, several amplifiers are usually serial-connected to provide enough gain to reduce the overall input offset voltage for the comparator Fig-ure 3.1(b). VOS = VOS,P1+ VOS,P2 A1 + VOS,P3 A1× A2 + VOS,L A1× A2× A3 (3.2)
Figure 3.1(c) ans (d) shows a general pre-amplifier and a regenerative latch schematics. With the pre-amplifier’s gain attenuation, the latch’s input offset is greatly reduced. Ac-cording to Equation (3.1), only the pre-amplifier’s offset dominates the overall input offset voltage of the comparator.
For the offset of a source-couple pair in the pre-amplifier, the standard deviation of the input offset voltage, VOS,P, is defined as
σ2(VOS,P)= σ2(∆Vt)+ (
Vov
2 )
2× σ2(∆β)
β2 (3.3)
where ∆Vt is the threshold voltage difference between two input transistors, Vov is the
gate over-drive voltage of M1 and M2, and ∆β is the β difference between two input transistors. With the following equations,
β = µCox W L (3.4) σ2(∆Vt)= A2V t W · L (3.5) σ2(∆β) β2 = A2β W · L (3.6)
the input offset voltage, VOS,P, can be rewritten as
σ2(VOS,P) = 1 W · L(A 2 Vt+ Vov2 4 · A 2 β) (3.7)
where W and L are the width and length of the input transistors M1 and M2, A2V
t and A
2
β
A1 A2 A3 Do VR Vi Vi VR Do Vi VR V1n V1p V1p V1n Do (a) Single Pre−amplifier (b) Multiple Pre−amplifiers
A (d) Latch schematic (c) Pre−amplifier schematic R R ck ck ckb M1 M2 VDD VDD VSS VSS VDD
of pre-amplifier is reduced by using larger transistor’s size and smaller gate-overdrive voltage for its input differential pair.
Considering a general pre-amplifier circuit, some key performance indices are defined as follow. Speed ∝ gm CGS ≈ 2I/Vov (2/3) · W L · Cox (3.8) P ower ∝ I · VDD (3.9) Accuracy2 ∝ V 2 DD σ2(V OS) ≈ W L · V 2 DD A2V t + Vov2 4 · A 2 β (3.10) Actually, these indices can not be optimized for all of them, but some tradeoffs may be existed among them. Here a relationship between speed, power and accuracy [38] is defined to describe the tradeoff,
Speed × Accuracy2 P ower ∝ 1 Cox·(A2Vt+ Vov2 4 · A 2 β) × VDD Vov (3.11)
If the gate-overdrive voltage Vov is proportional to the supply voltage VDD and Aβ is
smaller enough, this relationship can be represented as
Speed × Accuracy2 P ower ∝
1
Cox· A2Vt
(3.12) With above assumption, Equation (3.12) figures out a physical limitation: the relationship is process-dependent only. This result shows that for thinner process (Cox is larger), the
tradeoff is smaller. It means the advanced nanoscale CMOS processes actually degrade the performance of analog circuits. Since the tradeoff is constant for same process, the speed or accuracy improvements will suffer the penalty of larger power dissipation. For example, more one-bit accuracy will induce four-times power consumption.
Although Equation (3.12) is made by some assumptions [38], it may not describe the scaled CMOS transistors precisely. This approximation equation can still provide a qualitative trend. To break the tradeoff degradation trend, several innovative techniques, mentioned in Section 2.3, were proposed to reduce the equivalent input offset of the com-parator and achieve low power consumption. Some of them, including spatial averaging [6, 7], interpolation [8, 9] and offset storage [10, 11], are commonly applied to the flash ADCs. Here the qualitative analysis is described in the following section.
3.2.1
Spatial Averaging Technique
Spatial averaging technique improves the overall linearity of the ADC by averaging the error of an individual pre-amplifier with several adjacent pre-amplifiers. Figure 3.2 shows the averaging technique with resistor connections and its effect to improve ADC’s linear-ity. There are three transfer curves shown in Figure 3.2. The black ’dash-dot’ line is the ideal transfer curve for the comparator array without any offset. The green ’dash’ line and blue ’solid’ line represent real transfer curves before and after using spatial averag-ing technique respectively. With the resistors connected to its adjacent comparators, the equivalent input offset voltage is suppressed by the averaging mechanism.
The individual comparator offset can be treated as a random number and independent on others. This averaging mechanism uses resistor connection to perform the moving average function, by analog way. For each comparator, the moving average produces a spatial low-pass filter to suppress its large deviation by relating to adjacent comparators. The ratio, R1/R0, determines the degree of the offset reduction. Generally speaking, if
the ratio is lower, the offset reduction is more. This is because of such ’analog’ type moving average is constructed by the resistance, connected to other comparators. If the connecting resistor R1 is too large, the averaging path is weak to act as a real moving
average. The averaging technique can easily reduce the differential non-linearity (DNL), but has less reduction for the integral non-linearity (INL). Figure 3.3 shows the DNL and INL improvements with respect to the ratio, R1/R0. The DNL and INL reduction
factors are defined as RDNL and RINL respectively. Wn is defined as the number of the
adjacent comparators which have significant influence. The detail analysis can be referred to [39, 40, 7].
By using the resistors to connect output nodes of adjacent pre-amplifiers, the input offset of the individual comparator is averaged to improve the linearity of flash ADC. To perform a good averaging, there are extra comparators necessary in the both ends of the comparator array to provide enough neighbors. But this also increase extra power consumption. To mitigate this redundancy, averaging termination [40] and triple-cross connection [41] techniques were proposed, but they still require extra power and area. Moreover, the equivalent gain of the pre-amplifier is reduced by the resistive network. It
1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R VR VR VR 0 R R0 R0 R0 R0 R0 Vin [k−1] [k] [k+1] digital output input (V) after averaging before averaging VDD VDD VDD VDD VDD VDD VSS VSS VSS
