Arrangement of This Thesis - 金屬閘高介電n型金氧半場效電晶體及鰭式電晶體閘極電子穿隧電流的精確模擬

Chapter 1 Introduction

1.2 Arrangement of This Thesis

First of all, building tunneling current model for n-type FinFET is the main purpose of this thesis. The direct tunneling physical model for oxide dielectric is introduced in the first part of Chapter 2. This part includes four key parameters: the inversion layer charge density, the electron impact frequency on interface, the WKB transmission probability, and the reflection correction factor, as will be explained one by one. Because the gate material of experimental FinFET device usually contains high-K dielectric, modifying the model originally for conventional gate oxide SiO₂ is essential. Modified WKB transmission probability and reflection correction factor both are introduced in the second part of Chapter 2. In order to calculate the electron tunneling probability through the high-K stacks, the electron subband energy is necessary to determine. In the third part of Chapter 2, we employ a simple method to calculate subband energy.

Building the gate current model for FinFET is introduced in Chapter 3. It is divided into three parts. First, because of the device structure change from planar to multiple gate, full depletion situation needs to be considered in the double gate model.

Depletion charge density calculation is introduced in the first part. Next, the devices of two gates induce confinement to the electrons while the body thickness is scaling down. So the structure confinement makes a significant difference in calculated subband energy between planar and multiple gate devices, which will be introduced in

dlnIg/dVg-Vg fitting is important for high-K stacks devices. We can find that it might make an erroneous fitting result if the dlnIg/dVg fitting is not performed.

After the model is constructed, the experimental results about n-type FinFET are shown in Chapter 4. By fitting experimental data, we can extract the process and material parameters of the device. In the beginning, the gate current calculated by analytical model deviates from experimental one. Modified tunneling models are introduced by adding transition layer between the high-K dielectric and interfacial layer. Linear transition layer and parabolic transition layer are the two models adopted in this study. We can also prove that these models are valid for simulating the gate current. The dlnIg/dVg fitting is also done to help determine accurately the gate material parameters related to high-K dielectric. By all fittings and modifications, the analytical model for tunneling current remains valid, especially above threshold of operation. Finally, the conclusion of this thesis is drawn in Chapter 5.

Chapter 2 Physical Model for Planar FET

First, the principle of gate electron direct tunneling in an n⁺poly/SiO2/p-substrate structure will be explained. Then, by substituting high-K for SiO₂ as gate dielectric material, a physical model of electron tunneling across high-K stacks is formed.

2.1 Tunneling Current Model for Oxide Dielectric

The basic band diagram of n⁺poly/SiO₂/p-substrate is shown in Fig. 1. Quantum mechanical calculation for the inversion layer in substrate and modified Wentzel-Kramers-Brillouin (WKB) approximation for the transmission probability across SiO2 layer are employed in this model [2],[3]. The direct tunneling electron current model is made up of four key parameters: the inversion layer charge density, the electron impact frequency on interface, the WKB transmission probability, and specially, the reflection correction factor.

𝐽_𝑔 = 𝑞𝑁_𝑖,𝑗𝑓_𝑗𝑇_𝑊𝐾𝐵𝑇_𝑅 (2-1) where

J

g is the electron tunneling current;

q is the elemental charge;

N

i,j is the inversion layer charge per unit area with jth subband in the ith valley;

f

_j is the electron impact frequency on SiO₂/Si interface;

T

WKB is the WKB transmission probability;

T

_R is the reflection correction factor

A. Inversion Layer Charge (N

i,j

)

Using the density of states for a two-dimensional electron gas (2DEG) and Fermi-Dirac statics, the inversion layer charge density of each energy subband can be derived as

𝑁

_𝑖,𝑗

= �

^𝑘_𝜋ℏ^𝐵^𝑇₂

� 𝑔

_𝑖

𝑚

_𝑑𝑖

𝑙𝑛 �1 + 𝑒𝑥𝑝 �

^𝐸^𝐹_𝑘^−𝐸^𝑖𝑗

𝐵𝑇

��

(2-2) where g_i is the degeneracy of the ith valley; m_di is the density of states electron effective mass in the ith valley and Eij is the energy level of the jth subband in the ith valley.

B. Electron Impact Frequency (f

)

The electron impact frequency can be described as [4]

𝑓

_𝑗

= �2 ∫

₀^𝑧^𝑗_𝜈_𝑆𝑖⊥¹_(𝑥)

𝑑𝑥�

⁻¹ (2-3) where zj epresents the classical turning point in silicon for electrons in each subband and 𝜈_𝑆𝑖⊥the interface-normal group velocity component of electron wave packet, which can be expressed as

𝜈_𝑆𝑖⊥(𝑥) = �^2�𝐸^𝑖𝑗_𝑚^{−𝑞𝑉(𝑥)�}

𝑧,𝑖 (2-4)

m

z,i is the longitudinal or transverse effective mass in two or four fold valleys and V(x) is the potential well which can be approximated as a triangle-like electrostatic potential:

𝑉(𝑥) =

^𝜀^𝑜𝑥_𝜀^𝐹^𝑜𝑥^𝑥

𝑆𝑖 (2-5) Substituting (2-4) and (2-5) into (2-3), then we can obtain the impact frequency 𝑓𝑗 = �2 ∫ _𝜈 ¹

𝑆𝑖⊥(𝑥) 𝑧_𝑗

0 𝑑𝑥�⁻¹ = ^𝑞𝜀^𝑜𝑥_2𝜀^|𝐹^𝑜𝑥^|

𝑆𝑖 �2𝑚𝑧,𝑖𝐸𝑖𝑗�⁻¹² (2-6)

C. WKB Transmission Probability (T

WKB

)

To calculate the tunneling probability across the oxide barrier in Fig. 2, a modified WKB approximation is used. The modified WKB approximation includes T_WKB and

T

R [3],[4]. The former is the usual WKB tunneling probability, effective for smooth potential barriers; the latter is a correction factor for reflections from potential discontinuities. Both are combined in form:

𝑇 = 𝑇

_𝑊𝐾𝐵

𝑇

_𝑅 (2-7)

𝑇

_𝑊𝐾𝐵

= 𝑒𝑥𝑝�−2 ∫ 𝜅(𝑥) 𝑑𝑥

₀^𝑡^𝑜𝑥

�

(2-8)

κ(x) is the magnitude of the carriers imaginary wave vector within the bandgap

between the oxide layer

𝜅(𝑥) = �

^2𝑚^𝑜𝑥^{[𝐸−𝑞𝑉(𝑥)]}_ℏ₂ (2-9) Then substituting (2-9) into (2-8) yields

𝑇_𝑊𝐾𝐵 = 𝑒𝑥𝑝 �−2 �∫ �₀^𝑡^𝑜𝑥 ^2𝑚^𝑜𝑥^{[𝐸−𝑞𝑉(𝑥)]}_ℏ₂ 𝑑𝑥��

= 𝑒𝑥𝑝 �^4�2𝑚^𝑜𝑥^�𝜙^𝑎𝑛

32 −𝜙_{𝑐𝑎𝑡ℎ}³² �

3𝑞ℏ|𝐹_𝑜𝑥| � (2-10) 𝜙𝑐𝑎𝑡ℎ and 𝜙𝑎𝑛 represent the magnitude of the electron (tunneling from the jth subband in the ith valley) energy with reference to oxide conduction band in the channel and in the gate, respectively. They are calculated by

𝑞𝜙

_{𝑐𝑎𝑡ℎ}

= 𝑞𝜙

_𝑜𝑥

− 𝐸

_𝑖𝑗 (2-11) and

𝑞𝜙

_𝑎𝑛

= 𝑞𝜙

_𝑜𝑥

− 𝐸

_𝑖𝑗

− 𝑞𝐹

_𝑜𝑥

𝑡

_𝑜𝑥 (2-12) where 𝜙𝑜𝑥 is the Si-SiO₂ conduction band discontinuity.

The total energy is composed of transverse and longitudinal energies

𝐸 =

^ℏ²^�𝜅_2𝑚^𝑥²^+𝜅^𝑦²^�

𝑡

+ 𝐸

_𝑗 (2-13)

In this equation, m_t means the transverse effective mass and E_j is the energy in longitudinal direction.

D. Reflection Correction Factor (T

)

Reflection factor is related to the type of material the wave penetrates. There are two interfaces in n⁺poly-SiO2-p-substrate structure, Si/SiO2 and SiO2/n⁺poly. So the reflection correction factor is

𝑇

_𝑅

= 𝑇

_𝑅1

𝑇

_𝑅2

=

^4𝜈_𝜈^𝑆𝑖⊥^{(𝐸) × 𝜈}^𝑜𝑥^(𝜙^{𝑐𝑎𝑡ℎ}⁾

𝑆𝑖⊥2 (𝐸)+𝜈_𝑜𝑥² (𝜙_{𝑐𝑎𝑡ℎ})

×

^4𝜈_𝜈^𝑆𝑖⊥^{(𝐸+𝑞|𝐹}^𝑜𝑥^|𝑡^𝑜𝑥^{) × 𝜈}^𝑜𝑥^(𝜙^𝑎𝑛⁾

𝑆𝑖⊥2 (𝐸+𝑞|𝐹_𝑜𝑥|𝑡_𝑜𝑥)+𝜈_𝑜𝑥² (𝜙_𝑎𝑛) (2-14) where T_R1 and T_R2 are the reflection factors at the interface of Si/SiO₂ and SiO₂/n⁺poly,

respectively. 𝜈_𝑆𝑖⊥(𝐸) is the group velocity of electrons incident at the silicon-oxide interface

𝜈

_𝑆𝑖⊥

(𝐸) = �

^2𝐸_𝑚^𝑖𝑗

𝑧 (2-15) 𝜈_𝑜𝑥(𝜙_{𝑐𝑎𝑡ℎ}) is the magnitude of the purely imaginary group velocity of electron at the cathode side of SiO₂

:

𝜈

_𝑜𝑥

(𝜙

_{𝑐𝑎𝑡ℎ}

) =

¹_ℏ^𝑑𝜙_𝑑𝜅^{𝑐𝑎𝑡ℎ}

𝑜𝑥

=

^ℏ_2𝑚²^𝜅^𝑜𝑥²

𝑜𝑥 (2-16) On the other hand, 𝜈_𝑆𝑖⊥(𝐸 + 𝑞|𝐹_𝑜𝑥|𝑡_𝑜𝑥) means the group velocity of electrons leaving the oxide-polygate interface and 𝜈𝑜𝑥(𝜙𝑎𝑛) is the magnitude of the purely imaginary group velocity of electron at the anode side of SiO2.

According to electron tunneling current model in (2-1), four important key parameters have been introduced one by one, (2-2), (2-6), (2-10) and (2-14). As electron tunneling is closely related to its subband energy, Eij, it will be introduced in detail latter.

2.2 Modified Tunneling Current Model for High-K Gate Stacks

For highly scaled devices, thinner oxide induces a larger gate leakage current. In order to maintain device performance in the scaling direction, use of high permittivity is one of the solutions. In addition to dielectric layer change, poly gate is replaced by metal gate and thereby the poly depletion can be eliminated. The band diagram of metal gate/high-K/IL/p-substrate is shown in Fig. 3. Similarly, WKB approximation is employed to build the tunneling current model, along with some parameters modified.

A. Modified WKB Transmission Probability for High-K Stacks (T

WKB

)

To calculate the tunneling probability in high-K case, electron not only goes through the interfacial layer (IL) but also the high-K dielectric layer [4]. Consequently,

T

WKB has two parts in terms of interfacial layer and high-K dielectric:

𝑇

_𝑊𝐾𝐵

= 𝑒𝑥𝑝 ��−2 ∫ 𝜅(𝑥) 𝑑𝑥

₀^𝑡^𝐼𝐿

� + �−2 ∫

_𝑡^𝑡_𝐼𝐿^{ℎ𝑖𝑔ℎ−𝐾}

𝜅(𝑥) 𝑑𝑥 ��

^(2-17)

The above equation can apply to high-K stacks, but it is just one of the several cases.

The band diagram changes with varying gate bias voltage, meaning that lower tunneling barrier height corresponds to higher gate voltage. Three cases are shown in Fig. 4. 𝜙_{𝐼𝐿,𝑐𝑎𝑡ℎ} is denoted as the barrier height for tunneling electrons with reference to oxide conduction band at IL/p-substrate interface and 𝜙_{𝐼𝐿,𝑎𝑛} is the barrier height at high-K/IL interface in interfacial layer. 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ and 𝜙_{ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛} are also the barrier heights with the former at high-K/IL interface in high-K dielectric and the latter at metal-gate/high-K interface. They are calculated by

𝑞𝜙

𝐼𝐿,𝑐𝑎𝑡ℎ

= 𝑞𝜙

𝐼𝐿

− 𝐸

𝑖𝑗 (2-18) 𝑞𝜙_{𝐼𝐿,𝑎𝑛} = 𝑞𝜙_𝐼𝐿− 𝐸_𝑖𝑗 − 𝑞𝐹_𝐼𝐿𝑡_𝐼𝐿 (2-19)

𝑞𝜙

ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ

= 𝑞𝜙

ℎ𝑖𝑔ℎ−𝐾

− 𝐸

𝑖𝑗

− 𝑞𝐹

𝐼𝐿

𝑡

𝐼𝐿 (2-20)

𝑞𝜙

_{ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛}

= 𝑞𝜙

_{ℎ𝑖𝑔ℎ−𝐾}

− 𝐸

_𝑖𝑗

− 𝑞𝐹

_𝐼𝐿

𝑡

_𝐼𝐿

− 𝑞𝐹

_{ℎ𝑖𝑔ℎ−𝐾}

𝑡

_{ℎ𝑖𝑔ℎ−𝐾} (2-21)

By Gauss’ law we can get V_high-K (potential drop across high-K dielectric) easily, The three tunneling cases can be classified by defining the underlying conditions:

Case 1 --- 𝜙𝐼𝐿,𝑐𝑎𝑡ℎ > 0, 𝜙𝐼𝐿,𝑎𝑛 > 0, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ > 0 𝑎𝑛𝑑 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛> 0 Case 2 --- 𝜙_{𝐼𝐿,𝑐𝑎𝑡ℎ} > 0, 𝜙_{𝐼𝐿,𝑎𝑛} > 0, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ > 0 𝑎𝑛𝑑 𝜙_{ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛}≤ 0 Case 3 --- 𝜙𝐼𝐿,𝑐𝑎𝑡ℎ > 0, 𝜙𝐼𝐿,𝑎𝑛 > 0, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ ≤ 0 𝑎𝑛𝑑 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛≤ 0

Substituting the three cases into (2-17), the three conditions of tunneling probability are

B. Modified Reflection Correction Factor for High-K Stacks (T

)

According to the reflection correction factor for SiO2, TR needs to be considered at

unity for metal/high-K dielectric interface and for the interface of high-K gate stacks, so we only consider the reflection at the Si/IL interface in our model. Therefore, the correcting T_R for high-K stacks is as follows:

𝑇 _𝑅 = ^4𝜈 _𝜈

^𝑆𝑖⊥

^{(𝐸) × 𝜈}

^𝐼𝐿

^�𝜙

^{𝐼𝐿,𝑐𝑎𝑡ℎ}

^�

𝑆𝑖⊥2

(𝐸)+𝜈

_𝐼𝐿²

�𝜙

_{𝐼𝐿,𝑐𝑎𝑡ℎ}

�

(2-25)

2.3 Subband Energy Calculation

In this part, the method of calculating the electron subband energy will be introduced. We employ a simplified method to calculate the quantum mechanical effect in the inversion layer of a p-type Si substrate. Four physical values are estimated in this method; they are the charge densities in depletion and inversion, the depletion region band bending, and the inversion layer band bending. Those characteristic parameters of p-type substrate under the inversion conditions are denoted

𝑁𝑑𝑒𝑝 is the depleted space charge;

𝑁_𝑖𝑛𝑣 is the interfacial inversion charge;

𝜙𝑠 is the semiconductor surface potential or surface band bending;

𝜙_𝑑𝑒𝑝 is the band bending due to the depletion charge.

One assumption needs to be used to while simplifying the subband energy model:

the quantum confinement phenomenon of the MOS structure can be treated in a triangular well approximation, so the potential at the semiconductor surface layer follows a linear variation. This approximation has been shown to describe the electron behavior adequately as validated by self-consistent Schrödinger and Poisson equations solving.

The gate voltage induces surface band bending; the inversion charge and depletion

charge each are related to corresponding surface band bending. The total charge per unit area (𝑄) below the MOS gate is the sum of the inversion electron charge(𝑁_𝑖𝑛𝑣) and the depletion charge(𝑁𝑑𝑒𝑝). The total charge from the law of electrostatics is

𝑁

_𝑖𝑛𝑣

+ 𝑁

_𝑑𝑒𝑝

= 𝑄(𝜙

_𝑠

)

(2-26) First, the surface potential is essential for calculating the total charge.

𝜙_𝑑𝑒𝑝 = 𝜙_𝑠−^𝑞𝑁_𝜀^𝑠^𝑧̅^𝑞𝑚

𝑆𝑖𝜀₀ −^𝑘𝑇_𝑞 (2-27) The second term of the right side of (2-27) stems from the influence of inversion charge

𝑁

𝑖𝑛𝑣; the third term ^𝑘𝑇

𝑞

from the gradual transition of the space charge region

into the substrate, and the term

𝜙

_𝑑𝑒𝑝 due to the space charge

𝑁

_𝑑𝑒𝑝^.

𝑁

_𝑑𝑒𝑝

= �

^2𝜀^𝑆𝑖^𝜀⁰^𝜙_𝑞^𝑑𝑒𝑝^𝑁^𝑠𝑢𝑏

(2-28)

𝑧̅_𝑞𝑚 in (2-27) is the average equivalent widths of the quantum confined electron gas, as described by

𝑧̅ _𝑞𝑚 = ∑ ^𝑧 _𝑁

^𝑖𝑗

^𝑁

^𝑖𝑗

𝑖,𝑗

𝑖𝑛𝑣

(2-29) 𝑧_𝑖𝑗 is weighted with the corresponding subband occupation factor Nij, thus constituting the mean quantum mechanical channel width 𝑧̅𝑞𝑚. In this case, the wave functions are given by Airy functions. So the mean subband width 𝑧_𝑖𝑗 is calculated by

𝑧

_𝑖𝑗

= ∫�𝛹

𝑖𝑗

(𝑧)�

𝑧 𝑑𝑧 =

_3𝑞𝜀^2𝐸^𝑖𝑗^𝜀^𝑆𝑖

𝑜𝑥𝐸_𝑜𝑥

(2-30) The energy eigenvalues Eij can be expressed as

𝐸 _𝑖𝑗 = � _2𝑚 ^ℏ

² electric field and the index j is the subband number. Nij, the remaining parameter in

𝑁

_𝑖𝑗

= ∫ 𝐷

_𝐸^∞_𝑖𝑗 𝑖

(𝐸)𝑓(𝐸)𝑑𝐸 =

^𝑚_𝜋ℏ^𝑑𝑖₂

𝑙𝑛 �1 + 𝑒𝑥𝑝 �

^𝐸^𝐹_𝑘𝑇^−𝐸^𝑖𝑗

��

(2-32) where D_i

(E) is the density of states of the subband for two dimentional gas and f(E) is

the Fermi-Dirac occupation factor.

Chapter 3 Physical Model for FinFET

In this chapter, multiple gate devices are introduced, including gate tunneling current and electron energy in double gate and FinFET devices. Fig. 5 reveals that the width of FinFET is insignificant compared to the whole gate length (W_Fin＋2HFin), we can regard FinFET as double gate structure.

There are some changes to the tunneling model because of the different physical structural change from planar to double gate. The equations of depletion charge density and subband energy have to be modified since the Si body part is affected by both the front and back gate.

3.1 Depletion Charge Density Calculation

It is a significant improvement in the double gate structure that the substrate is controlled by two gates (front gate and back gate). Owing to its capability of sensitively influencing the channel, to suppress the short channel effects, the body doping can be decreased. While body thickness is reduced, full depletion in the body happens under the small gate voltage condition. So the task to calculate depletion charge density needs to be considered in two distinct situations:

Case 1 ---

𝐼𝑓 �

^2𝜀^𝑆𝑖^𝜀⁰^𝜙_𝑞^𝑑𝑒𝑝^𝑁^𝑠𝑢𝑏

<

^𝑁^𝑠𝑢𝑏₂^𝑡^{𝑏𝑜𝑑𝑦}

⟹ 𝑁

_𝑑𝑒𝑝

= �

^2𝜀^𝑆𝑖^𝜀⁰^𝜙_𝑞^𝑑𝑒𝑝^𝑁^𝑠𝑢𝑏

Case 2 ---

𝐼𝑓 �

^2𝜀^𝑆𝑖^𝜀⁰^𝜙_𝑞^𝑑𝑒𝑝^𝑁^𝑠𝑢𝑏

>

^𝑁^𝑠𝑢𝑏₂^𝑡^{𝑏𝑜𝑑𝑦}

⟹ 𝑁

_𝑑𝑒𝑝

=

^𝑁^𝑠𝑢𝑏₂^𝑡^{𝑏𝑜𝑑𝑦}

Case 1 is the condition that the channel works in depletion region. In this case, the depletion charge density is calculated by the aforementioned equation (2-28). Case 2

attributed by the doping concentration are totally depleted. Therefore, the depletion charge density is equal to half of the body doping charge density. It is not the total charge density because one gate just controls half of the charge in the channel. As long as the body doping is large enough, full depletion is going to happen later due to large gate voltage needed.

3.2 Subband Energy Calculation for FinFET

In double gate devices, gate leakage current and subthreshold leakage both are affected by the quantization of electron energy. Owing to small body thickness, structure confinement needs to be considered in calculating electron energy. Surface band bending changes the electric field in the substrate, so field confinement is another factor [5],[6]. The energy level associated with the jth subband of the ith valley (longitudinal or transverse) is given by

𝐸

_𝑖𝑗

= �

_2𝑚^ℏ² The first term in (4-1) is field confinement factor and the second is structure confinement one.

η is a fitting factor (theoretically ≈ 2/3), m

i is the electron effective mass at ith valley and tbody is the thickness of body between front gate dielectric and back gate dielectric.

From Fig. 6, it can be observed that, due to the absence of the bulk charge in the double gate device, the surface electric field is negligible below threshold. Therefore, in the double gate device, the electron quantization occurs principally due to the structural confinement below threshold. However, above threshold, an increase in gate voltage increases the electric field (due to higher inversion charge) which also increases the subband energies [7].

(Fig. 7). Evidence to validate the analytical model is given in Fig. 8, which shows that the gate current density values obtained from the numerical simulation and the analytical model are equal. Fig. 9 shows the subband energy in varying body doping concentration, effective oxide thickness and metal work function. We can find that no matter how the characteristics of the device change, the subband energies from analytical model and numerical simulation are nearly identical to each other, valid in the same fitting factors. Only the altered body thickness can change fitting factors.

We obtain the four subband fitting factors of 0.6715, 0.682, 0.67, and 0.68 for 10nm

t

_body (Fig. 10). These fitting factors all approach 2/3 as mentioned in [3],[5],[6].

The subband energy for body thicknesses from 10nm to 50nm all are closely comparable between analytical model and numerical simulation (Fig. 10). Fitting factor versus body thickness is plotted in Fig. 11. The fitting factors symbols for different oxide thicknesess represent the best fitting situations in Fig. 10. We can find that the fitting factor decreases as oxide thickness increases. It can be observed from Fig. 11 that data points are distinguished into two parts, with the first subband below second subband. All of the fitting factors lead to a linear relationship. Now, we have two sets of fitting factors, best fitting factors and linear fitting factors. The former is shown in Fig. 11 by discrete points and the latter by solid linear lines. Then, by using the fitting factors from the linear relation, the resulting subband energy does match the simulated value (Fig. 12). In order to testify the validity of the linear fitting factors, gate current from best factors and linear factors is shown in Fig. 13. The gate current curves in best and linear factors are almost equal as shown in Fig. 13(a) for body thicknesses of 10 and 30 nm. The gate current values for body thickness of 20nm, 40nm and 50nm are not shown explicitly but very small gate current change calculated with linear fitting with respect to the best fitting as shown in Fig. 13(b)

established by means of the linear equation of fitting factors shown in Fig. 11.

3.3 Parameters in FinFET Gate Tunneling Current Model

Transmission probability calculation is the most important part in this physical model. According to (2-24), 𝑚𝐼𝐿, 𝑚ℎ𝑖𝑔ℎ−𝐾, 𝜙𝐼𝐿,𝑎𝑛, 𝜙𝐼𝐿,𝑐𝑎𝑡ℎ, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ and 𝐹_𝐼𝐿, 𝐹_{ℎ𝑖𝑔ℎ−𝐾} are essential for resolving this equation. How to find the tunneling effective masses in interfacial layer (𝑚𝐼𝐿) and high-K layer (𝑚ℎ𝑖𝑔ℎ−𝐾) will be explained later. In order to obtain 𝜙_{𝐼𝐿,𝑎𝑛}, 𝜙_{𝐼𝐿,𝑐𝑎𝑡ℎ}, 𝜙_{ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛} and 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ, 𝜙_𝐼𝐿 and 𝜙ℎ𝑖𝑔ℎ−𝐾 are the two parameters used in the equations from (2-18) to (2-21). The electric field in interfacial layer (𝐹_𝐼𝐿) and high-K dielectric (𝐹_{ℎ𝑖𝑔ℎ−𝐾}) are defined in (2-22) and (2-23).

According to [8],[9], a method of extracting gate material parameters has been proposed, as long as gate current is dominated by direct tunneling or Fowler-Nordheim tunneling (F-N tunneling) from the plot of dlnIg/dVg versus Vg (Fig. 14). The transition of direct tunneling and F-N tunneling across high-K has a peak of dlnIg/dVg, and as a consequence, the position of the peak over can provide a direct estimate of metal work function and high-K electron affinity. From Fig. 14(b) and Fig. 14(c), 𝜙_{ℎ𝑖𝑔ℎ−𝐾} determines the peak position; 𝑚_{ℎ𝑖𝑔ℎ−𝐾} determines the peak height. So, adjusting 𝜙ℎ𝑖𝑔ℎ−𝐾 can shift the fitting curve of dlnIg/dVg versus Vg until the position of the peak is the same as the experimental value. Then, adjusting 𝑚ℎ𝑖𝑔ℎ−𝐾 can change the height of dlnIg/dVg peak until it approaches the experimental value. The parameters related to high-K are determined from the above method. Then, band offset with respect to silicon and the tunneling effective mass in interfacial layer, 𝜙_𝐼𝐿 and 𝑚_𝐼𝐿, can be extracted by fitting gate current versus gate voltage. Higher 𝜙𝐼𝐿 decreases the gate current because the electric barrier height can

𝜙

need more energy to tunnel across the interfacial layer, leading to gate tunneling current drop. Higher 𝑚_𝐼𝐿 also decreases the gate current because the electric effective mass can significantly affect the tunneling probability as shown in equation (2-24). The differential value of the band offset between the anode side and cathode side is negative. It means that the higher the effective mass is, the less likely the tunneling occurs. We can therefore extract the relevant HKMG material parameters by combining conventional Cg-Vg and Ig-Vg curve fittings with the new dlnIg/dVg-Vg curve fitting.

Chapter 4 Metal-Gate/High-K FinFET: Experiment and Fitting

The experimental devices were n-type FinFET with metal-gate/high-K/IL system, as schematically depicted in Fig. 3 in terms of energy band diagram in flat-band condition. Because of the small ratio of top gate width to total fin width, we can regard the FinFET structure as double gate structure, as shown in Fig. 5.

The electron tunneling current from inversion layer was measured with source, drain and bulk tied to ground. The measured terminal current is shown in Fig. 15(a).

The case of Vd = 0.05V is shown in Fig. 15(b). The following process parameters were obtained by Cg-Vg fitting using the Schrödinger-Poisson equation solver Schred [10], as depicted in Fig. 16. The results are that the metal work function Φ_𝑚 is 4.6eV, the EOT is 0.8nm, and the p-type substrate doping concentration 𝑁_𝑠𝑢𝑏 is 1×10¹⁸ cm^-3. Then, we took the permittivity of HfO₂ bases high-K (εk) as the literature value of 22 ε0 [11] and to meet EOT (0.8nm), the permittivity of IL (εIL) is determined to be 6.6 ε0. Corresponding band offsets of IL (ϕIL) to silicon conduction and valence band are therefore 2.44 eV [12].

The gate current was measured with source, drain, and bulk tied to the ground. The measured result has been depicted in Fig. 15(a) versus Vg. In the gate current fitting, the actual electron tunneling current is close to the electron tunneling current from the first and second subband. For the purpose of saving the computation time, we just calculate the first and second subband in this work. Many simplifications are employed in our tunneling simulation, but the results are reasonable as compared with experimental results as depicted in Fig. 17. The tunneling model is constructed by

WKB approximation of electron transmission probability through the high-K stacks.

From the fitting result in Fig. 17, the simulation by our model is not correct for the gate bias below threshold voltage. The reason for this failure can be attributed to the fact that the gate current is not dominated by direct tunneling in threshold region but our tunneling current model is limited to pure tunneling. Another drawback is that a serious deviation occurs at high gate voltage. This is due to the very large difference of permittivity between high-K dielectric (22 ε0) and IL (6.6 ε0). Thus, a gradual transition (intermixing) layer between high-K dielectric and IL needs to be considered

在文檔中金屬閘高介電n型金氧半場效電晶體及鰭式電晶體閘極電子穿隧電流的精確模擬 (頁 13-0)